1/* 2 * Toshiba TC90522 Demodulator 3 * 4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17/* 18 * NOTICE: 19 * This driver is incomplete and lacks init/config of the chips, 20 * as the necessary info is not disclosed. 21 * It assumes that users of this driver (such as a PCI bridge of 22 * DTV receiver cards) properly init and configure the chip 23 * via I2C *before* calling this driver's init() function. 24 * 25 * Currently, PT3 driver is the only one that uses this driver, 26 * and contains init/config code in its firmware. 27 * Thus some part of the code might be dependent on PT3 specific config. 28 */ 29 30#include <linux/kernel.h> 31#include <linux/math64.h> 32#include <linux/dvb/frontend.h> 33#include "dvb_math.h" 34#include "tc90522.h" 35 36#define TC90522_I2C_THRU_REG 0xfe 37 38#define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1) 39 40struct tc90522_state { 41 struct tc90522_config cfg; 42 struct dvb_frontend fe; 43 struct i2c_client *i2c_client; 44 struct i2c_adapter tuner_i2c; 45 46 bool lna; 47}; 48 49struct reg_val { 50 u8 reg; 51 u8 val; 52}; 53 54static int 55reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) 56{ 57 int i, ret; 58 struct i2c_msg msg; 59 60 ret = 0; 61 msg.addr = state->i2c_client->addr; 62 msg.flags = 0; 63 msg.len = 2; 64 for (i = 0; i < num; i++) { 65 msg.buf = (u8 *)®s[i]; 66 ret = i2c_transfer(state->i2c_client->adapter, &msg, 1); 67 if (ret == 0) 68 ret = -EIO; 69 if (ret < 0) 70 return ret; 71 } 72 return 0; 73} 74 75static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len) 76{ 77 struct i2c_msg msgs[2] = { 78 { 79 .addr = state->i2c_client->addr, 80 .flags = 0, 81 .buf = ®, 82 .len = 1, 83 }, 84 { 85 .addr = state->i2c_client->addr, 86 .flags = I2C_M_RD, 87 .buf = val, 88 .len = len, 89 }, 90 }; 91 int ret; 92 93 ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs)); 94 if (ret == ARRAY_SIZE(msgs)) 95 ret = 0; 96 else if (ret >= 0) 97 ret = -EIO; 98 return ret; 99} 100 101static struct tc90522_state *cfg_to_state(struct tc90522_config *c) 102{ 103 return container_of(c, struct tc90522_state, cfg); 104} 105 106 107static int tc90522s_set_tsid(struct dvb_frontend *fe) 108{ 109 struct reg_val set_tsid[] = { 110 { 0x8f, 00 }, 111 { 0x90, 00 } 112 }; 113 114 set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8; 115 set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff; 116 return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid)); 117} 118 119static int tc90522t_set_layers(struct dvb_frontend *fe) 120{ 121 struct reg_val rv; 122 u8 laysel; 123 124 laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07; 125 laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2; 126 rv.reg = 0x71; 127 rv.val = laysel; 128 return reg_write(fe->demodulator_priv, &rv, 1); 129} 130 131/* frontend ops */ 132 133static int tc90522s_read_status(struct dvb_frontend *fe, fe_status_t *status) 134{ 135 struct tc90522_state *state; 136 int ret; 137 u8 reg; 138 139 state = fe->demodulator_priv; 140 ret = reg_read(state, 0xc3, ®, 1); 141 if (ret < 0) 142 return ret; 143 144 *status = 0; 145 if (reg & 0x80) /* input level under min ? */ 146 return 0; 147 *status |= FE_HAS_SIGNAL; 148 149 if (reg & 0x60) /* carrier? */ 150 return 0; 151 *status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC; 152 153 if (reg & 0x10) 154 return 0; 155 if (reg_read(state, 0xc5, ®, 1) < 0 || !(reg & 0x03)) 156 return 0; 157 *status |= FE_HAS_LOCK; 158 return 0; 159} 160 161static int tc90522t_read_status(struct dvb_frontend *fe, fe_status_t *status) 162{ 163 struct tc90522_state *state; 164 int ret; 165 u8 reg; 166 167 state = fe->demodulator_priv; 168 ret = reg_read(state, 0x96, ®, 1); 169 if (ret < 0) 170 return ret; 171 172 *status = 0; 173 if (reg & 0xe0) { 174 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI 175 | FE_HAS_SYNC | FE_HAS_LOCK; 176 return 0; 177 } 178 179 ret = reg_read(state, 0x80, ®, 1); 180 if (ret < 0) 181 return ret; 182 183 if (reg & 0xf0) 184 return 0; 185 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER; 186 187 if (reg & 0x0c) 188 return 0; 189 *status |= FE_HAS_SYNC | FE_HAS_VITERBI; 190 191 if (reg & 0x02) 192 return 0; 193 *status |= FE_HAS_LOCK; 194 return 0; 195} 196 197static const fe_code_rate_t fec_conv_sat[] = { 198 FEC_NONE, /* unused */ 199 FEC_1_2, /* for BPSK */ 200 FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */ 201 FEC_2_3, /* for 8PSK. (trellis code) */ 202}; 203 204static int tc90522s_get_frontend(struct dvb_frontend *fe) 205{ 206 struct tc90522_state *state; 207 struct dtv_frontend_properties *c; 208 struct dtv_fe_stats *stats; 209 int ret, i; 210 int layers; 211 u8 val[10]; 212 u32 cndat; 213 214 state = fe->demodulator_priv; 215 c = &fe->dtv_property_cache; 216 c->delivery_system = SYS_ISDBS; 217 c->symbol_rate = 28860000; 218 219 layers = 0; 220 ret = reg_read(state, 0xe6, val, 5); 221 if (ret == 0) { 222 u8 v; 223 224 c->stream_id = val[0] << 8 | val[1]; 225 226 /* high/single layer */ 227 v = (val[2] & 0x70) >> 4; 228 c->modulation = (v == 7) ? PSK_8 : QPSK; 229 c->fec_inner = fec_conv_sat[v]; 230 c->layer[0].fec = c->fec_inner; 231 c->layer[0].modulation = c->modulation; 232 c->layer[0].segment_count = val[3] & 0x3f; /* slots */ 233 234 /* low layer */ 235 v = (val[2] & 0x07); 236 c->layer[1].fec = fec_conv_sat[v]; 237 if (v == 0) /* no low layer */ 238 c->layer[1].segment_count = 0; 239 else 240 c->layer[1].segment_count = val[4] & 0x3f; /* slots */ 241 /* actually, BPSK if v==1, but not defined in fe_modulation_t */ 242 c->layer[1].modulation = QPSK; 243 layers = (v > 0) ? 2 : 1; 244 } 245 246 /* statistics */ 247 248 stats = &c->strength; 249 stats->len = 0; 250 /* let the connected tuner set RSSI property cache */ 251 if (fe->ops.tuner_ops.get_rf_strength) { 252 u16 dummy; 253 254 fe->ops.tuner_ops.get_rf_strength(fe, &dummy); 255 } 256 257 stats = &c->cnr; 258 stats->len = 1; 259 stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE; 260 cndat = 0; 261 ret = reg_read(state, 0xbc, val, 2); 262 if (ret == 0) 263 cndat = val[0] << 8 | val[1]; 264 if (cndat >= 3000) { 265 u32 p, p4; 266 s64 cn; 267 268 cndat -= 3000; /* cndat: 4.12 fixed point float */ 269 /* 270 * cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3 271 * + 88977 * P^2 - 89565 * P + 58857 272 * (P = sqrt(cndat) / 64) 273 */ 274 /* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed point float */ 275 /* cn = cnr << 3 */ 276 p = int_sqrt(cndat << 16); 277 p4 = cndat * cndat; 278 cn = div64_s64(-16346LL * p4 * p, 10) >> 35; 279 cn += (14341LL * p4) >> 21; 280 cn -= (50259LL * cndat * p) >> 23; 281 cn += (88977LL * cndat) >> 9; 282 cn -= (89565LL * p) >> 11; 283 cn += 58857 << 3; 284 stats->stat[0].svalue = cn >> 3; 285 stats->stat[0].scale = FE_SCALE_DECIBEL; 286 } 287 288 /* per-layer post viterbi BER (or PER? config dependent?) */ 289 stats = &c->post_bit_error; 290 memset(stats, 0, sizeof(*stats)); 291 stats->len = layers; 292 ret = reg_read(state, 0xeb, val, 10); 293 if (ret < 0) 294 for (i = 0; i < layers; i++) 295 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 296 else { 297 for (i = 0; i < layers; i++) { 298 stats->stat[i].scale = FE_SCALE_COUNTER; 299 stats->stat[i].uvalue = val[i * 5] << 16 300 | val[i * 5 + 1] << 8 | val[i * 5 + 2]; 301 } 302 } 303 stats = &c->post_bit_count; 304 memset(stats, 0, sizeof(*stats)); 305 stats->len = layers; 306 if (ret < 0) 307 for (i = 0; i < layers; i++) 308 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 309 else { 310 for (i = 0; i < layers; i++) { 311 stats->stat[i].scale = FE_SCALE_COUNTER; 312 stats->stat[i].uvalue = 313 val[i * 5 + 3] << 8 | val[i * 5 + 4]; 314 stats->stat[i].uvalue *= 204 * 8; 315 } 316 } 317 318 return 0; 319} 320 321 322static const fe_transmit_mode_t tm_conv[] = { 323 TRANSMISSION_MODE_2K, 324 TRANSMISSION_MODE_4K, 325 TRANSMISSION_MODE_8K, 326 0 327}; 328 329static const fe_code_rate_t fec_conv_ter[] = { 330 FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0 331}; 332 333static const fe_modulation_t mod_conv[] = { 334 DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0 335}; 336 337static int tc90522t_get_frontend(struct dvb_frontend *fe) 338{ 339 struct tc90522_state *state; 340 struct dtv_frontend_properties *c; 341 struct dtv_fe_stats *stats; 342 int ret, i; 343 int layers; 344 u8 val[15], mode; 345 u32 cndat; 346 347 state = fe->demodulator_priv; 348 c = &fe->dtv_property_cache; 349 c->delivery_system = SYS_ISDBT; 350 c->bandwidth_hz = 6000000; 351 mode = 1; 352 ret = reg_read(state, 0xb0, val, 1); 353 if (ret == 0) { 354 mode = (val[0] & 0xc0) >> 2; 355 c->transmission_mode = tm_conv[mode]; 356 c->guard_interval = (val[0] & 0x30) >> 4; 357 } 358 359 ret = reg_read(state, 0xb2, val, 6); 360 layers = 0; 361 if (ret == 0) { 362 u8 v; 363 364 c->isdbt_partial_reception = val[0] & 0x01; 365 c->isdbt_sb_mode = (val[0] & 0xc0) == 0x40; 366 367 /* layer A */ 368 v = (val[2] & 0x78) >> 3; 369 if (v == 0x0f) 370 c->layer[0].segment_count = 0; 371 else { 372 layers++; 373 c->layer[0].segment_count = v; 374 c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2]; 375 c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5]; 376 v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7; 377 c->layer[0].interleaving = v; 378 } 379 380 /* layer B */ 381 v = (val[3] & 0x03) << 1 | (val[4] & 0xc0) >> 6; 382 if (v == 0x0f) 383 c->layer[1].segment_count = 0; 384 else { 385 layers++; 386 c->layer[1].segment_count = v; 387 c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5]; 388 c->layer[1].modulation = mod_conv[(val[2] & 0x07)]; 389 c->layer[1].interleaving = (val[3] & 0x1c) >> 2; 390 } 391 392 /* layer C */ 393 v = (val[5] & 0x1e) >> 1; 394 if (v == 0x0f) 395 c->layer[2].segment_count = 0; 396 else { 397 layers++; 398 c->layer[2].segment_count = v; 399 c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)]; 400 c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3]; 401 c->layer[2].interleaving = (val[5] & 0xe0) >> 5; 402 } 403 } 404 405 /* statistics */ 406 407 stats = &c->strength; 408 stats->len = 0; 409 /* let the connected tuner set RSSI property cache */ 410 if (fe->ops.tuner_ops.get_rf_strength) { 411 u16 dummy; 412 413 fe->ops.tuner_ops.get_rf_strength(fe, &dummy); 414 } 415 416 stats = &c->cnr; 417 stats->len = 1; 418 stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE; 419 cndat = 0; 420 ret = reg_read(state, 0x8b, val, 3); 421 if (ret == 0) 422 cndat = val[0] << 16 | val[1] << 8 | val[2]; 423 if (cndat != 0) { 424 u32 p, tmp; 425 s64 cn; 426 427 /* 428 * cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5 429 * (P = 10log10(5505024/cndat)) 430 */ 431 /* cn = cnr << 3 (61.3 fixed point float */ 432 /* p = 10log10(5505024/cndat) << 24 (8.24 fixed point float)*/ 433 p = intlog10(5505024) - intlog10(cndat); 434 p *= 10; 435 436 cn = 24772; 437 cn += div64_s64(43827LL * p, 10) >> 24; 438 tmp = p >> 8; 439 cn += div64_s64(3184LL * tmp * tmp, 10) >> 32; 440 tmp = p >> 13; 441 cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33; 442 tmp = p >> 18; 443 cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24; 444 445 stats->stat[0].svalue = cn >> 3; 446 stats->stat[0].scale = FE_SCALE_DECIBEL; 447 } 448 449 /* per-layer post viterbi BER (or PER? config dependent?) */ 450 stats = &c->post_bit_error; 451 memset(stats, 0, sizeof(*stats)); 452 stats->len = layers; 453 ret = reg_read(state, 0x9d, val, 15); 454 if (ret < 0) 455 for (i = 0; i < layers; i++) 456 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 457 else { 458 for (i = 0; i < layers; i++) { 459 stats->stat[i].scale = FE_SCALE_COUNTER; 460 stats->stat[i].uvalue = val[i * 3] << 16 461 | val[i * 3 + 1] << 8 | val[i * 3 + 2]; 462 } 463 } 464 stats = &c->post_bit_count; 465 memset(stats, 0, sizeof(*stats)); 466 stats->len = layers; 467 if (ret < 0) 468 for (i = 0; i < layers; i++) 469 stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE; 470 else { 471 for (i = 0; i < layers; i++) { 472 stats->stat[i].scale = FE_SCALE_COUNTER; 473 stats->stat[i].uvalue = 474 val[9 + i * 2] << 8 | val[9 + i * 2 + 1]; 475 stats->stat[i].uvalue *= 204 * 8; 476 } 477 } 478 479 return 0; 480} 481 482static const struct reg_val reset_sat = { 0x03, 0x01 }; 483static const struct reg_val reset_ter = { 0x01, 0x40 }; 484 485static int tc90522_set_frontend(struct dvb_frontend *fe) 486{ 487 struct tc90522_state *state; 488 int ret; 489 490 state = fe->demodulator_priv; 491 492 if (fe->ops.tuner_ops.set_params) 493 ret = fe->ops.tuner_ops.set_params(fe); 494 else 495 ret = -ENODEV; 496 if (ret < 0) 497 goto failed; 498 499 if (fe->ops.delsys[0] == SYS_ISDBS) { 500 ret = tc90522s_set_tsid(fe); 501 if (ret < 0) 502 goto failed; 503 ret = reg_write(state, &reset_sat, 1); 504 } else { 505 ret = tc90522t_set_layers(fe); 506 if (ret < 0) 507 goto failed; 508 ret = reg_write(state, &reset_ter, 1); 509 } 510 if (ret < 0) 511 goto failed; 512 513 return 0; 514 515failed: 516 dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n", 517 __func__, fe->dvb->num, fe->id); 518 return ret; 519} 520 521static int tc90522_get_tune_settings(struct dvb_frontend *fe, 522 struct dvb_frontend_tune_settings *settings) 523{ 524 if (fe->ops.delsys[0] == SYS_ISDBS) { 525 settings->min_delay_ms = 250; 526 settings->step_size = 1000; 527 settings->max_drift = settings->step_size * 2; 528 } else { 529 settings->min_delay_ms = 400; 530 settings->step_size = 142857; 531 settings->max_drift = settings->step_size; 532 } 533 return 0; 534} 535 536static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on) 537{ 538 struct reg_val agc_sat[] = { 539 { 0x0a, 0x00 }, 540 { 0x10, 0x30 }, 541 { 0x11, 0x00 }, 542 { 0x03, 0x01 }, 543 }; 544 struct reg_val agc_ter[] = { 545 { 0x25, 0x00 }, 546 { 0x23, 0x4c }, 547 { 0x01, 0x40 }, 548 }; 549 struct tc90522_state *state; 550 struct reg_val *rv; 551 int num; 552 553 state = fe->demodulator_priv; 554 if (fe->ops.delsys[0] == SYS_ISDBS) { 555 agc_sat[0].val = on ? 0xff : 0x00; 556 agc_sat[1].val |= 0x80; 557 agc_sat[1].val |= on ? 0x01 : 0x00; 558 agc_sat[2].val |= on ? 0x40 : 0x00; 559 rv = agc_sat; 560 num = ARRAY_SIZE(agc_sat); 561 } else { 562 agc_ter[0].val = on ? 0x40 : 0x00; 563 agc_ter[1].val |= on ? 0x00 : 0x01; 564 rv = agc_ter; 565 num = ARRAY_SIZE(agc_ter); 566 } 567 return reg_write(state, rv, num); 568} 569 570static const struct reg_val sleep_sat = { 0x17, 0x01 }; 571static const struct reg_val sleep_ter = { 0x03, 0x90 }; 572 573static int tc90522_sleep(struct dvb_frontend *fe) 574{ 575 struct tc90522_state *state; 576 int ret; 577 578 state = fe->demodulator_priv; 579 if (fe->ops.delsys[0] == SYS_ISDBS) 580 ret = reg_write(state, &sleep_sat, 1); 581 else { 582 ret = reg_write(state, &sleep_ter, 1); 583 if (ret == 0 && fe->ops.set_lna && 584 fe->dtv_property_cache.lna == LNA_AUTO) { 585 fe->dtv_property_cache.lna = 0; 586 ret = fe->ops.set_lna(fe); 587 fe->dtv_property_cache.lna = LNA_AUTO; 588 } 589 } 590 if (ret < 0) 591 dev_warn(&state->tuner_i2c.dev, 592 "(%s) failed. [adap%d-fe%d]\n", 593 __func__, fe->dvb->num, fe->id); 594 return ret; 595} 596 597static const struct reg_val wakeup_sat = { 0x17, 0x00 }; 598static const struct reg_val wakeup_ter = { 0x03, 0x80 }; 599 600static int tc90522_init(struct dvb_frontend *fe) 601{ 602 struct tc90522_state *state; 603 int ret; 604 605 /* 606 * Because the init sequence is not public, 607 * the parent device/driver should have init'ed the device before. 608 * just wake up the device here. 609 */ 610 611 state = fe->demodulator_priv; 612 if (fe->ops.delsys[0] == SYS_ISDBS) 613 ret = reg_write(state, &wakeup_sat, 1); 614 else { 615 ret = reg_write(state, &wakeup_ter, 1); 616 if (ret == 0 && fe->ops.set_lna && 617 fe->dtv_property_cache.lna == LNA_AUTO) { 618 fe->dtv_property_cache.lna = 1; 619 ret = fe->ops.set_lna(fe); 620 fe->dtv_property_cache.lna = LNA_AUTO; 621 } 622 } 623 if (ret < 0) { 624 dev_warn(&state->tuner_i2c.dev, 625 "(%s) failed. [adap%d-fe%d]\n", 626 __func__, fe->dvb->num, fe->id); 627 return ret; 628 } 629 630 /* prefer 'all-layers' to 'none' as a default */ 631 if (fe->dtv_property_cache.isdbt_layer_enabled == 0) 632 fe->dtv_property_cache.isdbt_layer_enabled = 7; 633 return tc90522_set_if_agc(fe, true); 634} 635 636 637/* 638 * tuner I2C adapter functions 639 */ 640 641static int 642tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 643{ 644 struct tc90522_state *state; 645 struct i2c_msg *new_msgs; 646 int i, j; 647 int ret, rd_num; 648 u8 wbuf[256]; 649 u8 *p, *bufend; 650 651 if (num <= 0) 652 return -EINVAL; 653 654 rd_num = 0; 655 for (i = 0; i < num; i++) 656 if (msgs[i].flags & I2C_M_RD) 657 rd_num++; 658 new_msgs = kmalloc(sizeof(*new_msgs) * (num + rd_num), GFP_KERNEL); 659 if (!new_msgs) 660 return -ENOMEM; 661 662 state = i2c_get_adapdata(adap); 663 p = wbuf; 664 bufend = wbuf + sizeof(wbuf); 665 for (i = 0, j = 0; i < num; i++, j++) { 666 new_msgs[j].addr = state->i2c_client->addr; 667 new_msgs[j].flags = msgs[i].flags; 668 669 if (msgs[i].flags & I2C_M_RD) { 670 new_msgs[j].flags &= ~I2C_M_RD; 671 if (p + 2 > bufend) 672 break; 673 p[0] = TC90522_I2C_THRU_REG; 674 p[1] = msgs[i].addr << 1 | 0x01; 675 new_msgs[j].buf = p; 676 new_msgs[j].len = 2; 677 p += 2; 678 j++; 679 new_msgs[j].addr = state->i2c_client->addr; 680 new_msgs[j].flags = msgs[i].flags; 681 new_msgs[j].buf = msgs[i].buf; 682 new_msgs[j].len = msgs[i].len; 683 continue; 684 } 685 686 if (p + msgs[i].len + 2 > bufend) 687 break; 688 p[0] = TC90522_I2C_THRU_REG; 689 p[1] = msgs[i].addr << 1; 690 memcpy(p + 2, msgs[i].buf, msgs[i].len); 691 new_msgs[j].buf = p; 692 new_msgs[j].len = msgs[i].len + 2; 693 p += new_msgs[j].len; 694 } 695 696 if (i < num) 697 ret = -ENOMEM; 698 else 699 ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j); 700 if (ret >= 0 && ret < j) 701 ret = -EIO; 702 kfree(new_msgs); 703 return (ret == j) ? num : ret; 704} 705 706static u32 tc90522_functionality(struct i2c_adapter *adap) 707{ 708 return I2C_FUNC_I2C; 709} 710 711static const struct i2c_algorithm tc90522_tuner_i2c_algo = { 712 .master_xfer = &tc90522_master_xfer, 713 .functionality = &tc90522_functionality, 714}; 715 716 717/* 718 * I2C driver functions 719 */ 720 721static const struct dvb_frontend_ops tc90522_ops_sat = { 722 .delsys = { SYS_ISDBS }, 723 .info = { 724 .name = "Toshiba TC90522 ISDB-S module", 725 .frequency_min = 950000, 726 .frequency_max = 2150000, 727 .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO | 728 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | 729 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO, 730 }, 731 732 .init = tc90522_init, 733 .sleep = tc90522_sleep, 734 .set_frontend = tc90522_set_frontend, 735 .get_tune_settings = tc90522_get_tune_settings, 736 737 .get_frontend = tc90522s_get_frontend, 738 .read_status = tc90522s_read_status, 739}; 740 741static const struct dvb_frontend_ops tc90522_ops_ter = { 742 .delsys = { SYS_ISDBT }, 743 .info = { 744 .name = "Toshiba TC90522 ISDB-T module", 745 .frequency_min = 470000000, 746 .frequency_max = 770000000, 747 .frequency_stepsize = 142857, 748 .caps = FE_CAN_INVERSION_AUTO | 749 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 750 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 751 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 752 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | 753 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | 754 FE_CAN_HIERARCHY_AUTO, 755 }, 756 757 .init = tc90522_init, 758 .sleep = tc90522_sleep, 759 .set_frontend = tc90522_set_frontend, 760 .get_tune_settings = tc90522_get_tune_settings, 761 762 .get_frontend = tc90522t_get_frontend, 763 .read_status = tc90522t_read_status, 764}; 765 766 767static int tc90522_probe(struct i2c_client *client, 768 const struct i2c_device_id *id) 769{ 770 struct tc90522_state *state; 771 struct tc90522_config *cfg; 772 const struct dvb_frontend_ops *ops; 773 struct i2c_adapter *adap; 774 int ret; 775 776 state = kzalloc(sizeof(*state), GFP_KERNEL); 777 if (!state) 778 return -ENOMEM; 779 state->i2c_client = client; 780 781 cfg = client->dev.platform_data; 782 memcpy(&state->cfg, cfg, sizeof(state->cfg)); 783 cfg->fe = state->cfg.fe = &state->fe; 784 ops = id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter; 785 memcpy(&state->fe.ops, ops, sizeof(*ops)); 786 state->fe.demodulator_priv = state; 787 788 adap = &state->tuner_i2c; 789 adap->owner = THIS_MODULE; 790 adap->algo = &tc90522_tuner_i2c_algo; 791 adap->dev.parent = &client->dev; 792 strlcpy(adap->name, "tc90522_sub", sizeof(adap->name)); 793 i2c_set_adapdata(adap, state); 794 ret = i2c_add_adapter(adap); 795 if (ret < 0) 796 goto err; 797 cfg->tuner_i2c = state->cfg.tuner_i2c = adap; 798 799 i2c_set_clientdata(client, &state->cfg); 800 dev_info(&client->dev, "Toshiba TC90522 attached.\n"); 801 return 0; 802 803err: 804 kfree(state); 805 return ret; 806} 807 808static int tc90522_remove(struct i2c_client *client) 809{ 810 struct tc90522_state *state; 811 812 state = cfg_to_state(i2c_get_clientdata(client)); 813 i2c_del_adapter(&state->tuner_i2c); 814 kfree(state); 815 return 0; 816} 817 818 819static const struct i2c_device_id tc90522_id[] = { 820 { TC90522_I2C_DEV_SAT, 0 }, 821 { TC90522_I2C_DEV_TER, 1 }, 822 {} 823}; 824MODULE_DEVICE_TABLE(i2c, tc90522_id); 825 826static struct i2c_driver tc90522_driver = { 827 .driver = { 828 .name = "tc90522", 829 }, 830 .probe = tc90522_probe, 831 .remove = tc90522_remove, 832 .id_table = tc90522_id, 833}; 834 835module_i2c_driver(tc90522_driver); 836 837MODULE_DESCRIPTION("Toshiba TC90522 frontend"); 838MODULE_AUTHOR("Akihiro TSUKADA"); 839MODULE_LICENSE("GPL"); 840