41 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
42 static int power_down_qam(struct drxk_state *state);
43 static int set_dvbt_standard(struct drxk_state *state,
45 static int set_qam_standard(struct drxk_state *state,
47 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
49 static int set_dvbt_standard(struct drxk_state *state,
51 static int dvbt_start(struct drxk_state *state);
52 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
54 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
55 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
56 static int switch_antenna_to_qam(struct drxk_state *state);
57 static int switch_antenna_to_dvbt(struct drxk_state *state);
59 static bool is_dvbt(struct drxk_state *state)  in is_dvbt()  argument
61 	return state->m_operation_mode == OM_DVBT;  in is_dvbt()
64 static bool is_qam(struct drxk_state *state)  in is_qam()  argument
66 	return state->m_operation_mode == OM_QAM_ITU_A ||  in is_qam()
67 	    state->m_operation_mode == OM_QAM_ITU_B ||  in is_qam()
68 	    state->m_operation_mode == OM_QAM_ITU_C;  in is_qam()
110 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
113 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
116 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
218 static int drxk_i2c_lock(struct drxk_state *state)  in drxk_i2c_lock()  argument
220 	i2c_lock_adapter(state->i2c);  in drxk_i2c_lock()
221 	state->drxk_i2c_exclusive_lock = true;  in drxk_i2c_lock()
226 static void drxk_i2c_unlock(struct drxk_state *state)  in drxk_i2c_unlock()  argument
228 	if (!state->drxk_i2c_exclusive_lock)  in drxk_i2c_unlock()
231 	i2c_unlock_adapter(state->i2c);  in drxk_i2c_unlock()
232 	state->drxk_i2c_exclusive_lock = false;  in drxk_i2c_unlock()
235 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,  in drxk_i2c_transfer()  argument
238 	if (state->drxk_i2c_exclusive_lock)  in drxk_i2c_transfer()
239 		return __i2c_transfer(state->i2c, msgs, len);  in drxk_i2c_transfer()
241 		return i2c_transfer(state->i2c, msgs, len);  in drxk_i2c_transfer()
244 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)  in i2c_read1()  argument
250 	return drxk_i2c_transfer(state, msgs, 1);  in i2c_read1()
253 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)  in i2c_write()  argument
266 	status = drxk_i2c_transfer(state, &msg, 1);  in i2c_write()
276 static int i2c_read(struct drxk_state *state,  in i2c_read()  argument
287 	status = drxk_i2c_transfer(state, msgs, 2);  in i2c_read()
310 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)  in read16_flags()  argument
313 	u8 adr = state->demod_address, mm1[4], mm2[2], len;  in read16_flags()
315 	if (state->single_master)  in read16_flags()
330 	status = i2c_read(state, adr, mm1, len, mm2, 2);  in read16_flags()
339 static int read16(struct drxk_state *state, u32 reg, u16 *data)  in read16()  argument
341 	return read16_flags(state, reg, data, 0);  in read16()
344 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)  in read32_flags()  argument
347 	u8 adr = state->demod_address, mm1[4], mm2[4], len;  in read32_flags()
349 	if (state->single_master)  in read32_flags()
364 	status = i2c_read(state, adr, mm1, len, mm2, 4);  in read32_flags()
374 static int read32(struct drxk_state *state, u32 reg, u32 *data)  in read32()  argument
376 	return read32_flags(state, reg, data, 0);  in read32()
379 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)  in write16_flags()  argument
381 	u8 adr = state->demod_address, mm[6], len;  in write16_flags()
383 	if (state->single_master)  in write16_flags()
400 	return i2c_write(state, adr, mm, len + 2);  in write16_flags()
403 static int write16(struct drxk_state *state, u32 reg, u16 data)  in write16()  argument
405 	return write16_flags(state, reg, data, 0);  in write16()
408 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)  in write32_flags()  argument
410 	u8 adr = state->demod_address, mm[8], len;  in write32_flags()
412 	if (state->single_master)  in write32_flags()
431 	return i2c_write(state, adr, mm, len + 4);  in write32_flags()
434 static int write32(struct drxk_state *state, u32 reg, u32 data)  in write32()  argument
436 	return write32_flags(state, reg, data, 0);  in write32()
439 static int write_block(struct drxk_state *state, u32 address,  in write_block()  argument
445 	if (state->single_master)  in write_block()
449 		int chunk = blk_size > state->m_chunk_size ?  in write_block()
450 		    state->m_chunk_size : blk_size;  in write_block()
451 		u8 *adr_buf = &state->chunk[0];  in write_block()
461 			if (chunk == state->m_chunk_size)  in write_block()
469 		memcpy(&state->chunk[adr_length], p_block, chunk);  in write_block()
478 		status = i2c_write(state, state->demod_address,  in write_block()
479 				   &state->chunk[0], chunk + adr_length);  in write_block()
496 static int power_up_device(struct drxk_state *state)  in power_up_device()  argument
504 	status = i2c_read1(state, state->demod_address, &data);  in power_up_device()
508 			status = i2c_write(state, state->demod_address,  in power_up_device()
514 			status = i2c_read1(state, state->demod_address,  in power_up_device()
523 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);  in power_up_device()
526 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_up_device()
530 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);  in power_up_device()
534 	state->m_current_power_mode = DRX_POWER_UP;  in power_up_device()
544 static int init_state(struct drxk_state *state)  in init_state()  argument
600 	state->m_has_lna = false;  in init_state()
601 	state->m_has_dvbt = false;  in init_state()
602 	state->m_has_dvbc = false;  in init_state()
603 	state->m_has_atv = false;  in init_state()
604 	state->m_has_oob = false;  in init_state()
605 	state->m_has_audio = false;  in init_state()
607 	if (!state->m_chunk_size)  in init_state()
608 		state->m_chunk_size = 124;  in init_state()
610 	state->m_osc_clock_freq = 0;  in init_state()
611 	state->m_smart_ant_inverted = false;  in init_state()
612 	state->m_b_p_down_open_bridge = false;  in init_state()
615 	state->m_sys_clock_freq = 151875;  in init_state()
618 	state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *  in init_state()
621 	if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)  in init_state()
622 		state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;  in init_state()
623 	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);  in init_state()
625 	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;  in init_state()
627 	state->m_b_power_down = (ul_power_down != 0);  in init_state()
629 	state->m_drxk_a3_patch_code = false;  in init_state()
633 	state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;  in init_state()
634 	state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;  in init_state()
635 	state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;  in init_state()
636 	state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;  in init_state()
637 	state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;  in init_state()
638 	state->m_vsb_pga_cfg = 140;  in init_state()
641 	state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;  in init_state()
642 	state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;  in init_state()
643 	state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;  in init_state()
644 	state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;  in init_state()
645 	state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;  in init_state()
646 	state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;  in init_state()
647 	state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;  in init_state()
648 	state->m_vsb_pre_saw_cfg.reference = 0x07;  in init_state()
649 	state->m_vsb_pre_saw_cfg.use_pre_saw = true;  in init_state()
651 	state->m_Quality83percent = DEFAULT_MER_83;  in init_state()
652 	state->m_Quality93percent = DEFAULT_MER_93;  in init_state()
654 		state->m_Quality83percent = ulQual83;  in init_state()
655 		state->m_Quality93percent = ulQual93;  in init_state()
659 	state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;  in init_state()
660 	state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;  in init_state()
661 	state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;  in init_state()
662 	state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;  in init_state()
663 	state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;  in init_state()
666 	state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;  in init_state()
667 	state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;  in init_state()
668 	state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;  in init_state()
669 	state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;  in init_state()
670 	state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;  in init_state()
671 	state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;  in init_state()
672 	state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;  in init_state()
673 	state->m_atv_pre_saw_cfg.reference = 0x04;  in init_state()
674 	state->m_atv_pre_saw_cfg.use_pre_saw = true;  in init_state()
678 	state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;  in init_state()
679 	state->m_dvbt_rf_agc_cfg.output_level = 0;  in init_state()
680 	state->m_dvbt_rf_agc_cfg.min_output_level = 0;  in init_state()
681 	state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;  in init_state()
682 	state->m_dvbt_rf_agc_cfg.top = 0x2100;  in init_state()
683 	state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;  in init_state()
684 	state->m_dvbt_rf_agc_cfg.speed = 1;  in init_state()
688 	state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;  in init_state()
689 	state->m_dvbt_if_agc_cfg.output_level = 0;  in init_state()
690 	state->m_dvbt_if_agc_cfg.min_output_level = 0;  in init_state()
691 	state->m_dvbt_if_agc_cfg.max_output_level = 9000;  in init_state()
692 	state->m_dvbt_if_agc_cfg.top = 13424;  in init_state()
693 	state->m_dvbt_if_agc_cfg.cut_off_current = 0;  in init_state()
694 	state->m_dvbt_if_agc_cfg.speed = 3;  in init_state()
695 	state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;  in init_state()
696 	state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;  in init_state()
699 	state->m_dvbt_pre_saw_cfg.reference = 4;  in init_state()
700 	state->m_dvbt_pre_saw_cfg.use_pre_saw = false;  in init_state()
703 	state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;  in init_state()
704 	state->m_qam_rf_agc_cfg.output_level = 0;  in init_state()
705 	state->m_qam_rf_agc_cfg.min_output_level = 6023;  in init_state()
706 	state->m_qam_rf_agc_cfg.max_output_level = 27000;  in init_state()
707 	state->m_qam_rf_agc_cfg.top = 0x2380;  in init_state()
708 	state->m_qam_rf_agc_cfg.cut_off_current = 4000;  in init_state()
709 	state->m_qam_rf_agc_cfg.speed = 3;  in init_state()
712 	state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;  in init_state()
713 	state->m_qam_if_agc_cfg.output_level = 0;  in init_state()
714 	state->m_qam_if_agc_cfg.min_output_level = 0;  in init_state()
715 	state->m_qam_if_agc_cfg.max_output_level = 9000;  in init_state()
716 	state->m_qam_if_agc_cfg.top = 0x0511;  in init_state()
717 	state->m_qam_if_agc_cfg.cut_off_current = 0;  in init_state()
718 	state->m_qam_if_agc_cfg.speed = 3;  in init_state()
719 	state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;  in init_state()
720 	state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;  in init_state()
722 	state->m_qam_pga_cfg = 140;  in init_state()
723 	state->m_qam_pre_saw_cfg.reference = 4;  in init_state()
724 	state->m_qam_pre_saw_cfg.use_pre_saw = false;  in init_state()
726 	state->m_operation_mode = OM_NONE;  in init_state()
727 	state->m_drxk_state = DRXK_UNINITIALIZED;  in init_state()
730 	state->m_enable_mpeg_output = true;	/* If TRUE; enable MPEG ouput */  in init_state()
731 	state->m_insert_rs_byte = false;	/* If TRUE; insert RS byte */  in init_state()
732 	state->m_invert_data = false;	/* If TRUE; invert DATA signals */  in init_state()
733 	state->m_invert_err = false;	/* If TRUE; invert ERR signal */  in init_state()
734 	state->m_invert_str = false;	/* If TRUE; invert STR signals */  in init_state()
735 	state->m_invert_val = false;	/* If TRUE; invert VAL signals */  in init_state()
736 	state->m_invert_clk = (ul_invert_ts_clock != 0);	/* If TRUE; invert CLK signals */  in init_state()
741 	state->m_dvbt_bitrate = ul_dvbt_bitrate;  in init_state()
742 	state->m_dvbc_bitrate = ul_dvbc_bitrate;  in init_state()
744 	state->m_ts_data_strength = (ul_ts_data_strength & 0x07);  in init_state()
747 	state->m_mpeg_ts_static_bitrate = 19392658;  in init_state()
748 	state->m_disable_te_ihandling = false;  in init_state()
751 		state->m_insert_rs_byte = true;  in init_state()
753 	state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;  in init_state()
755 		state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;  in init_state()
756 	state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;  in init_state()
758 		state->m_demod_lock_time_out = ul_demod_lock_time_out;  in init_state()
761 	state->m_constellation = DRX_CONSTELLATION_AUTO;  in init_state()
762 	state->m_qam_interleave_mode = DRXK_QAM_I12_J17;  in init_state()
763 	state->m_fec_rs_plen = 204 * 8;	/* fecRsPlen  annex A */  in init_state()
764 	state->m_fec_rs_prescale = 1;  in init_state()
766 	state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;  in init_state()
767 	state->m_agcfast_clip_ctrl_delay = 0;  in init_state()
769 	state->m_gpio_cfg = ul_gpio_cfg;  in init_state()
771 	state->m_b_power_down = false;  in init_state()
772 	state->m_current_power_mode = DRX_POWER_DOWN;  in init_state()
774 	state->m_rfmirror = (ul_rf_mirror == 0);  in init_state()
775 	state->m_if_agc_pol = false;  in init_state()
779 static int drxx_open(struct drxk_state *state)  in drxx_open()  argument
788 	status = write16(state, SCU_RAM_GPIO__A,  in drxx_open()
793 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);  in drxx_open()
796 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in drxx_open()
799 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);  in drxx_open()
802 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);  in drxx_open()
805 	status = write16(state, SIO_TOP_COMM_KEY__A, key);  in drxx_open()
812 static int get_device_capabilities(struct drxk_state *state)  in get_device_capabilities()  argument
823 	status = write16(state, SCU_RAM_GPIO__A,  in get_device_capabilities()
827 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in get_device_capabilities()
830 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);  in get_device_capabilities()
833 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in get_device_capabilities()
843 		state->m_osc_clock_freq = 27000;  in get_device_capabilities()
847 		state->m_osc_clock_freq = 20250;  in get_device_capabilities()
851 		state->m_osc_clock_freq = 20250;  in get_device_capabilities()
861 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);  in get_device_capabilities()
870 		state->m_device_spin = DRXK_SPIN_A1;  in get_device_capabilities()
874 		state->m_device_spin = DRXK_SPIN_A2;  in get_device_capabilities()
878 		state->m_device_spin = DRXK_SPIN_A3;  in get_device_capabilities()
882 		state->m_device_spin = DRXK_SPIN_UNKNOWN;  in get_device_capabilities()
890 		state->m_has_lna = false;  in get_device_capabilities()
891 		state->m_has_oob = false;  in get_device_capabilities()
892 		state->m_has_atv = false;  in get_device_capabilities()
893 		state->m_has_audio = false;  in get_device_capabilities()
894 		state->m_has_dvbt = true;  in get_device_capabilities()
895 		state->m_has_dvbc = true;  in get_device_capabilities()
896 		state->m_has_sawsw = true;  in get_device_capabilities()
897 		state->m_has_gpio2 = false;  in get_device_capabilities()
898 		state->m_has_gpio1 = false;  in get_device_capabilities()
899 		state->m_has_irqn = false;  in get_device_capabilities()
903 		state->m_has_lna = false;  in get_device_capabilities()
904 		state->m_has_oob = false;  in get_device_capabilities()
905 		state->m_has_atv = true;  in get_device_capabilities()
906 		state->m_has_audio = false;  in get_device_capabilities()
907 		state->m_has_dvbt = true;  in get_device_capabilities()
908 		state->m_has_dvbc = false;  in get_device_capabilities()
909 		state->m_has_sawsw = true;  in get_device_capabilities()
910 		state->m_has_gpio2 = true;  in get_device_capabilities()
911 		state->m_has_gpio1 = true;  in get_device_capabilities()
912 		state->m_has_irqn = false;  in get_device_capabilities()
916 		state->m_has_lna = false;  in get_device_capabilities()
917 		state->m_has_oob = false;  in get_device_capabilities()
918 		state->m_has_atv = true;  in get_device_capabilities()
919 		state->m_has_audio = false;  in get_device_capabilities()
920 		state->m_has_dvbt = true;  in get_device_capabilities()
921 		state->m_has_dvbc = false;  in get_device_capabilities()
922 		state->m_has_sawsw = true;  in get_device_capabilities()
923 		state->m_has_gpio2 = true;  in get_device_capabilities()
924 		state->m_has_gpio1 = true;  in get_device_capabilities()
925 		state->m_has_irqn = false;  in get_device_capabilities()
929 		state->m_has_lna = false;  in get_device_capabilities()
930 		state->m_has_oob = false;  in get_device_capabilities()
931 		state->m_has_atv = true;  in get_device_capabilities()
932 		state->m_has_audio = true;  in get_device_capabilities()
933 		state->m_has_dvbt = true;  in get_device_capabilities()
934 		state->m_has_dvbc = false;  in get_device_capabilities()
935 		state->m_has_sawsw = true;  in get_device_capabilities()
936 		state->m_has_gpio2 = true;  in get_device_capabilities()
937 		state->m_has_gpio1 = true;  in get_device_capabilities()
938 		state->m_has_irqn = false;  in get_device_capabilities()
942 		state->m_has_lna = false;  in get_device_capabilities()
943 		state->m_has_oob = false;  in get_device_capabilities()
944 		state->m_has_atv = true;  in get_device_capabilities()
945 		state->m_has_audio = true;  in get_device_capabilities()
946 		state->m_has_dvbt = true;  in get_device_capabilities()
947 		state->m_has_dvbc = true;  in get_device_capabilities()
948 		state->m_has_sawsw = true;  in get_device_capabilities()
949 		state->m_has_gpio2 = true;  in get_device_capabilities()
950 		state->m_has_gpio1 = true;  in get_device_capabilities()
951 		state->m_has_irqn = false;  in get_device_capabilities()
955 		state->m_has_lna = false;  in get_device_capabilities()
956 		state->m_has_oob = false;  in get_device_capabilities()
957 		state->m_has_atv = true;  in get_device_capabilities()
958 		state->m_has_audio = true;  in get_device_capabilities()
959 		state->m_has_dvbt = true;  in get_device_capabilities()
960 		state->m_has_dvbc = true;  in get_device_capabilities()
961 		state->m_has_sawsw = true;  in get_device_capabilities()
962 		state->m_has_gpio2 = true;  in get_device_capabilities()
963 		state->m_has_gpio1 = true;  in get_device_capabilities()
964 		state->m_has_irqn = false;  in get_device_capabilities()
968 		state->m_has_lna = false;  in get_device_capabilities()
969 		state->m_has_oob = false;  in get_device_capabilities()
970 		state->m_has_atv = true;  in get_device_capabilities()
971 		state->m_has_audio = true;  in get_device_capabilities()
972 		state->m_has_dvbt = true;  in get_device_capabilities()
973 		state->m_has_dvbc = true;  in get_device_capabilities()
974 		state->m_has_sawsw = true;  in get_device_capabilities()
975 		state->m_has_gpio2 = true;  in get_device_capabilities()
976 		state->m_has_gpio1 = true;  in get_device_capabilities()
977 		state->m_has_irqn = false;  in get_device_capabilities()
981 		state->m_has_lna = false;  in get_device_capabilities()
982 		state->m_has_oob = false;  in get_device_capabilities()
983 		state->m_has_atv = true;  in get_device_capabilities()
984 		state->m_has_audio = false;  in get_device_capabilities()
985 		state->m_has_dvbt = true;  in get_device_capabilities()
986 		state->m_has_dvbc = true;  in get_device_capabilities()
987 		state->m_has_sawsw = true;  in get_device_capabilities()
988 		state->m_has_gpio2 = true;  in get_device_capabilities()
989 		state->m_has_gpio1 = true;  in get_device_capabilities()
990 		state->m_has_irqn = false;  in get_device_capabilities()
1001 	       state->m_osc_clock_freq / 1000,  in get_device_capabilities()
1002 	       state->m_osc_clock_freq % 1000);  in get_device_capabilities()
1012 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)  in hi_command()  argument
1020 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);  in hi_command()
1028 		    ((state->m_hi_cfg_ctrl) &  in hi_command()
1039 			status = read16(state, SIO_HI_RA_RAM_CMD__A,  in hi_command()
1045 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);  in hi_command()
1054 static int hi_cfg_command(struct drxk_state *state)  in hi_cfg_command()  argument
1060 	mutex_lock(&state->mutex);  in hi_cfg_command()
1062 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,  in hi_cfg_command()
1063 			 state->m_hi_cfg_timeout);  in hi_cfg_command()
1066 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,  in hi_cfg_command()
1067 			 state->m_hi_cfg_ctrl);  in hi_cfg_command()
1070 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,  in hi_cfg_command()
1071 			 state->m_hi_cfg_wake_up_key);  in hi_cfg_command()
1074 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,  in hi_cfg_command()
1075 			 state->m_hi_cfg_bridge_delay);  in hi_cfg_command()
1078 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in hi_cfg_command()
1079 			 state->m_hi_cfg_timing_div);  in hi_cfg_command()
1082 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in hi_cfg_command()
1086 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);  in hi_cfg_command()
1090 	state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;  in hi_cfg_command()
1092 	mutex_unlock(&state->mutex);  in hi_cfg_command()
1098 static int init_hi(struct drxk_state *state)  in init_hi()  argument
1102 	state->m_hi_cfg_wake_up_key = (state->demod_address << 1);  in init_hi()
1103 	state->m_hi_cfg_timeout = 0x96FF;  in init_hi()
1105 	state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;  in init_hi()
1107 	return hi_cfg_command(state);  in init_hi()
1110 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)  in mpegts_configure_pins()  argument
1119 		state->m_enable_parallel ? "parallel" : "serial");  in mpegts_configure_pins()
1122 	status = write16(state, SCU_RAM_GPIO__A,  in mpegts_configure_pins()
1128 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in mpegts_configure_pins()
1134 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);  in mpegts_configure_pins()
1137 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);  in mpegts_configure_pins()
1140 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);  in mpegts_configure_pins()
1143 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);  in mpegts_configure_pins()
1146 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);  in mpegts_configure_pins()
1149 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1152 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1155 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1158 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1161 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1164 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1167 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1173 			((state->m_ts_data_strength <<  in mpegts_configure_pins()
1175 		sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<  in mpegts_configure_pins()
1179 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1183 		if (state->enable_merr_cfg)  in mpegts_configure_pins()
1186 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);  in mpegts_configure_pins()
1189 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);  in mpegts_configure_pins()
1193 		if (state->m_enable_parallel) {  in mpegts_configure_pins()
1195 			status = write16(state, SIO_PDR_MD1_CFG__A,  in mpegts_configure_pins()
1199 			status = write16(state, SIO_PDR_MD2_CFG__A,  in mpegts_configure_pins()
1203 			status = write16(state, SIO_PDR_MD3_CFG__A,  in mpegts_configure_pins()
1207 			status = write16(state, SIO_PDR_MD4_CFG__A,  in mpegts_configure_pins()
1211 			status = write16(state, SIO_PDR_MD5_CFG__A,  in mpegts_configure_pins()
1215 			status = write16(state, SIO_PDR_MD6_CFG__A,  in mpegts_configure_pins()
1219 			status = write16(state, SIO_PDR_MD7_CFG__A,  in mpegts_configure_pins()
1224 			sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<  in mpegts_configure_pins()
1228 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1231 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1234 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1237 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1240 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1243 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1246 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1250 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);  in mpegts_configure_pins()
1253 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1258 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);  in mpegts_configure_pins()
1262 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in mpegts_configure_pins()
1269 static int mpegts_disable(struct drxk_state *state)  in mpegts_disable()  argument
1273 	return mpegts_configure_pins(state, false);  in mpegts_disable()
1276 static int bl_chain_cmd(struct drxk_state *state,  in bl_chain_cmd()  argument
1284 	mutex_lock(&state->mutex);  in bl_chain_cmd()
1285 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);  in bl_chain_cmd()
1288 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);  in bl_chain_cmd()
1291 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);  in bl_chain_cmd()
1294 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_chain_cmd()
1301 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_chain_cmd()
1316 	mutex_unlock(&state->mutex);  in bl_chain_cmd()
1321 static int download_microcode(struct drxk_state *state,  in download_microcode()  argument
1374 		status = write_block(state, address, block_size, p_src);  in download_microcode()
1385 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)  in dvbt_enable_ofdm_token_ring()  argument
1400 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1406 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);  in dvbt_enable_ofdm_token_ring()
1410 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1423 static int mpegts_stop(struct drxk_state *state)  in mpegts_stop()  argument
1432 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_stop()
1436 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_stop()
1441 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);  in mpegts_stop()
1445 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);  in mpegts_stop()
1454 static int scu_command(struct drxk_state *state,  in scu_command()  argument
1477 	mutex_lock(&state->mutex);  in scu_command()
1488 	write_block(state, SCU_RAM_PARAM_0__A -  in scu_command()
1494 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);  in scu_command()
1509 			status = read16(state, SCU_RAM_PARAM_0__A - ii,  in scu_command()
1548 	mutex_unlock(&state->mutex);  in scu_command()
1552 static int set_iqm_af(struct drxk_state *state, bool active)  in set_iqm_af()  argument
1560 	status = read16(state, IQM_AF_STDBY__A, &data);  in set_iqm_af()
1578 	status = write16(state, IQM_AF_STDBY__A, data);  in set_iqm_af()
1586 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)  in ctrl_power_mode()  argument
1619 	if (state->m_current_power_mode == *mode)  in ctrl_power_mode()
1623 	if (state->m_current_power_mode != DRX_POWER_UP) {  in ctrl_power_mode()
1624 		status = power_up_device(state);  in ctrl_power_mode()
1627 		status = dvbt_enable_ofdm_token_ring(state, true);  in ctrl_power_mode()
1644 		switch (state->m_operation_mode) {  in ctrl_power_mode()
1646 			status = mpegts_stop(state);  in ctrl_power_mode()
1649 			status = power_down_dvbt(state, false);  in ctrl_power_mode()
1655 			status = mpegts_stop(state);  in ctrl_power_mode()
1658 			status = power_down_qam(state);  in ctrl_power_mode()
1665 		status = dvbt_enable_ofdm_token_ring(state, false);  in ctrl_power_mode()
1668 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);  in ctrl_power_mode()
1671 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in ctrl_power_mode()
1676 			state->m_hi_cfg_ctrl |=  in ctrl_power_mode()
1678 			status = hi_cfg_command(state);  in ctrl_power_mode()
1683 	state->m_current_power_mode = *mode;  in ctrl_power_mode()
1692 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)  in power_down_dvbt()  argument
1701 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_dvbt()
1706 		status = scu_command(state,  in power_down_dvbt()
1713 		status = scu_command(state,  in power_down_dvbt()
1722 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in power_down_dvbt()
1725 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in power_down_dvbt()
1728 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in power_down_dvbt()
1733 	status = set_iqm_af(state, false);  in power_down_dvbt()
1739 		status = ctrl_power_mode(state, &power_mode);  in power_down_dvbt()
1749 static int setoperation_mode(struct drxk_state *state,  in setoperation_mode()  argument
1762 	status = write16(state, SCU_RAM_GPIO__A,  in setoperation_mode()
1768 	if (state->m_operation_mode == o_mode)  in setoperation_mode()
1771 	switch (state->m_operation_mode) {  in setoperation_mode()
1776 		status = mpegts_stop(state);  in setoperation_mode()
1779 		status = power_down_dvbt(state, true);  in setoperation_mode()
1782 		state->m_operation_mode = OM_NONE;  in setoperation_mode()
1786 		status = mpegts_stop(state);  in setoperation_mode()
1789 		status = power_down_qam(state);  in setoperation_mode()
1792 		state->m_operation_mode = OM_NONE;  in setoperation_mode()
1806 		state->m_operation_mode = o_mode;  in setoperation_mode()
1807 		status = set_dvbt_standard(state, o_mode);  in setoperation_mode()
1814 			(state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');  in setoperation_mode()
1815 		state->m_operation_mode = o_mode;  in setoperation_mode()
1816 		status = set_qam_standard(state, o_mode);  in setoperation_mode()
1830 static int start(struct drxk_state *state, s32 offset_freq,  in start()  argument
1839 	if (state->m_drxk_state != DRXK_STOPPED &&  in start()
1840 		state->m_drxk_state != DRXK_DTV_STARTED)  in start()
1843 	state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);  in start()
1846 		state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;  in start()
1850 	switch (state->m_operation_mode) {  in start()
1854 		status = set_qam(state, i_freqk_hz, offsetk_hz);  in start()
1857 		state->m_drxk_state = DRXK_DTV_STARTED;  in start()
1861 		status = mpegts_stop(state);  in start()
1864 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);  in start()
1867 		status = dvbt_start(state);  in start()
1870 		state->m_drxk_state = DRXK_DTV_STARTED;  in start()
1881 static int shut_down(struct drxk_state *state)  in shut_down()  argument
1885 	mpegts_stop(state);  in shut_down()
1889 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)  in get_lock_status()  argument
1901 	switch (state->m_operation_mode) {  in get_lock_status()
1905 		status = get_qam_lock_status(state, p_lock_status);  in get_lock_status()
1908 		status = get_dvbt_lock_status(state, p_lock_status);  in get_lock_status()
1919 static int mpegts_start(struct drxk_state *state)  in mpegts_start()  argument
1926 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_start()
1930 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_start()
1933 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);  in mpegts_start()
1940 static int mpegts_dto_init(struct drxk_state *state)  in mpegts_dto_init()  argument
1947 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);  in mpegts_dto_init()
1950 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);  in mpegts_dto_init()
1953 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);  in mpegts_dto_init()
1956 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);  in mpegts_dto_init()
1959 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);  in mpegts_dto_init()
1962 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);  in mpegts_dto_init()
1965 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);  in mpegts_dto_init()
1968 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);  in mpegts_dto_init()
1973 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);  in mpegts_dto_init()
1976 	status = write16(state, FEC_OC_SNC_LWM__A, 2);  in mpegts_dto_init()
1979 	status = write16(state, FEC_OC_SNC_HWM__A, 12);  in mpegts_dto_init()
1987 static int mpegts_dto_setup(struct drxk_state *state,  in mpegts_dto_setup()  argument
2007 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);  in mpegts_dto_setup()
2010 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2015 	if (state->m_insert_rs_byte) {  in mpegts_dto_setup()
2026 	if (!state->m_enable_parallel) {  in mpegts_dto_setup()
2033 		max_bit_rate = state->m_dvbt_bitrate;  in mpegts_dto_setup()
2036 		static_clk = state->m_dvbt_static_clk;  in mpegts_dto_setup()
2042 		max_bit_rate = state->m_dvbc_bitrate;  in mpegts_dto_setup()
2043 		static_clk = state->m_dvbc_static_clk;  in mpegts_dto_setup()
2075 		fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)  in mpegts_dto_setup()
2090 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);  in mpegts_dto_setup()
2093 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);  in mpegts_dto_setup()
2096 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);  in mpegts_dto_setup()
2099 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);  in mpegts_dto_setup()
2102 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);  in mpegts_dto_setup()
2105 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2110 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);  in mpegts_dto_setup()
2113 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,  in mpegts_dto_setup()
2117 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);  in mpegts_dto_setup()
2124 static int mpegts_configure_polarity(struct drxk_state *state)  in mpegts_configure_polarity()  argument
2139 	if (state->m_invert_data)  in mpegts_configure_polarity()
2142 	if (state->m_invert_err)  in mpegts_configure_polarity()
2145 	if (state->m_invert_str)  in mpegts_configure_polarity()
2148 	if (state->m_invert_val)  in mpegts_configure_polarity()
2151 	if (state->m_invert_clk)  in mpegts_configure_polarity()
2154 	return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);  in mpegts_configure_polarity()
2159 static int set_agc_rf(struct drxk_state *state,  in set_agc_rf()  argument
2174 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2178 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2181 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2189 		if (state->m_rf_agc_pol)  in set_agc_rf()
2193 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2198 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_rf()
2207 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_rf()
2211 		if (is_dvbt(state))  in set_agc_rf()
2212 			p_if_agc_settings = &state->m_dvbt_if_agc_cfg;  in set_agc_rf()
2213 		else if (is_qam(state))  in set_agc_rf()
2214 			p_if_agc_settings = &state->m_qam_if_agc_cfg;  in set_agc_rf()
2216 			p_if_agc_settings = &state->m_atv_if_agc_cfg;  in set_agc_rf()
2224 			status = write16(state,  in set_agc_rf()
2232 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,  in set_agc_rf()
2238 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,  in set_agc_rf()
2247 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2251 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2256 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2260 		if (state->m_rf_agc_pol)  in set_agc_rf()
2264 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2269 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);  in set_agc_rf()
2274 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,  in set_agc_rf()
2282 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2286 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2291 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2295 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2312 static int set_agc_if(struct drxk_state *state,  in set_agc_if()  argument
2325 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2329 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2333 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2341 		if (state->m_if_agc_pol)  in set_agc_if()
2345 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2350 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_if()
2358 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_if()
2362 		if (is_qam(state))  in set_agc_if()
2363 			p_rf_agc_settings = &state->m_qam_rf_agc_cfg;  in set_agc_if()
2365 			p_rf_agc_settings = &state->m_atv_rf_agc_cfg;  in set_agc_if()
2369 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2378 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2382 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2386 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2394 		if (state->m_if_agc_pol)  in set_agc_if()
2398 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2403 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2412 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2416 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2421 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2425 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2433 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);  in set_agc_if()
2440 static int get_qam_signal_to_noise(struct drxk_state *state,  in get_qam_signal_to_noise()  argument
2455 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);  in get_qam_signal_to_noise()
2461 	switch (state->props.modulation) {  in get_qam_signal_to_noise()
2489 static int get_dvbt_signal_to_noise(struct drxk_state *state,  in get_dvbt_signal_to_noise()  argument
2509 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,  in get_dvbt_signal_to_noise()
2513 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,  in get_dvbt_signal_to_noise()
2517 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,  in get_dvbt_signal_to_noise()
2521 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,  in get_dvbt_signal_to_noise()
2531 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);  in get_dvbt_signal_to_noise()
2540 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,  in get_dvbt_signal_to_noise()
2593 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)  in get_signal_to_noise()  argument
2598 	switch (state->m_operation_mode) {  in get_signal_to_noise()
2600 		return get_dvbt_signal_to_noise(state, p_signal_to_noise);  in get_signal_to_noise()
2603 		return get_qam_signal_to_noise(state, p_signal_to_noise);  in get_signal_to_noise()
2611 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2645 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2648 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2654 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2678 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2690 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2694 		switch (state->props.modulation) {
2725 static int get_quality(struct drxk_state *state, s32 *p_quality)
2729 	switch (state->m_operation_mode) {
2731 		return get_dvbt_quality(state, p_quality);
2733 		return get_dvbc_quality(state, p_quality);
2755 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)  in ConfigureI2CBridge()  argument
2761 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in ConfigureI2CBridge()
2763 	if (state->m_drxk_state == DRXK_POWERED_DOWN)  in ConfigureI2CBridge()
2766 	if (state->no_i2c_bridge)  in ConfigureI2CBridge()
2769 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in ConfigureI2CBridge()
2774 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2779 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2785 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);  in ConfigureI2CBridge()
2793 static int set_pre_saw(struct drxk_state *state,  in set_pre_saw()  argument
2804 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);  in set_pre_saw()
2811 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,  in bl_direct_cmd()  argument
2822 	mutex_lock(&state->mutex);  in bl_direct_cmd()
2823 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);  in bl_direct_cmd()
2826 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);  in bl_direct_cmd()
2829 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);  in bl_direct_cmd()
2832 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);  in bl_direct_cmd()
2835 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);  in bl_direct_cmd()
2838 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_direct_cmd()
2844 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_direct_cmd()
2857 	mutex_unlock(&state->mutex);  in bl_direct_cmd()
2862 static int adc_sync_measurement(struct drxk_state *state, u16 *count)  in adc_sync_measurement()  argument
2870 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);  in adc_sync_measurement()
2873 	status = write16(state, IQM_AF_START_LOCK__A, 1);  in adc_sync_measurement()
2878 	status = read16(state, IQM_AF_PHASE0__A, &data);  in adc_sync_measurement()
2883 	status = read16(state, IQM_AF_PHASE1__A, &data);  in adc_sync_measurement()
2888 	status = read16(state, IQM_AF_PHASE2__A, &data);  in adc_sync_measurement()
2900 static int adc_synchronization(struct drxk_state *state)  in adc_synchronization()  argument
2907 	status = adc_sync_measurement(state, &count);  in adc_synchronization()
2915 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);  in adc_synchronization()
2928 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);  in adc_synchronization()
2931 		status = adc_sync_measurement(state, &count);  in adc_synchronization()
2944 static int set_frequency_shifter(struct drxk_state *state,  in set_frequency_shifter()  argument
2951 	bool tuner_mirror = !state->m_b_mirror_freq_spect;  in set_frequency_shifter()
2956 	u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);  in set_frequency_shifter()
2967 		if ((state->m_operation_mode == OM_QAM_ITU_A) ||  in set_frequency_shifter()
2968 		    (state->m_operation_mode == OM_QAM_ITU_C) ||  in set_frequency_shifter()
2969 		    (state->m_operation_mode == OM_DVBT))  in set_frequency_shifter()
2993 	image_to_select = state->m_rfmirror ^ tuner_mirror ^  in set_frequency_shifter()
2995 	state->m_iqm_fs_rate_ofs =  in set_frequency_shifter()
2999 		state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;  in set_frequency_shifter()
3003 	status = write32(state, IQM_FS_RATE_OFS_LO__A,  in set_frequency_shifter()
3004 			 state->m_iqm_fs_rate_ofs);  in set_frequency_shifter()
3010 static int init_agc(struct drxk_state *state, bool is_dtv)  in init_agc()  argument
3040 	if (!is_qam(state)) {  in init_agc()
3042 		       __func__, state->m_operation_mode);  in init_agc()
3060 	fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;  in init_agc()
3062 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in init_agc()
3067 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);  in init_agc()
3070 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);  in init_agc()
3073 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);  in init_agc()
3076 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);  in init_agc()
3079 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,  in init_agc()
3083 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in init_agc()
3087 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);  in init_agc()
3090 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);  in init_agc()
3093 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);  in init_agc()
3096 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);  in init_agc()
3099 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);  in init_agc()
3102 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);  in init_agc()
3106 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,  in init_agc()
3110 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,  in init_agc()
3114 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);  in init_agc()
3118 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);  in init_agc()
3121 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);  in init_agc()
3124 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);  in init_agc()
3128 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);  in init_agc()
3131 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);  in init_agc()
3134 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);  in init_agc()
3137 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);  in init_agc()
3140 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);  in init_agc()
3143 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);  in init_agc()
3146 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);  in init_agc()
3149 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);  in init_agc()
3152 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);  in init_agc()
3155 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);  in init_agc()
3158 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);  in init_agc()
3161 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);  in init_agc()
3164 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);  in init_agc()
3167 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);  in init_agc()
3170 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);  in init_agc()
3173 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);  in init_agc()
3176 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);  in init_agc()
3179 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);  in init_agc()
3182 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);  in init_agc()
3187 	status = read16(state, SCU_RAM_AGC_KI__A, &data);  in init_agc()
3197 	status = write16(state, SCU_RAM_AGC_KI__A, data);  in init_agc()
3204 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)  in dvbtqam_get_acc_pkt_err()  argument
3210 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in dvbtqam_get_acc_pkt_err()
3212 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,  in dvbtqam_get_acc_pkt_err()
3219 static int dvbt_sc_command(struct drxk_state *state,  in dvbt_sc_command()  argument
3231 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);  in dvbt_sc_command()
3243 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3255 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);  in dvbt_sc_command()
3273 		status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);  in dvbt_sc_command()
3277 		status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);  in dvbt_sc_command()
3282 		status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);  in dvbt_sc_command()
3295 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3302 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);  in dvbt_sc_command()
3319 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));  in dvbt_sc_command()
3339 static int power_up_dvbt(struct drxk_state *state)  in power_up_dvbt()  argument
3345 	status = ctrl_power_mode(state, &power_mode);  in power_up_dvbt()
3351 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)  in dvbt_ctrl_set_inc_enable()  argument
3357 		status = write16(state, IQM_CF_BYPASSDET__A, 0);  in dvbt_ctrl_set_inc_enable()
3359 		status = write16(state, IQM_CF_BYPASSDET__A, 1);  in dvbt_ctrl_set_inc_enable()
3366 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)  in dvbt_ctrl_set_fr_enable()  argument
3374 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,  in dvbt_ctrl_set_fr_enable()
3378 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);  in dvbt_ctrl_set_fr_enable()
3386 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,  in dvbt_ctrl_set_echo_threshold()  argument
3393 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);  in dvbt_ctrl_set_echo_threshold()
3414 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);  in dvbt_ctrl_set_echo_threshold()
3421 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,  in dvbt_ctrl_set_sqi_speed()  argument
3436 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,  in dvbt_ctrl_set_sqi_speed()
3454 static int dvbt_activate_presets(struct drxk_state *state)  in dvbt_activate_presets()  argument
3464 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);  in dvbt_activate_presets()
3467 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);  in dvbt_activate_presets()
3470 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);  in dvbt_activate_presets()
3473 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);  in dvbt_activate_presets()
3476 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,  in dvbt_activate_presets()
3477 			 state->m_dvbt_if_agc_cfg.ingain_tgt_max);  in dvbt_activate_presets()
3494 static int set_dvbt_standard(struct drxk_state *state,  in set_dvbt_standard()  argument
3503 	power_up_dvbt(state);  in set_dvbt_standard()
3505 	switch_antenna_to_dvbt(state);  in set_dvbt_standard()
3507 	status = scu_command(state,  in set_dvbt_standard()
3515 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt_standard()
3522 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt_standard()
3525 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt_standard()
3528 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_dvbt_standard()
3534 	status = write16(state, IQM_AF_UPD_SEL__A, 1);  in set_dvbt_standard()
3538 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_dvbt_standard()
3542 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_dvbt_standard()
3546 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_dvbt_standard()
3549 	status = set_iqm_af(state, true);  in set_dvbt_standard()
3553 	status = write16(state, IQM_AF_AGC_RF__A, 0);  in set_dvbt_standard()
3558 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */  in set_dvbt_standard()
3561 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */  in set_dvbt_standard()
3564 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */  in set_dvbt_standard()
3568 	status = write16(state, IQM_RC_STRETCH__A, 16);  in set_dvbt_standard()
3571 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */  in set_dvbt_standard()
3574 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */  in set_dvbt_standard()
3577 	status = write16(state, IQM_CF_SCALE__A, 1600);  in set_dvbt_standard()
3580 	status = write16(state, IQM_CF_SCALE_SH__A, 0);  in set_dvbt_standard()
3585 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_dvbt_standard()
3588 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */  in set_dvbt_standard()
3592 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,  in set_dvbt_standard()
3597 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */  in set_dvbt_standard()
3600 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);  in set_dvbt_standard()
3604 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);  in set_dvbt_standard()
3607 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_dvbt_standard()
3612 	status = adc_synchronization(state);  in set_dvbt_standard()
3615 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);  in set_dvbt_standard()
3620 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt_standard()
3624 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);  in set_dvbt_standard()
3627 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);  in set_dvbt_standard()
3632 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);  in set_dvbt_standard()
3636 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);  in set_dvbt_standard()
3641 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt_standard()
3645 	if (!state->m_drxk_a3_rom_code) {  in set_dvbt_standard()
3647 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in set_dvbt_standard()
3648 				 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);  in set_dvbt_standard()
3655 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);  in set_dvbt_standard()
3658 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);  in set_dvbt_standard()
3664 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */  in set_dvbt_standard()
3670 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);  in set_dvbt_standard()
3674 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);  in set_dvbt_standard()
3678 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);  in set_dvbt_standard()
3683 	status = mpegts_dto_setup(state, OM_DVBT);  in set_dvbt_standard()
3687 	status = dvbt_activate_presets(state);  in set_dvbt_standard()
3703 static int dvbt_start(struct drxk_state *state)  in dvbt_start()  argument
3713 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,  in dvbt_start()
3719 	status = mpegts_start(state);  in dvbt_start()
3722 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in dvbt_start()
3740 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,  in set_dvbt()  argument
3754 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
3761 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt()
3766 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt()
3769 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt()
3775 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);  in set_dvbt()
3782 	switch (state->props.transmission_mode) {  in set_dvbt()
3796 	switch (state->props.guard_interval) {  in set_dvbt()
3816 	switch (state->props.hierarchy) {  in set_dvbt()
3837 	switch (state->props.modulation) {  in set_dvbt()
3874 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);  in set_dvbt()
3880 	switch (state->props.code_rate_HP) {  in set_dvbt()
3915 	switch (state->props.bandwidth_hz) {  in set_dvbt()
3917 		state->props.bandwidth_hz = 8000000;  in set_dvbt()
3921 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3926 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3930 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3934 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3938 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3945 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3950 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3954 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3958 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3962 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3969 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3974 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3978 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3982 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3986 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
4010 					((state->m_sys_clock_freq *  in set_dvbt()
4023 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);  in set_dvbt()
4034 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_dvbt()
4042 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt()
4047 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);  in set_dvbt()
4050 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);  in set_dvbt()
4055 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
4067 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,  in set_dvbt()
4072 	if (!state->m_drxk_a3_rom_code)  in set_dvbt()
4073 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);  in set_dvbt()
4091 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)  in get_dvbt_lock_status()  argument
4107 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);  in get_dvbt_lock_status()
4113 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);  in get_dvbt_lock_status()
4132 static int power_up_qam(struct drxk_state *state)  in power_up_qam()  argument
4138 	status = ctrl_power_mode(state, &power_mode);  in power_up_qam()
4147 static int power_down_qam(struct drxk_state *state)  in power_down_qam()  argument
4154 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_qam()
4163 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in power_down_qam()
4166 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in power_down_qam()
4173 	status = set_iqm_af(state, false);  in power_down_qam()
4195 static int set_qam_measurement(struct drxk_state *state,  in set_qam_measurement()  argument
4256 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4259 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,  in set_qam_measurement()
4263 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4270 static int set_qam16(struct drxk_state *state)  in set_qam16()  argument
4277 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);  in set_qam16()
4280 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);  in set_qam16()
4283 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);  in set_qam16()
4286 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);  in set_qam16()
4289 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);  in set_qam16()
4292 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);  in set_qam16()
4296 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);  in set_qam16()
4299 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);  in set_qam16()
4302 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);  in set_qam16()
4305 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);  in set_qam16()
4308 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);  in set_qam16()
4311 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam16()
4315 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam16()
4318 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam16()
4321 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam16()
4326 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam16()
4332 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam16()
4335 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam16()
4338 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam16()
4341 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam16()
4344 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam16()
4347 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam16()
4350 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam16()
4353 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam16()
4357 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam16()
4360 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam16()
4363 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam16()
4366 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam16()
4369 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam16()
4372 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam16()
4375 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam16()
4378 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam16()
4381 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);  in set_qam16()
4384 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam16()
4387 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam16()
4390 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam16()
4397 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);  in set_qam16()
4400 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam16()
4403 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);  in set_qam16()
4406 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);  in set_qam16()
4409 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);  in set_qam16()
4412 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);  in set_qam16()
4416 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam16()
4419 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam16()
4422 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);  in set_qam16()
4429 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);  in set_qam16()
4432 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);  in set_qam16()
4435 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);  in set_qam16()
4438 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);  in set_qam16()
4441 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);  in set_qam16()
4444 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);  in set_qam16()
4447 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);  in set_qam16()
4464 static int set_qam32(struct drxk_state *state)  in set_qam32()  argument
4472 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);  in set_qam32()
4475 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);  in set_qam32()
4478 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);  in set_qam32()
4481 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);  in set_qam32()
4484 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);  in set_qam32()
4487 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);  in set_qam32()
4492 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);  in set_qam32()
4495 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);  in set_qam32()
4498 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);  in set_qam32()
4501 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);  in set_qam32()
4504 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam32()
4507 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam32()
4511 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam32()
4514 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam32()
4517 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam32()
4523 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam32()
4531 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam32()
4534 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam32()
4537 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam32()
4540 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam32()
4543 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam32()
4546 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam32()
4549 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam32()
4552 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam32()
4556 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam32()
4559 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam32()
4562 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam32()
4565 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam32()
4568 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam32()
4571 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam32()
4574 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam32()
4577 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam32()
4580 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);  in set_qam32()
4583 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam32()
4586 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam32()
4589 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam32()
4596 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);  in set_qam32()
4599 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam32()
4602 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam32()
4605 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam32()
4608 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);  in set_qam32()
4611 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam32()
4615 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam32()
4618 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam32()
4621 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);  in set_qam32()
4628 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam32()
4631 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);  in set_qam32()
4634 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);  in set_qam32()
4637 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);  in set_qam32()
4640 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);  in set_qam32()
4643 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);  in set_qam32()
4646 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);  in set_qam32()
4660 static int set_qam64(struct drxk_state *state)  in set_qam64()  argument
4667 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);  in set_qam64()
4670 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);  in set_qam64()
4673 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);  in set_qam64()
4676 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);  in set_qam64()
4679 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);  in set_qam64()
4682 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);  in set_qam64()
4687 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);  in set_qam64()
4690 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);  in set_qam64()
4693 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);  in set_qam64()
4696 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);  in set_qam64()
4699 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam64()
4702 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam64()
4706 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam64()
4709 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam64()
4712 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam64()
4717 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam64()
4725 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam64()
4728 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam64()
4731 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam64()
4734 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam64()
4737 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam64()
4740 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam64()
4743 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam64()
4746 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam64()
4750 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam64()
4753 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);  in set_qam64()
4756 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);  in set_qam64()
4759 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam64()
4762 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);  in set_qam64()
4765 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam64()
4768 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam64()
4771 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam64()
4774 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam64()
4777 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam64()
4780 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam64()
4783 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam64()
4790 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);  in set_qam64()
4793 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam64()
4796 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam64()
4799 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);  in set_qam64()
4802 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);  in set_qam64()
4805 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);  in set_qam64()
4809 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam64()
4812 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam64()
4815 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);  in set_qam64()
4822 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam64()
4825 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);  in set_qam64()
4828 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);  in set_qam64()
4831 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);  in set_qam64()
4834 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);  in set_qam64()
4837 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);  in set_qam64()
4840 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);  in set_qam64()
4855 static int set_qam128(struct drxk_state *state)  in set_qam128()  argument
4862 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);  in set_qam128()
4865 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);  in set_qam128()
4868 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);  in set_qam128()
4871 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);  in set_qam128()
4874 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);  in set_qam128()
4877 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);  in set_qam128()
4882 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);  in set_qam128()
4885 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);  in set_qam128()
4888 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);  in set_qam128()
4891 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);  in set_qam128()
4894 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);  in set_qam128()
4897 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam128()
4901 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam128()
4904 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam128()
4907 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam128()
4914 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam128()
4922 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam128()
4925 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam128()
4928 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam128()
4931 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam128()
4934 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam128()
4937 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam128()
4940 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam128()
4943 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam128()
4947 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam128()
4950 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);  in set_qam128()
4953 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);  in set_qam128()
4956 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam128()
4959 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);  in set_qam128()
4962 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);  in set_qam128()
4965 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam128()
4968 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam128()
4971 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);  in set_qam128()
4974 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam128()
4977 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam128()
4980 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam128()
4987 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam128()
4990 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam128()
4993 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam128()
4996 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam128()
4999 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);  in set_qam128()
5002 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam128()
5006 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam128()
5009 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);  in set_qam128()
5013 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam128()
5019 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam128()
5022 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);  in set_qam128()
5025 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);  in set_qam128()
5028 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);  in set_qam128()
5031 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);  in set_qam128()
5034 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);  in set_qam128()
5037 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);  in set_qam128()
5052 static int set_qam256(struct drxk_state *state)  in set_qam256()  argument
5059 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);  in set_qam256()
5062 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);  in set_qam256()
5065 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);  in set_qam256()
5068 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);  in set_qam256()
5071 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);  in set_qam256()
5074 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);  in set_qam256()
5079 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);  in set_qam256()
5082 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);  in set_qam256()
5085 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);  in set_qam256()
5088 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);  in set_qam256()
5091 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);  in set_qam256()
5094 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam256()
5098 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam256()
5101 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam256()
5104 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam256()
5110 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam256()
5118 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam256()
5121 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam256()
5124 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam256()
5127 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam256()
5130 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam256()
5133 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam256()
5136 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam256()
5139 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam256()
5143 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam256()
5146 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);  in set_qam256()
5149 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);  in set_qam256()
5152 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam256()
5155 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);  in set_qam256()
5158 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);  in set_qam256()
5161 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam256()
5164 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam256()
5167 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam256()
5170 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam256()
5173 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam256()
5176 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam256()
5183 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam256()
5186 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam256()
5189 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam256()
5192 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam256()
5195 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);  in set_qam256()
5198 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);  in set_qam256()
5202 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam256()
5205 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam256()
5208 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam256()
5215 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam256()
5218 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);  in set_qam256()
5221 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);  in set_qam256()
5224 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);  in set_qam256()
5227 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);  in set_qam256()
5230 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);  in set_qam256()
5233 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);  in set_qam256()
5248 static int qam_reset_qam(struct drxk_state *state)  in qam_reset_qam()  argument
5255 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in qam_reset_qam()
5259 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in qam_reset_qam()
5276 static int qam_set_symbolrate(struct drxk_state *state)  in qam_set_symbolrate()  argument
5287 	adc_frequency = (state->m_sys_clock_freq * 1000) / 3;  in qam_set_symbolrate()
5290 	if (state->props.symbol_rate <= 1188750)  in qam_set_symbolrate()
5292 	else if (state->props.symbol_rate <= 2377500)  in qam_set_symbolrate()
5294 	else if (state->props.symbol_rate <= 4755000)  in qam_set_symbolrate()
5296 	status = write16(state, IQM_FD_RATESEL__A, ratesel);  in qam_set_symbolrate()
5303 	symb_freq = state->props.symbol_rate * (1 << ratesel);  in qam_set_symbolrate()
5312 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);  in qam_set_symbolrate()
5315 	state->m_iqm_rc_rate = iqm_rc_rate;  in qam_set_symbolrate()
5319 	symb_freq = state->props.symbol_rate;  in qam_set_symbolrate()
5330 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);  in qam_set_symbolrate()
5347 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)  in get_qam_lock_status()  argument
5354 	status = scu_command(state,  in get_qam_lock_status()
5388 static int qam_demodulator_command(struct drxk_state *state,  in qam_demodulator_command()  argument
5395 	set_param_parameters[0] = state->m_constellation;	/* modulation     */  in qam_demodulator_command()
5401 		if (state->m_operation_mode == OM_QAM_ITU_C)  in qam_demodulator_command()
5406 		status = scu_command(state,  in qam_demodulator_command()
5413 		status = scu_command(state,  in qam_demodulator_command()
5419 		if (state->m_operation_mode == OM_QAM_ITU_C)  in qam_demodulator_command()
5429 		status = scu_command(state,  in qam_demodulator_command()
5446 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,  in set_qam()  argument
5451 	int qam_demod_param_count = state->qam_demod_parameter_count;  in set_qam()
5460 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);  in set_qam()
5463 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);  in set_qam()
5466 	status = qam_reset_qam(state);  in set_qam()
5475 	status = qam_set_symbolrate(state);  in set_qam()
5480 	switch (state->props.modulation) {  in set_qam()
5482 		state->m_constellation = DRX_CONSTELLATION_QAM256;  in set_qam()
5486 		state->m_constellation = DRX_CONSTELLATION_QAM64;  in set_qam()
5489 		state->m_constellation = DRX_CONSTELLATION_QAM16;  in set_qam()
5492 		state->m_constellation = DRX_CONSTELLATION_QAM32;  in set_qam()
5495 		state->m_constellation = DRX_CONSTELLATION_QAM128;  in set_qam()
5506 	if (state->qam_demod_parameter_count == 4  in set_qam()
5507 		|| !state->qam_demod_parameter_count) {  in set_qam()
5509 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5515 	if (state->qam_demod_parameter_count == 2  in set_qam()
5516 		|| (!state->qam_demod_parameter_count && status < 0)) {  in set_qam()
5518 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5525 			state->qam_demod_parameter_count,  in set_qam()
5526 			state->microcode_name);  in set_qam()
5528 	} else if (!state->qam_demod_parameter_count) {  in set_qam()
5537 		state->qam_demod_parameter_count = qam_demod_param_count;  in set_qam()
5549 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_qam()
5555 	status = set_qam_measurement(state, state->m_constellation,  in set_qam()
5556 				     state->props.symbol_rate);  in set_qam()
5561 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);  in set_qam()
5564 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);  in set_qam()
5569 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);  in set_qam()
5572 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);  in set_qam()
5575 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);  in set_qam()
5578 	status = write16(state, QAM_LC_MODE__A, 7);  in set_qam()
5582 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);  in set_qam()
5585 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);  in set_qam()
5588 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);  in set_qam()
5591 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);  in set_qam()
5594 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);  in set_qam()
5597 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);  in set_qam()
5600 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);  in set_qam()
5603 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);  in set_qam()
5606 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);  in set_qam()
5609 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);  in set_qam()
5612 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);  in set_qam()
5615 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);  in set_qam()
5618 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);  in set_qam()
5621 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);  in set_qam()
5624 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);  in set_qam()
5629 	status = write16(state, QAM_SY_SP_INV__A,  in set_qam()
5635 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam()
5640 	switch (state->props.modulation) {  in set_qam()
5642 		status = set_qam16(state);  in set_qam()
5645 		status = set_qam32(state);  in set_qam()
5649 		status = set_qam64(state);  in set_qam()
5652 		status = set_qam128(state);  in set_qam()
5655 		status = set_qam256(state);  in set_qam()
5665 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam()
5672 	status = mpegts_dto_setup(state, state->m_operation_mode);  in set_qam()
5677 	status = mpegts_start(state);  in set_qam()
5680 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in set_qam()
5683 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);  in set_qam()
5686 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_qam()
5691 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in set_qam()
5706 static int set_qam_standard(struct drxk_state *state,  in set_qam_standard()  argument
5719 	switch_antenna_to_qam(state);  in set_qam_standard()
5722 	status = power_up_qam(state);  in set_qam_standard()
5726 	status = qam_reset_qam(state);  in set_qam_standard()
5732 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_qam_standard()
5735 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_qam_standard()
5743 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,  in set_qam_standard()
5748 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,  in set_qam_standard()
5754 		status = bl_direct_cmd(state,  in set_qam_standard()
5766 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);  in set_qam_standard()
5769 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);  in set_qam_standard()
5772 	status = write16(state, IQM_CF_MIDTAP__A,  in set_qam_standard()
5777 	status = write16(state, IQM_RC_STRETCH__A, 21);  in set_qam_standard()
5780 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_qam_standard()
5783 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_qam_standard()
5786 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_qam_standard()
5789 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);  in set_qam_standard()
5793 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);  in set_qam_standard()
5796 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);  in set_qam_standard()
5799 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);  in set_qam_standard()
5802 	status = write16(state, IQM_AF_UPD_SEL__A, 0);  in set_qam_standard()
5807 	status = write16(state, IQM_CF_CLP_VAL__A, 500);  in set_qam_standard()
5810 	status = write16(state, IQM_CF_DATATH__A, 1000);  in set_qam_standard()
5813 	status = write16(state, IQM_CF_BYPASSDET__A, 1);  in set_qam_standard()
5816 	status = write16(state, IQM_CF_DET_LCT__A, 0);  in set_qam_standard()
5819 	status = write16(state, IQM_CF_WND_LEN__A, 1);  in set_qam_standard()
5822 	status = write16(state, IQM_CF_PKDTH__A, 1);  in set_qam_standard()
5825 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);  in set_qam_standard()
5830 	status = set_iqm_af(state, true);  in set_qam_standard()
5833 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);  in set_qam_standard()
5838 	status = adc_synchronization(state);  in set_qam_standard()
5843 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);  in set_qam_standard()
5848 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam_standard()
5855 	status = init_agc(state, true);  in set_qam_standard()
5858 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));  in set_qam_standard()
5863 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);  in set_qam_standard()
5866 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);  in set_qam_standard()
5871 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam_standard()
5878 static int write_gpio(struct drxk_state *state)  in write_gpio()  argument
5885 	status = write16(state, SCU_RAM_GPIO__A,  in write_gpio()
5891 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in write_gpio()
5895 	if (state->m_has_sawsw) {  in write_gpio()
5896 		if (state->uio_mask & 0x0001) { /* UIO-1 */  in write_gpio()
5898 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,  in write_gpio()
5899 					 state->m_gpio_cfg);  in write_gpio()
5904 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5907 			if ((state->m_gpio & 0x0001) == 0)  in write_gpio()
5912 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5916 		if (state->uio_mask & 0x0002) { /* UIO-2 */  in write_gpio()
5918 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,  in write_gpio()
5919 					 state->m_gpio_cfg);  in write_gpio()
5924 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5927 			if ((state->m_gpio & 0x0002) == 0)  in write_gpio()
5932 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5936 		if (state->uio_mask & 0x0004) { /* UIO-3 */  in write_gpio()
5938 			status = write16(state, SIO_PDR_GPIO_CFG__A,  in write_gpio()
5939 					 state->m_gpio_cfg);  in write_gpio()
5944 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5947 			if ((state->m_gpio & 0x0004) == 0)  in write_gpio()
5952 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5958 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in write_gpio()
5965 static int switch_antenna_to_qam(struct drxk_state *state)  in switch_antenna_to_qam()  argument
5972 	if (!state->antenna_gpio)  in switch_antenna_to_qam()
5975 	gpio_state = state->m_gpio & state->antenna_gpio;  in switch_antenna_to_qam()
5977 	if (state->antenna_dvbt ^ gpio_state) {  in switch_antenna_to_qam()
5979 		if (state->antenna_dvbt)  in switch_antenna_to_qam()
5980 			state->m_gpio &= ~state->antenna_gpio;  in switch_antenna_to_qam()
5982 			state->m_gpio |= state->antenna_gpio;  in switch_antenna_to_qam()
5983 		status = write_gpio(state);  in switch_antenna_to_qam()
5990 static int switch_antenna_to_dvbt(struct drxk_state *state)  in switch_antenna_to_dvbt()  argument
5997 	if (!state->antenna_gpio)  in switch_antenna_to_dvbt()
6000 	gpio_state = state->m_gpio & state->antenna_gpio;  in switch_antenna_to_dvbt()
6002 	if (!(state->antenna_dvbt ^ gpio_state)) {  in switch_antenna_to_dvbt()
6004 		if (state->antenna_dvbt)  in switch_antenna_to_dvbt()
6005 			state->m_gpio |= state->antenna_gpio;  in switch_antenna_to_dvbt()
6007 			state->m_gpio &= ~state->antenna_gpio;  in switch_antenna_to_dvbt()
6008 		status = write_gpio(state);  in switch_antenna_to_dvbt()
6016 static int power_down_device(struct drxk_state *state)  in power_down_device()  argument
6027 	if (state->m_b_p_down_open_bridge) {  in power_down_device()
6029 		status = ConfigureI2CBridge(state, true);  in power_down_device()
6034 	status = dvbt_enable_ofdm_token_ring(state, false);  in power_down_device()
6038 	status = write16(state, SIO_CC_PWD_MODE__A,  in power_down_device()
6042 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_down_device()
6045 	state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;  in power_down_device()
6046 	status = hi_cfg_command(state);  in power_down_device()
6054 static int init_drxk(struct drxk_state *state)  in init_drxk()  argument
6061 	if ((state->m_drxk_state == DRXK_UNINITIALIZED)) {  in init_drxk()
6062 		drxk_i2c_lock(state);  in init_drxk()
6063 		status = power_up_device(state);  in init_drxk()
6066 		status = drxx_open(state);  in init_drxk()
6070 		status = write16(state, SIO_CC_SOFT_RST__A,  in init_drxk()
6076 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in init_drxk()
6084 		state->m_drxk_a3_patch_code = true;  in init_drxk()
6085 		status = get_device_capabilities(state);  in init_drxk()
6092 		state->m_hi_cfg_bridge_delay =  in init_drxk()
6093 			(u16) ((state->m_osc_clock_freq / 1000) *  in init_drxk()
6096 		if (state->m_hi_cfg_bridge_delay >  in init_drxk()
6098 			state->m_hi_cfg_bridge_delay =  in init_drxk()
6102 		state->m_hi_cfg_bridge_delay +=  in init_drxk()
6103 			state->m_hi_cfg_bridge_delay <<  in init_drxk()
6106 		status = init_hi(state);  in init_drxk()
6111 		if (!(state->m_DRXK_A1_ROM_CODE)  in init_drxk()
6112 			&& !(state->m_DRXK_A2_ROM_CODE))  in init_drxk()
6115 			status = write16(state, SCU_RAM_GPIO__A,  in init_drxk()
6122 		status = mpegts_disable(state);  in init_drxk()
6127 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);  in init_drxk()
6130 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);  in init_drxk()
6135 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6141 		status = write16(state, SIO_BL_COMM_EXEC__A,  in init_drxk()
6145 		status = bl_chain_cmd(state, 0, 6, 100);  in init_drxk()
6149 		if (state->fw) {  in init_drxk()
6150 			status = download_microcode(state, state->fw->data,  in init_drxk()
6151 						   state->fw->size);  in init_drxk()
6157 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6163 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in init_drxk()
6166 		status = drxx_open(state);  in init_drxk()
6173 		status = ctrl_power_mode(state, &power_mode);  in init_drxk()
6188 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,  in init_drxk()
6197 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,  in init_drxk()
6217 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);  in init_drxk()
6223 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);  in init_drxk()
6227 		status = mpegts_dto_init(state);  in init_drxk()
6230 		status = mpegts_stop(state);  in init_drxk()
6233 		status = mpegts_configure_polarity(state);  in init_drxk()
6236 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);  in init_drxk()
6240 		status = write_gpio(state);  in init_drxk()
6244 		state->m_drxk_state = DRXK_STOPPED;  in init_drxk()
6246 		if (state->m_b_power_down) {  in init_drxk()
6247 			status = power_down_device(state);  in init_drxk()
6250 			state->m_drxk_state = DRXK_POWERED_DOWN;  in init_drxk()
6252 			state->m_drxk_state = DRXK_STOPPED;  in init_drxk()
6256 		if (state->m_has_dvbc) {  in init_drxk()
6257 			state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;  in init_drxk()
6258 			state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;  in init_drxk()
6259 			strlcat(state->frontend.ops.info.name, " DVB-C",  in init_drxk()
6260 				sizeof(state->frontend.ops.info.name));  in init_drxk()
6262 		if (state->m_has_dvbt) {  in init_drxk()
6263 			state->frontend.ops.delsys[n++] = SYS_DVBT;  in init_drxk()
6264 			strlcat(state->frontend.ops.info.name, " DVB-T",  in init_drxk()
6265 				sizeof(state->frontend.ops.info.name));  in init_drxk()
6267 		drxk_i2c_unlock(state);  in init_drxk()
6271 		state->m_drxk_state = DRXK_NO_DEV;  in init_drxk()
6272 		drxk_i2c_unlock(state);  in init_drxk()
6282 	struct drxk_state *state = context;  in load_firmware_cb()  local
6287 			state->microcode_name);  in load_firmware_cb()
6289 			state->microcode_name);  in load_firmware_cb()
6290 		state->microcode_name = NULL;  in load_firmware_cb()
6303 	state->fw = fw;  in load_firmware_cb()
6305 	init_drxk(state);  in load_firmware_cb()
6310 	struct drxk_state *state = fe->demodulator_priv;  in drxk_release()  local
6313 	release_firmware(state->fw);  in drxk_release()
6315 	kfree(state);  in drxk_release()
6320 	struct drxk_state *state = fe->demodulator_priv;  in drxk_sleep()  local
6324 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_sleep()
6326 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_sleep()
6329 	shut_down(state);  in drxk_sleep()
6335 	struct drxk_state *state = fe->demodulator_priv;  in drxk_gate_ctrl()  local
6339 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_gate_ctrl()
6342 	return ConfigureI2CBridge(state, enable ? true : false);  in drxk_gate_ctrl()
6349 	struct drxk_state *state = fe->demodulator_priv;  in drxk_set_parameters()  local
6354 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_set_parameters()
6357 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_set_parameters()
6372 	old_delsys = state->props.delivery_system;  in drxk_set_parameters()
6373 	state->props = *p;  in drxk_set_parameters()
6376 		shut_down(state);  in drxk_set_parameters()
6380 			if (!state->m_has_dvbc)  in drxk_set_parameters()
6382 			state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?  in drxk_set_parameters()
6384 			if (state->m_itut_annex_c)  in drxk_set_parameters()
6385 				setoperation_mode(state, OM_QAM_ITU_C);  in drxk_set_parameters()
6387 				setoperation_mode(state, OM_QAM_ITU_A);  in drxk_set_parameters()
6390 			if (!state->m_has_dvbt)  in drxk_set_parameters()
6392 			setoperation_mode(state, OM_DVBT);  in drxk_set_parameters()
6400 	start(state, 0, IF);  in drxk_set_parameters()
6417 static int get_strength(struct drxk_state *state, u64 *strength)  in get_strength()  argument
6432 	if (is_dvbt(state)) {  in get_strength()
6433 		rf_agc = state->m_dvbt_rf_agc_cfg;  in get_strength()
6434 		if_agc = state->m_dvbt_if_agc_cfg;  in get_strength()
6435 	} else if (is_qam(state)) {  in get_strength()
6436 		rf_agc = state->m_qam_rf_agc_cfg;  in get_strength()
6437 		if_agc = state->m_qam_if_agc_cfg;  in get_strength()
6439 		rf_agc = state->m_atv_rf_agc_cfg;  in get_strength()
6440 		if_agc = state->m_atv_if_agc_cfg;  in get_strength()
6445 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);  in get_strength()
6450 		read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);  in get_strength()
6478 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,  in get_strength()
6483 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,  in get_strength()
6521 	struct drxk_state *state = fe->demodulator_priv;  in drxk_get_stats()  local
6534 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_get_stats()
6536 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_get_stats()
6540 	state->fe_status = 0;  in drxk_get_stats()
6541 	get_lock_status(state, &stat);  in drxk_get_stats()
6543 		state->fe_status |= 0x1f;  in drxk_get_stats()
6545 		state->fe_status |= 0x0f;  in drxk_get_stats()
6547 		state->fe_status |= 0x07;  in drxk_get_stats()
6552 	get_strength(state, &c->strength.stat[0].uvalue);  in drxk_get_stats()
6557 		get_signal_to_noise(state, &cnr);  in drxk_get_stats()
6585 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);  in drxk_get_stats()
6590 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);  in drxk_get_stats()
6596 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);  in drxk_get_stats()
6601 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);  in drxk_get_stats()
6606 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);  in drxk_get_stats()
6611 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);  in drxk_get_stats()
6615 	write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in drxk_get_stats()
6644 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_status()  local
6653 	*status = state->fe_status;  in drxk_read_status()
6661 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_signal_strength()  local
6666 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_read_signal_strength()
6668 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_read_signal_strength()
6677 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_snr()  local
6682 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_read_snr()
6684 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_read_snr()
6687 	get_signal_to_noise(state, &snr2);  in drxk_read_snr()
6698 	struct drxk_state *state = fe->demodulator_priv;  in drxk_read_ucblocks()  local
6703 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_read_ucblocks()
6705 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_read_ucblocks()
6708 	dvbtqam_get_acc_pkt_err(state, &err);  in drxk_read_ucblocks()
6716 	struct drxk_state *state = fe->demodulator_priv;  in drxk_get_tune_settings()  local
6721 	if (state->m_drxk_state == DRXK_NO_DEV)  in drxk_get_tune_settings()
6723 	if (state->m_drxk_state == DRXK_UNINITIALIZED)  in drxk_get_tune_settings()
6776 	struct drxk_state *state = NULL;  in drxk_attach()  local
6781 	state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);  in drxk_attach()
6782 	if (!state)  in drxk_attach()
6785 	state->i2c = i2c;  in drxk_attach()
6786 	state->demod_address = adr;  in drxk_attach()
6787 	state->single_master = config->single_master;  in drxk_attach()
6788 	state->microcode_name = config->microcode_name;  in drxk_attach()
6789 	state->qam_demod_parameter_count = config->qam_demod_parameter_count;  in drxk_attach()
6790 	state->no_i2c_bridge = config->no_i2c_bridge;  in drxk_attach()
6791 	state->antenna_gpio = config->antenna_gpio;  in drxk_attach()
6792 	state->antenna_dvbt = config->antenna_dvbt;  in drxk_attach()
6793 	state->m_chunk_size = config->chunk_size;  in drxk_attach()
6794 	state->enable_merr_cfg = config->enable_merr_cfg;  in drxk_attach()
6797 		state->m_dvbt_static_clk = false;  in drxk_attach()
6798 		state->m_dvbc_static_clk = false;  in drxk_attach()
6800 		state->m_dvbt_static_clk = true;  in drxk_attach()
6801 		state->m_dvbc_static_clk = true;  in drxk_attach()
6806 		state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;  in drxk_attach()
6808 		state->m_ts_clockk_strength = 0x06;  in drxk_attach()
6811 		state->m_enable_parallel = true;  in drxk_attach()
6813 		state->m_enable_parallel = false;  in drxk_attach()
6816 	state->uio_mask = config->antenna_gpio;  in drxk_attach()
6819 	if (!state->antenna_dvbt && state->antenna_gpio)  in drxk_attach()
6820 		state->m_gpio |= state->antenna_gpio;  in drxk_attach()
6822 		state->m_gpio &= ~state->antenna_gpio;  in drxk_attach()
6824 	mutex_init(&state->mutex);  in drxk_attach()
6826 	memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));  in drxk_attach()
6827 	state->frontend.demodulator_priv = state;  in drxk_attach()
6829 	init_state(state);  in drxk_attach()
6832 	if (state->microcode_name) {  in drxk_attach()
6835 		status = request_firmware(&fw, state->microcode_name,  in drxk_attach()
6836 					  state->i2c->dev.parent);  in drxk_attach()
6839 		load_firmware_cb(fw, state);  in drxk_attach()
6840 	} else if (init_drxk(state) < 0)  in drxk_attach()
6845 	p = &state->frontend.dtv_property_cache;  in drxk_attach()
6865 	return &state->frontend;  in drxk_attach()
6869 	kfree(state);  in drxk_attach()