Lines Matching refs:state
313 static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data) in s5h1409_writereg() argument
318 struct i2c_msg msg = { .addr = state->config->demod_address, in s5h1409_writereg()
321 ret = i2c_transfer(state->i2c, &msg, 1); in s5h1409_writereg()
330 static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg) in s5h1409_readreg() argument
337 { .addr = state->config->demod_address, .flags = 0, in s5h1409_readreg()
339 { .addr = state->config->demod_address, .flags = I2C_M_RD, in s5h1409_readreg()
342 ret = i2c_transfer(state->i2c, msg, 2); in s5h1409_readreg()
351 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_softreset() local
355 s5h1409_writereg(state, 0xf5, 0); in s5h1409_softreset()
356 s5h1409_writereg(state, 0xf5, 1); in s5h1409_softreset()
357 state->is_qam_locked = 0; in s5h1409_softreset()
358 state->qam_state = QAM_STATE_UNTUNED; in s5h1409_softreset()
363 #define S5H1409_QAM_IF_FREQ (state->config->qam_if)
367 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_if_freq() local
373 s5h1409_writereg(state, 0x87, 0x014b); in s5h1409_set_if_freq()
374 s5h1409_writereg(state, 0x88, 0x0cb5); in s5h1409_set_if_freq()
375 s5h1409_writereg(state, 0x89, 0x03e2); in s5h1409_set_if_freq()
380 s5h1409_writereg(state, 0x87, 0x01be); in s5h1409_set_if_freq()
381 s5h1409_writereg(state, 0x88, 0x0436); in s5h1409_set_if_freq()
382 s5h1409_writereg(state, 0x89, 0x054d); in s5h1409_set_if_freq()
385 state->if_freq = KHz; in s5h1409_set_if_freq()
392 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_spectralinversion() local
397 return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */ in s5h1409_set_spectralinversion()
399 return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */ in s5h1409_set_spectralinversion()
405 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_enable_modulation() local
412 if (state->if_freq != S5H1409_VSB_IF_FREQ) in s5h1409_enable_modulation()
414 s5h1409_writereg(state, 0xf4, 0); in s5h1409_enable_modulation()
420 if (state->if_freq != S5H1409_QAM_IF_FREQ) in s5h1409_enable_modulation()
422 s5h1409_writereg(state, 0xf4, 1); in s5h1409_enable_modulation()
423 s5h1409_writereg(state, 0x85, 0x110); in s5h1409_enable_modulation()
430 state->current_modulation = m; in s5h1409_enable_modulation()
438 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_i2c_gate_ctrl() local
443 return s5h1409_writereg(state, 0xf3, 1); in s5h1409_i2c_gate_ctrl()
445 return s5h1409_writereg(state, 0xf3, 0); in s5h1409_i2c_gate_ctrl()
450 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_gpio() local
455 return s5h1409_writereg(state, 0xe3, in s5h1409_set_gpio()
456 s5h1409_readreg(state, 0xe3) | 0x1100); in s5h1409_set_gpio()
458 return s5h1409_writereg(state, 0xe3, in s5h1409_set_gpio()
459 s5h1409_readreg(state, 0xe3) & 0xfeff); in s5h1409_set_gpio()
464 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_sleep() local
468 return s5h1409_writereg(state, 0xf2, enable); in s5h1409_sleep()
473 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_register_reset() local
477 return s5h1409_writereg(state, 0xfa, 0); in s5h1409_register_reset()
482 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_qam_amhum_mode() local
485 if (state->qam_state < QAM_STATE_INTERLEAVE_SET) { in s5h1409_set_qam_amhum_mode()
491 if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) { in s5h1409_set_qam_amhum_mode()
498 reg = s5h1409_readreg(state, 0xf0); in s5h1409_set_qam_amhum_mode()
503 s5h1409_writereg(state, 0x96, 0x000c); in s5h1409_set_qam_amhum_mode()
505 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) { in s5h1409_set_qam_amhum_mode()
508 s5h1409_writereg(state, 0x93, 0x3130); in s5h1409_set_qam_amhum_mode()
509 s5h1409_writereg(state, 0x9e, 0x2836); in s5h1409_set_qam_amhum_mode()
510 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3; in s5h1409_set_qam_amhum_mode()
513 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) { in s5h1409_set_qam_amhum_mode()
516 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode()
517 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode()
518 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2; in s5h1409_set_qam_amhum_mode()
523 if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) { in s5h1409_set_qam_amhum_mode()
525 s5h1409_writereg(state, 0x96, 0x0008); in s5h1409_set_qam_amhum_mode()
526 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode()
527 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode()
528 state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1; in s5h1409_set_qam_amhum_mode()
535 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_qam_amhum_mode_legacy() local
538 if (state->is_qam_locked) in s5h1409_set_qam_amhum_mode_legacy()
542 reg = s5h1409_readreg(state, 0xf0); in s5h1409_set_qam_amhum_mode_legacy()
546 state->is_qam_locked = 1; in s5h1409_set_qam_amhum_mode_legacy()
549 s5h1409_writereg(state, 0x96, 0x00c); in s5h1409_set_qam_amhum_mode_legacy()
551 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode_legacy()
552 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode_legacy()
554 s5h1409_writereg(state, 0x93, 0x3130); in s5h1409_set_qam_amhum_mode_legacy()
555 s5h1409_writereg(state, 0x9e, 0x2836); in s5h1409_set_qam_amhum_mode_legacy()
559 s5h1409_writereg(state, 0x96, 0x0008); in s5h1409_set_qam_amhum_mode_legacy()
560 s5h1409_writereg(state, 0x93, 0x3332); in s5h1409_set_qam_amhum_mode_legacy()
561 s5h1409_writereg(state, 0x9e, 0x2c37); in s5h1409_set_qam_amhum_mode_legacy()
567 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_qam_interleave_mode() local
570 if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) { in s5h1409_set_qam_interleave_mode()
575 reg = s5h1409_readreg(state, 0xf1); in s5h1409_set_qam_interleave_mode()
579 if (state->qam_state == QAM_STATE_UNTUNED || in s5h1409_set_qam_interleave_mode()
580 state->qam_state == QAM_STATE_TUNING_STARTED) { in s5h1409_set_qam_interleave_mode()
583 reg1 = s5h1409_readreg(state, 0xb2); in s5h1409_set_qam_interleave_mode()
584 reg2 = s5h1409_readreg(state, 0xad); in s5h1409_set_qam_interleave_mode()
586 s5h1409_writereg(state, 0x96, 0x0020); in s5h1409_set_qam_interleave_mode()
587 s5h1409_writereg(state, 0xad, in s5h1409_set_qam_interleave_mode()
589 state->qam_state = QAM_STATE_INTERLEAVE_SET; in s5h1409_set_qam_interleave_mode()
592 if (state->qam_state == QAM_STATE_UNTUNED) { in s5h1409_set_qam_interleave_mode()
595 s5h1409_writereg(state, 0x96, 0x08); in s5h1409_set_qam_interleave_mode()
596 s5h1409_writereg(state, 0xab, in s5h1409_set_qam_interleave_mode()
597 s5h1409_readreg(state, 0xab) | 0x1001); in s5h1409_set_qam_interleave_mode()
598 state->qam_state = QAM_STATE_TUNING_STARTED; in s5h1409_set_qam_interleave_mode()
605 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_qam_interleave_mode_legacy() local
608 reg = s5h1409_readreg(state, 0xf1); in s5h1409_set_qam_interleave_mode_legacy()
612 if (state->qam_state != 2) { in s5h1409_set_qam_interleave_mode_legacy()
613 state->qam_state = 2; in s5h1409_set_qam_interleave_mode_legacy()
614 reg1 = s5h1409_readreg(state, 0xb2); in s5h1409_set_qam_interleave_mode_legacy()
615 reg2 = s5h1409_readreg(state, 0xad); in s5h1409_set_qam_interleave_mode_legacy()
617 s5h1409_writereg(state, 0x96, 0x20); in s5h1409_set_qam_interleave_mode_legacy()
618 s5h1409_writereg(state, 0xad, in s5h1409_set_qam_interleave_mode_legacy()
620 s5h1409_writereg(state, 0xab, in s5h1409_set_qam_interleave_mode_legacy()
621 s5h1409_readreg(state, 0xab) & 0xeffe); in s5h1409_set_qam_interleave_mode_legacy()
624 if (state->qam_state != 1) { in s5h1409_set_qam_interleave_mode_legacy()
625 state->qam_state = 1; in s5h1409_set_qam_interleave_mode_legacy()
626 s5h1409_writereg(state, 0x96, 0x08); in s5h1409_set_qam_interleave_mode_legacy()
627 s5h1409_writereg(state, 0xab, in s5h1409_set_qam_interleave_mode_legacy()
628 s5h1409_readreg(state, 0xab) | 0x1001); in s5h1409_set_qam_interleave_mode_legacy()
637 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_frontend() local
643 state->current_frequency = p->frequency; in s5h1409_set_frontend()
660 if (state->current_modulation != VSB_8) { in s5h1409_set_frontend()
664 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) { in s5h1409_set_frontend()
678 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_set_mpeg_timing() local
683 val = s5h1409_readreg(state, 0xac) & 0xcfff; in s5h1409_set_mpeg_timing()
703 return s5h1409_writereg(state, 0xac, val); in s5h1409_set_mpeg_timing()
712 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_init() local
719 s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data); in s5h1409_init()
722 state->current_modulation = VSB_8; in s5h1409_init()
727 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) { in s5h1409_init()
729 s5h1409_writereg(state, 0x09, 0x0050); in s5h1409_init()
732 s5h1409_writereg(state, 0x21, 0x0001); in s5h1409_init()
733 s5h1409_writereg(state, 0x50, 0x030e); in s5h1409_init()
736 s5h1409_writereg(state, 0x82, 0x0800); in s5h1409_init()
739 if (state->config->output_mode == S5H1409_SERIAL_OUTPUT) in s5h1409_init()
740 s5h1409_writereg(state, 0xab, in s5h1409_init()
741 s5h1409_readreg(state, 0xab) | 0x100); /* Serial */ in s5h1409_init()
743 s5h1409_writereg(state, 0xab, in s5h1409_init()
744 s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */ in s5h1409_init()
746 s5h1409_set_spectralinversion(fe, state->config->inversion); in s5h1409_init()
747 s5h1409_set_if_freq(fe, state->if_freq); in s5h1409_init()
748 s5h1409_set_gpio(fe, state->config->gpio); in s5h1409_init()
749 s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing); in s5h1409_init()
760 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_read_status() local
767 if (state->current_modulation != VSB_8) { in s5h1409_read_status()
771 if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) { in s5h1409_read_status()
778 reg = s5h1409_readreg(state, 0xf1); in s5h1409_read_status()
784 switch (state->config->status_mode) { in s5h1409_read_status()
858 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_read_snr() local
862 switch (state->current_modulation) { in s5h1409_read_snr()
864 reg = s5h1409_readreg(state, 0xf0) & 0xff; in s5h1409_read_snr()
867 reg = s5h1409_readreg(state, 0xf0) & 0xff; in s5h1409_read_snr()
870 reg = s5h1409_readreg(state, 0xf1) & 0x3ff; in s5h1409_read_snr()
916 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_read_ucblocks() local
918 *ucblocks = s5h1409_readreg(state, 0xb5); in s5h1409_read_ucblocks()
931 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_get_frontend() local
933 p->frequency = state->current_frequency; in s5h1409_get_frontend()
934 p->modulation = state->current_modulation; in s5h1409_get_frontend()
948 struct s5h1409_state *state = fe->demodulator_priv; in s5h1409_release() local
949 kfree(state); in s5h1409_release()
957 struct s5h1409_state *state = NULL; in s5h1409_attach() local
961 state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL); in s5h1409_attach()
962 if (state == NULL) in s5h1409_attach()
966 state->config = config; in s5h1409_attach()
967 state->i2c = i2c; in s5h1409_attach()
968 state->current_modulation = 0; in s5h1409_attach()
969 state->if_freq = S5H1409_VSB_IF_FREQ; in s5h1409_attach()
972 reg = s5h1409_readreg(state, 0x04); in s5h1409_attach()
977 memcpy(&state->frontend.ops, &s5h1409_ops, in s5h1409_attach()
979 state->frontend.demodulator_priv = state; in s5h1409_attach()
981 if (s5h1409_init(&state->frontend) != 0) { in s5h1409_attach()
988 s5h1409_i2c_gate_ctrl(&state->frontend, 1); in s5h1409_attach()
990 return &state->frontend; in s5h1409_attach()
993 kfree(state); in s5h1409_attach()