Lines Matching refs:state
65 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
79 static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg) in s5h1420_readreg() argument
84 { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 }, in s5h1420_readreg()
85 { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 }, in s5h1420_readreg()
86 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 }, in s5h1420_readreg()
90 b[1] = state->shadow[(reg - 1) & 0xff]; in s5h1420_readreg()
92 if (state->config->repeated_start_workaround) { in s5h1420_readreg()
93 ret = i2c_transfer(state->i2c, msg, 3); in s5h1420_readreg()
97 ret = i2c_transfer(state->i2c, &msg[1], 1); in s5h1420_readreg()
100 ret = i2c_transfer(state->i2c, &msg[2], 1); in s5h1420_readreg()
110 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data) in s5h1420_writereg() argument
113 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; in s5h1420_writereg()
117 err = i2c_transfer(state->i2c, &msg, 1); in s5h1420_writereg()
122 state->shadow[reg] = data; in s5h1420_writereg()
129 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_set_voltage() local
135 s5h1420_writereg(state, 0x3c, in s5h1420_set_voltage()
136 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02); in s5h1420_set_voltage()
140 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03); in s5h1420_set_voltage()
144 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd); in s5h1420_set_voltage()
154 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_set_tone() local
159 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
160 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08); in s5h1420_set_tone()
164 s5h1420_writereg(state, 0x3b, in s5h1420_set_tone()
165 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01); in s5h1420_set_tone()
176 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_send_master_cmd() local
187 val = s5h1420_readreg(state, 0x3b); in s5h1420_send_master_cmd()
188 s5h1420_writereg(state, 0x3b, 0x02); in s5h1420_send_master_cmd()
193 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]); in s5h1420_send_master_cmd()
197 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | in s5h1420_send_master_cmd()
203 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) in s5h1420_send_master_cmd()
212 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_master_cmd()
221 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_recv_slave_reply() local
229 val = s5h1420_readreg(state, 0x3b); in s5h1420_recv_slave_reply()
230 …s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive … in s5h1420_recv_slave_reply()
236 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */ in s5h1420_recv_slave_reply()
248 if (s5h1420_readreg(state, 0x49)) { in s5h1420_recv_slave_reply()
254 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4; in s5h1420_recv_slave_reply()
263 reply->msg[i] = s5h1420_readreg(state, 0x3d + i); in s5h1420_recv_slave_reply()
268 s5h1420_writereg(state, 0x3b, val); in s5h1420_recv_slave_reply()
275 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_send_burst() local
281 val = s5h1420_readreg(state, 0x3b); in s5h1420_send_burst()
282 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01); in s5h1420_send_burst()
286 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04); in s5h1420_send_burst()
291 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08); in s5h1420_send_burst()
296 if (!(s5h1420_readreg(state, 0x3b) & 0x08)) in s5h1420_send_burst()
305 s5h1420_writereg(state, 0x3b, val); in s5h1420_send_burst()
310 static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state) in s5h1420_get_status_bits() argument
315 val = s5h1420_readreg(state, 0x14); in s5h1420_get_status_bits()
320 val = s5h1420_readreg(state, 0x36); in s5h1420_get_status_bits()
333 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_status() local
342 *status = s5h1420_get_status_bits(state); in s5h1420_read_status()
347 val = s5h1420_readreg(state, Vit10); in s5h1420_read_status()
350 s5h1420_writereg(state, Vit09, 0x13); in s5h1420_read_status()
352 s5h1420_writereg(state, Vit09, 0x1b); in s5h1420_read_status()
356 *status = s5h1420_get_status_bits(state); in s5h1420_read_status()
361 if ((*status & FE_HAS_LOCK) && !state->postlocked) { in s5h1420_read_status()
364 u32 tmp = s5h1420_getsymbolrate(state); in s5h1420_read_status()
365 switch (s5h1420_readreg(state, Vit10) & 0x07) { in s5h1420_read_status()
378 tmp = state->fclk / tmp; in s5h1420_read_status()
400 s5h1420_writereg(state, FEC01, 0x18); in s5h1420_read_status()
401 s5h1420_writereg(state, FEC01, 0x10); in s5h1420_read_status()
402 s5h1420_writereg(state, FEC01, val); in s5h1420_read_status()
405 val = s5h1420_readreg(state, Mpeg02); in s5h1420_read_status()
406 s5h1420_writereg(state, Mpeg02, val | (1 << 6)); in s5h1420_read_status()
409 val = s5h1420_readreg(state, QPSK01) & 0x7f; in s5h1420_read_status()
410 s5h1420_writereg(state, QPSK01, val); in s5h1420_read_status()
414 if (s5h1420_getsymbolrate(state) >= 20000000) { in s5h1420_read_status()
415 s5h1420_writereg(state, Loop04, 0x8a); in s5h1420_read_status()
416 s5h1420_writereg(state, Loop05, 0x6a); in s5h1420_read_status()
418 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_read_status()
419 s5h1420_writereg(state, Loop05, 0x27); in s5h1420_read_status()
423 state->postlocked = 1; in s5h1420_read_status()
433 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_ber() local
435 s5h1420_writereg(state, 0x46, 0x1d); in s5h1420_read_ber()
438 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); in s5h1420_read_ber()
445 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_signal_strength() local
447 u8 val = s5h1420_readreg(state, 0x15); in s5h1420_read_signal_strength()
456 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_read_ucblocks() local
458 s5h1420_writereg(state, 0x46, 0x1f); in s5h1420_read_ucblocks()
461 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47); in s5h1420_read_ucblocks()
466 static void s5h1420_reset(struct s5h1420_state* state) in s5h1420_reset() argument
469 s5h1420_writereg (state, 0x01, 0x08); in s5h1420_reset()
470 s5h1420_writereg (state, 0x01, 0x00); in s5h1420_reset()
474 static void s5h1420_setsymbolrate(struct s5h1420_state* state, in s5h1420_setsymbolrate() argument
485 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
489 v = s5h1420_readreg(state, Loop01); in s5h1420_setsymbolrate()
490 s5h1420_writereg(state, Loop01, v & 0x7f); in s5h1420_setsymbolrate()
491 s5h1420_writereg(state, Tnco01, val >> 16); in s5h1420_setsymbolrate()
492 s5h1420_writereg(state, Tnco02, val >> 8); in s5h1420_setsymbolrate()
493 s5h1420_writereg(state, Tnco03, val & 0xff); in s5h1420_setsymbolrate()
494 s5h1420_writereg(state, Loop01, v | 0x80); in s5h1420_setsymbolrate()
498 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state) in s5h1420_getsymbolrate() argument
500 return state->symbol_rate; in s5h1420_getsymbolrate()
503 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset) in s5h1420_setfreqoffset() argument
512 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); in s5h1420_setfreqoffset()
516 v = s5h1420_readreg(state, Loop01); in s5h1420_setfreqoffset()
517 s5h1420_writereg(state, Loop01, v & 0xbf); in s5h1420_setfreqoffset()
518 s5h1420_writereg(state, Pnco01, val >> 16); in s5h1420_setfreqoffset()
519 s5h1420_writereg(state, Pnco02, val >> 8); in s5h1420_setfreqoffset()
520 s5h1420_writereg(state, Pnco03, val & 0xff); in s5h1420_setfreqoffset()
521 s5h1420_writereg(state, Loop01, v | 0x40); in s5h1420_setfreqoffset()
525 static int s5h1420_getfreqoffset(struct s5h1420_state* state) in s5h1420_getfreqoffset() argument
529 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08); in s5h1420_getfreqoffset()
530 val = s5h1420_readreg(state, 0x0e) << 16; in s5h1420_getfreqoffset()
531 val |= s5h1420_readreg(state, 0x0f) << 8; in s5h1420_getfreqoffset()
532 val |= s5h1420_readreg(state, 0x10); in s5h1420_getfreqoffset()
533 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7); in s5h1420_getfreqoffset()
540 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
545 static void s5h1420_setfec_inversion(struct s5h1420_state* state, in s5h1420_setfec_inversion() argument
554 inversion = state->config->invert ? 0x08 : 0; in s5h1420_setfec_inversion()
556 inversion = state->config->invert ? 0 : 0x08; in s5h1420_setfec_inversion()
593 s5h1420_writereg(state, Vit08, vit08); in s5h1420_setfec_inversion()
594 s5h1420_writereg(state, Vit09, vit09); in s5h1420_setfec_inversion()
598 static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state) in s5h1420_getfec() argument
600 switch(s5h1420_readreg(state, 0x32) & 0x07) { in s5h1420_getfec()
623 static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state) in s5h1420_getinversion() argument
625 if (s5h1420_readreg(state, 0x32) & 0x08) in s5h1420_getinversion()
634 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_set_frontend() local
642 frequency_delta = p->frequency - state->tunedfreq; in s5h1420_set_frontend()
646 (state->fec_inner == p->fec_inner) && in s5h1420_set_frontend()
647 (state->symbol_rate == p->symbol_rate)) { in s5h1420_set_frontend()
657 s5h1420_setfreqoffset(state, p->frequency - tmp); in s5h1420_set_frontend()
659 s5h1420_setfreqoffset(state, 0); in s5h1420_set_frontend()
667 s5h1420_reset(state); in s5h1420_set_frontend()
671 state->fclk = 80000000; in s5h1420_set_frontend()
673 state->fclk = 59000000; in s5h1420_set_frontend()
675 state->fclk = 86000000; in s5h1420_set_frontend()
677 state->fclk = 88000000; in s5h1420_set_frontend()
679 state->fclk = 44000000; in s5h1420_set_frontend()
681 …dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1)… in s5h1420_set_frontend()
682 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8); in s5h1420_set_frontend()
683 s5h1420_writereg(state, PLL02, 0x40); in s5h1420_set_frontend()
684 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); in s5h1420_set_frontend()
688 s5h1420_writereg(state, QPSK01, 0xae | 0x10); in s5h1420_set_frontend()
690 s5h1420_writereg(state, QPSK01, 0xac | 0x10); in s5h1420_set_frontend()
693 s5h1420_writereg(state, CON_1, 0x00); in s5h1420_set_frontend()
694 s5h1420_writereg(state, QPSK02, 0x00); in s5h1420_set_frontend()
695 s5h1420_writereg(state, Pre01, 0xb0); in s5h1420_set_frontend()
697 s5h1420_writereg(state, Loop01, 0xF0); in s5h1420_set_frontend()
698 s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */ in s5h1420_set_frontend()
699 s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */ in s5h1420_set_frontend()
701 s5h1420_writereg(state, Loop04, 0x79); in s5h1420_set_frontend()
703 s5h1420_writereg(state, Loop04, 0x58); in s5h1420_set_frontend()
704 s5h1420_writereg(state, Loop05, 0x6b); in s5h1420_set_frontend()
707 s5h1420_writereg(state, Post01, (0 << 6) | 0x10); in s5h1420_set_frontend()
709 s5h1420_writereg(state, Post01, (1 << 6) | 0x10); in s5h1420_set_frontend()
711 s5h1420_writereg(state, Post01, (3 << 6) | 0x10); in s5h1420_set_frontend()
713 s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */ in s5h1420_set_frontend()
715 s5h1420_writereg(state, Sync01, 0x33); in s5h1420_set_frontend()
716 s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity); in s5h1420_set_frontend()
717 s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */ in s5h1420_set_frontend()
718 s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */ in s5h1420_set_frontend()
720 s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */ in s5h1420_set_frontend()
721 s5h1420_writereg(state, DiS03, 0x00); in s5h1420_set_frontend()
722 s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */ in s5h1420_set_frontend()
729 s5h1420_setfreqoffset(state, 0); in s5h1420_set_frontend()
733 s5h1420_setsymbolrate(state, p); in s5h1420_set_frontend()
734 s5h1420_setfec_inversion(state, p); in s5h1420_set_frontend()
737 s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1); in s5h1420_set_frontend()
739 state->fec_inner = p->fec_inner; in s5h1420_set_frontend()
740 state->symbol_rate = p->symbol_rate; in s5h1420_set_frontend()
741 state->postlocked = 0; in s5h1420_set_frontend()
742 state->tunedfreq = p->frequency; in s5h1420_set_frontend()
751 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_get_frontend() local
753 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state); in s5h1420_get_frontend()
754 p->inversion = s5h1420_getinversion(state); in s5h1420_get_frontend()
755 p->symbol_rate = s5h1420_getsymbolrate(state); in s5h1420_get_frontend()
756 p->fec_inner = s5h1420_getfec(state); in s5h1420_get_frontend()
796 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_i2c_gate_ctrl() local
799 return s5h1420_writereg(state, 0x02, state->CON_1_val | 1); in s5h1420_i2c_gate_ctrl()
801 return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe); in s5h1420_i2c_gate_ctrl()
806 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_init() local
809 state->CON_1_val = state->config->serial_mpeg << 4; in s5h1420_init()
810 s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_init()
812 s5h1420_reset(state); in s5h1420_init()
819 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_sleep() local
820 state->CON_1_val = 0x12; in s5h1420_sleep()
821 return s5h1420_writereg(state, 0x02, state->CON_1_val); in s5h1420_sleep()
826 struct s5h1420_state* state = fe->demodulator_priv; in s5h1420_release() local
827 i2c_del_adapter(&state->tuner_i2c_adapter); in s5h1420_release()
828 kfree(state); in s5h1420_release()
838 struct s5h1420_state *state = i2c_get_adapdata(i2c_adap); in s5h1420_tuner_i2c_tuner_xfer() local
840 …u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition… in s5h1420_tuner_i2c_tuner_xfer()
851 m[0].addr = state->config->demod_address; in s5h1420_tuner_i2c_tuner_xfer()
857 return i2c_transfer(state->i2c, m, 1 + num) == 1 + num ? num : -EIO; in s5h1420_tuner_i2c_tuner_xfer()
867 struct s5h1420_state *state = fe->demodulator_priv; in s5h1420_get_tuner_i2c_adapter() local
868 return &state->tuner_i2c_adapter; in s5h1420_get_tuner_i2c_adapter()
878 struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL); in s5h1420_attach() local
881 if (state == NULL) in s5h1420_attach()
885 state->config = config; in s5h1420_attach()
886 state->i2c = i2c; in s5h1420_attach()
887 state->postlocked = 0; in s5h1420_attach()
888 state->fclk = 88000000; in s5h1420_attach()
889 state->tunedfreq = 0; in s5h1420_attach()
890 state->fec_inner = FEC_NONE; in s5h1420_attach()
891 state->symbol_rate = 0; in s5h1420_attach()
894 i = s5h1420_readreg(state, ID01); in s5h1420_attach()
898 memset(state->shadow, 0xff, sizeof(state->shadow)); in s5h1420_attach()
901 state->shadow[i] = s5h1420_readreg(state, i); in s5h1420_attach()
904 memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops)); in s5h1420_attach()
905 state->frontend.demodulator_priv = state; in s5h1420_attach()
908 strlcpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", in s5h1420_attach()
909 sizeof(state->tuner_i2c_adapter.name)); in s5h1420_attach()
910 state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo; in s5h1420_attach()
911 state->tuner_i2c_adapter.algo_data = NULL; in s5h1420_attach()
912 i2c_set_adapdata(&state->tuner_i2c_adapter, state); in s5h1420_attach()
913 if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { in s5h1420_attach()
918 return &state->frontend; in s5h1420_attach()
921 kfree(state); in s5h1420_attach()