Lines Matching refs:state
167 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg) in __dib8000_read_word() argument
171 state->i2c_write_buffer[0] = reg >> 8; in __dib8000_read_word()
172 state->i2c_write_buffer[1] = reg & 0xff; in __dib8000_read_word()
174 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in __dib8000_read_word()
175 state->msg[0].addr = state->i2c.addr >> 1; in __dib8000_read_word()
176 state->msg[0].flags = 0; in __dib8000_read_word()
177 state->msg[0].buf = state->i2c_write_buffer; in __dib8000_read_word()
178 state->msg[0].len = 2; in __dib8000_read_word()
179 state->msg[1].addr = state->i2c.addr >> 1; in __dib8000_read_word()
180 state->msg[1].flags = I2C_M_RD; in __dib8000_read_word()
181 state->msg[1].buf = state->i2c_read_buffer; in __dib8000_read_word()
182 state->msg[1].len = 2; in __dib8000_read_word()
184 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2) in __dib8000_read_word()
187 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in __dib8000_read_word()
192 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) in dib8000_read_word() argument
196 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read_word()
201 ret = __dib8000_read_word(state, reg); in dib8000_read_word()
203 mutex_unlock(&state->i2c_buffer_lock); in dib8000_read_word()
208 static u32 dib8000_read32(struct dib8000_state *state, u16 reg) in dib8000_read32() argument
212 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read32()
217 rw[0] = __dib8000_read_word(state, reg + 0); in dib8000_read32()
218 rw[1] = __dib8000_read_word(state, reg + 1); in dib8000_read32()
220 mutex_unlock(&state->i2c_buffer_lock); in dib8000_read32()
247 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) in dib8000_write_word() argument
251 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_write_word()
256 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib8000_write_word()
257 state->i2c_write_buffer[1] = reg & 0xff; in dib8000_write_word()
258 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib8000_write_word()
259 state->i2c_write_buffer[3] = val & 0xff; in dib8000_write_word()
261 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib8000_write_word()
262 state->msg[0].addr = state->i2c.addr >> 1; in dib8000_write_word()
263 state->msg[0].flags = 0; in dib8000_write_word()
264 state->msg[0].buf = state->i2c_write_buffer; in dib8000_write_word()
265 state->msg[0].len = 4; in dib8000_write_word()
267 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? in dib8000_write_word()
269 mutex_unlock(&state->i2c_buffer_lock); in dib8000_write_word()
375 static u16 fft_to_mode(struct dib8000_state *state) in fft_to_mode() argument
378 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in fft_to_mode()
394 static void dib8000_set_acquisition_mode(struct dib8000_state *state) in dib8000_set_acquisition_mode() argument
396 u16 nud = dib8000_read_word(state, 298); in dib8000_set_acquisition_mode()
399 dib8000_write_word(state, 298, nud); in dib8000_set_acquisition_mode()
403 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_output_mode() local
406 state->output_mode = mode; in dib8000_set_output_mode()
409 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8000_set_output_mode()
412 &state->fe[0], mode); in dib8000_set_output_mode()
425 if (state->cfg.hostbus_diversity) { in dib8000_set_output_mode()
442 dib8000_set_acquisition_mode(state); in dib8000_set_output_mode()
447 &state->fe[0]); in dib8000_set_output_mode()
451 if (state->cfg.output_mpeg2_in_188_bytes) in dib8000_set_output_mode()
454 dib8000_write_word(state, 299, smo_mode); in dib8000_set_output_mode()
455 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */ in dib8000_set_output_mode()
456 dib8000_write_word(state, 1286, outreg); in dib8000_set_output_mode()
457 dib8000_write_word(state, 1291, sram); in dib8000_set_output_mode()
464 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_diversity_in() local
465 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0; in dib8000_set_diversity_in()
468 if (!state->differential_constellation) { in dib8000_set_diversity_in()
469 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1 in dib8000_set_diversity_in()
470 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2 in dib8000_set_diversity_in()
472 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 in dib8000_set_diversity_in()
473 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 in dib8000_set_diversity_in()
475 state->diversity_onoff = onoff; in dib8000_set_diversity_in()
479 dib8000_write_word(state, 270, 1); in dib8000_set_diversity_in()
480 dib8000_write_word(state, 271, 0); in dib8000_set_diversity_in()
483 dib8000_write_word(state, 270, 6); in dib8000_set_diversity_in()
484 dib8000_write_word(state, 271, 6); in dib8000_set_diversity_in()
487 dib8000_write_word(state, 270, 0); in dib8000_set_diversity_in()
488 dib8000_write_word(state, 271, 1); in dib8000_set_diversity_in()
492 if (state->revision == 0x8002) { in dib8000_set_diversity_in()
493 tmp = dib8000_read_word(state, 903); in dib8000_set_diversity_in()
494 dib8000_write_word(state, 903, tmp & ~(1 << 3)); in dib8000_set_diversity_in()
496 dib8000_write_word(state, 903, tmp | (1 << 3)); in dib8000_set_diversity_in()
501 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode) in dib8000_set_power_mode() argument
505 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, in dib8000_set_power_mode()
508 if (state->revision != 0x8090) in dib8000_set_power_mode()
509 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; in dib8000_set_power_mode()
511 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80; in dib8000_set_power_mode()
521 if (state->revision != 0x8090) in dib8000_set_power_mode()
527 if (state->revision != 0x8090) in dib8000_set_power_mode()
535 dib8000_write_word(state, 774, reg_774); in dib8000_set_power_mode()
536 dib8000_write_word(state, 775, reg_775); in dib8000_set_power_mode()
537 dib8000_write_word(state, 776, reg_776); in dib8000_set_power_mode()
538 dib8000_write_word(state, 900, reg_900); in dib8000_set_power_mode()
539 dib8000_write_word(state, 1280, reg_1280); in dib8000_set_power_mode()
542 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no) in dib8000_set_adc_state() argument
545 u16 reg, reg_907 = dib8000_read_word(state, 907); in dib8000_set_adc_state()
546 u16 reg_908 = dib8000_read_word(state, 908); in dib8000_set_adc_state()
550 if (state->revision != 0x8090) { in dib8000_set_adc_state()
552 ret |= dib8000_write_word(state, 908, reg_908); in dib8000_set_adc_state()
555 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
557 dib8000_write_word(state, 1925, reg | in dib8000_set_adc_state()
561 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
564 dib8000_write_word(state, 1925, reg & ~(1<<4)); in dib8000_set_adc_state()
566 reg = dib8000_read_word(state, 921) & ~((0x3 << 14) in dib8000_set_adc_state()
570 dib8000_write_word(state, 921, reg | (1 << 14) in dib8000_set_adc_state()
576 if (state->revision == 0x8090) { in dib8000_set_adc_state()
577 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
579 dib8000_write_word(state, 1925, in dib8000_set_adc_state()
607 ret |= dib8000_write_word(state, 907, reg_907); in dib8000_set_adc_state()
608 ret |= dib8000_write_word(state, 908, reg_908); in dib8000_set_adc_state()
615 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_bandwidth() local
621 if (state->timf == 0) { in dib8000_set_bandwidth()
623 timf = state->timf_default; in dib8000_set_bandwidth()
626 timf = state->timf; in dib8000_set_bandwidth()
629 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); in dib8000_set_bandwidth()
630 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); in dib8000_set_bandwidth()
635 static int dib8000_sad_calib(struct dib8000_state *state) in dib8000_sad_calib() argument
639 if (state->revision == 0x8090) { in dib8000_sad_calib()
640 dib8000_write_word(state, 922, (sad_sel << 2)); in dib8000_sad_calib()
641 dib8000_write_word(state, 923, 2048); in dib8000_sad_calib()
643 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1); in dib8000_sad_calib()
644 dib8000_write_word(state, 922, (sad_sel << 2)); in dib8000_sad_calib()
647 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); in dib8000_sad_calib()
648 dib8000_write_word(state, 924, 776); in dib8000_sad_calib()
651 dib8000_write_word(state, 923, (1 << 0)); in dib8000_sad_calib()
652 dib8000_write_word(state, 923, (0 << 0)); in dib8000_sad_calib()
661 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_wbd_ref() local
664 state->wbd_ref = value; in dib8000_set_wbd_ref()
665 return dib8000_write_word(state, 106, value); in dib8000_set_wbd_ref()
668 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_co… in dib8000_reset_pll_common() argument
671 if (state->revision != 0x8090) { in dib8000_reset_pll_common()
672 dib8000_write_word(state, 23, in dib8000_reset_pll_common()
674 dib8000_write_word(state, 24, in dib8000_reset_pll_common()
677 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
678 dib8000_write_word(state, 24, in dib8000_reset_pll_common()
681 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); in dib8000_reset_pll_common()
682 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); in dib8000_reset_pll_common()
683 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); in dib8000_reset_pll_common()
685 if (state->revision != 0x8090) in dib8000_reset_pll_common()
686 dib8000_write_word(state, 922, bw->sad_cfg); in dib8000_reset_pll_common()
689 static void dib8000_reset_pll(struct dib8000_state *state) in dib8000_reset_pll() argument
691 const struct dibx000_bandwidth_config *pll = state->cfg.pll; in dib8000_reset_pll()
694 if (state->revision != 0x8090) { in dib8000_reset_pll()
695 dib8000_write_word(state, 901, in dib8000_reset_pll()
703 dib8000_write_word(state, 902, clk_cfg1); in dib8000_reset_pll()
705 dib8000_write_word(state, 902, clk_cfg1); in dib8000_reset_pll()
710 if (state->cfg.pll->ADClkSrc == 0) in dib8000_reset_pll()
711 dib8000_write_word(state, 904, in dib8000_reset_pll()
715 else if (state->cfg.refclksel != 0) in dib8000_reset_pll()
716 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
717 ((state->cfg.refclksel & 0x3) << 10) | in dib8000_reset_pll()
721 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
725 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | in dib8000_reset_pll()
729 reg = dib8000_read_word(state, 1857); in dib8000_reset_pll()
730 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); in dib8000_reset_pll()
732 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */ in dib8000_reset_pll()
733 dib8000_write_word(state, 1858, reg | 1); in dib8000_reset_pll()
735 dib8000_write_word(state, 904, (pll->modulo << 8)); in dib8000_reset_pll()
738 dib8000_reset_pll_common(state, pll); in dib8000_reset_pll()
744 struct dib8000_state *state = fe->demodulator_priv; in dib8000_update_pll() local
745 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856); in dib8000_update_pll()
746 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; in dib8000_update_pll()
758 if (state->revision == 0x8090) { in dib8000_update_pll()
760 reg_1857 = dib8000_read_word(state, 1857); in dib8000_update_pll()
762 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15)); in dib8000_update_pll()
764 dib8000_write_word(state, 1856, reg_1856 | in dib8000_update_pll()
769 internal = dib8000_read32(state, 23) / 1000; in dib8000_update_pll()
776 dib8000_write_word(state, 23, in dib8000_update_pll()
778 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); in dib8000_update_pll()
780 dib8000_write_word(state, 1857, reg_1857 | (1 << 15)); in dib8000_update_pll()
782 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1) in dib8000_update_pll()
786 reg_1856 = dib8000_read_word(state, 1856); in dib8000_update_pll()
790 if (bw != state->current_demod_bw) { in dib8000_update_pll()
792 …dth Change %d MHz -> %d MHz (prediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldpredi… in dib8000_update_pll()
794 if (state->cfg.pll->pll_prediv != oldprediv) { in dib8000_update_pll()
798 …ing for %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg… in dib8000_update_pll()
799 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */ in dib8000_update_pll()
800 dib8000_reset_pll(state); in dib8000_update_pll()
801 dib8000_write_word(state, 898, 0x0004); /* sad */ in dib8000_update_pll()
803 ratio = state->cfg.pll->pll_ratio; in dib8000_update_pll()
805 state->current_demod_bw = bw; in dib8000_update_pll()
810 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)", state->cfg.pll->pll_prediv, ratio); in dib8000_update_pll()
811 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL … in dib8000_update_pll()
851 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_gpio() local
852 return dib8000_cfg_gpio(state, num, dir, val); in dib8000_set_gpio()
993 struct dib8000_state *state = fe->demodulator_priv; in dib8000_reset_stats() local
994 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_reset_stats()
1021 state->init_ucb = -ucb; in dib8000_reset_stats()
1022 state->ber_jiffies_stats = 0; in dib8000_reset_stats()
1023 state->per_jiffies_stats = 0; in dib8000_reset_stats()
1024 memset(&state->ber_jiffies_stats_layer, 0, in dib8000_reset_stats()
1025 sizeof(state->ber_jiffies_stats_layer)); in dib8000_reset_stats()
1030 struct dib8000_state *state = fe->demodulator_priv; in dib8000_reset() local
1032 if ((state->revision = dib8000_identify(&state->i2c)) == 0) in dib8000_reset()
1036 if (state->revision != 0x8090) in dib8000_reset()
1037 dib8000_write_word(state, 1287, 0x0003); in dib8000_reset()
1039 if (state->revision == 0x8000) in dib8000_reset()
1042 dibx000_reset_i2c_master(&state->i2c_master); in dib8000_reset()
1044 dib8000_set_power_mode(state, DIB8000_POWER_ALL); in dib8000_reset()
1047 dib8000_set_adc_state(state, DIBX000_ADC_OFF); in dib8000_reset()
1050 dib8000_write_word(state, 770, 0xffff); in dib8000_reset()
1051 dib8000_write_word(state, 771, 0xffff); in dib8000_reset()
1052 dib8000_write_word(state, 772, 0xfffc); in dib8000_reset()
1053 dib8000_write_word(state, 898, 0x000c); /* restart sad */ in dib8000_reset()
1054 if (state->revision == 0x8090) in dib8000_reset()
1055 dib8000_write_word(state, 1280, 0x0045); in dib8000_reset()
1057 dib8000_write_word(state, 1280, 0x004d); in dib8000_reset()
1058 dib8000_write_word(state, 1281, 0x000c); in dib8000_reset()
1060 dib8000_write_word(state, 770, 0x0000); in dib8000_reset()
1061 dib8000_write_word(state, 771, 0x0000); in dib8000_reset()
1062 dib8000_write_word(state, 772, 0x0000); in dib8000_reset()
1063 dib8000_write_word(state, 898, 0x0004); // sad in dib8000_reset()
1064 dib8000_write_word(state, 1280, 0x0000); in dib8000_reset()
1065 dib8000_write_word(state, 1281, 0x0000); in dib8000_reset()
1068 if (state->revision != 0x8090) { in dib8000_reset()
1069 if (state->cfg.drives) in dib8000_reset()
1070 dib8000_write_word(state, 906, state->cfg.drives); in dib8000_reset()
1074 dib8000_write_word(state, 906, 0x2d98); in dib8000_reset()
1078 dib8000_reset_pll(state); in dib8000_reset()
1079 if (state->revision != 0x8090) in dib8000_reset()
1080 dib8000_write_word(state, 898, 0x0004); in dib8000_reset()
1082 if (dib8000_reset_gpio(state) != 0) in dib8000_reset()
1085 if ((state->revision != 0x8090) && in dib8000_reset()
1089 state->current_agc = NULL; in dib8000_reset()
1093 if (state->cfg.pll->ifreq == 0) in dib8000_reset()
1094 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ in dib8000_reset()
1096 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ in dib8000_reset()
1106 dib8000_write_word(state, r, *n++); in dib8000_reset()
1113 state->isdbt_cfg_loaded = 0; in dib8000_reset()
1116 if ((state->revision != 8090) && (state->cfg.div_cfg != 0)) in dib8000_reset()
1117 dib8000_write_word(state, 903, state->cfg.div_cfg); in dib8000_reset()
1120 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); in dib8000_reset()
1124 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON); in dib8000_reset()
1125 dib8000_sad_calib(state); in dib8000_reset()
1126 if (state->revision != 0x8090) in dib8000_reset()
1127 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF); in dib8000_reset()
1130 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); in dib8000_reset()
1132 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); in dib8000_reset()
1139 static void dib8000_restart_agc(struct dib8000_state *state) in dib8000_restart_agc() argument
1142 dib8000_write_word(state, 770, 0x0a00); in dib8000_restart_agc()
1143 dib8000_write_word(state, 770, 0x0000); in dib8000_restart_agc()
1146 static int dib8000_update_lna(struct dib8000_state *state) in dib8000_update_lna() argument
1150 if (state->cfg.update_lna) { in dib8000_update_lna()
1152 dyn_gain = dib8000_read_word(state, 390); in dib8000_update_lna()
1154 if (state->cfg.update_lna(state->fe[0], dyn_gain)) { in dib8000_update_lna()
1155 dib8000_restart_agc(state); in dib8000_update_lna()
1162 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band) in dib8000_set_agc_config() argument
1168 if (state->current_band == band && state->current_agc != NULL) in dib8000_set_agc_config()
1170 state->current_band = band; in dib8000_set_agc_config()
1172 for (i = 0; i < state->cfg.agc_config_count; i++) in dib8000_set_agc_config()
1173 if (state->cfg.agc[i].band_caps & band) { in dib8000_set_agc_config()
1174 agc = &state->cfg.agc[i]; in dib8000_set_agc_config()
1183 state->current_agc = agc; in dib8000_set_agc_config()
1186 dib8000_write_word(state, 76, agc->setup); in dib8000_set_agc_config()
1187 dib8000_write_word(state, 77, agc->inv_gain); in dib8000_set_agc_config()
1188 dib8000_write_word(state, 78, agc->time_stabiliz); in dib8000_set_agc_config()
1189 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock); in dib8000_set_agc_config()
1192 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp); in dib8000_set_agc_config()
1193 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp); in dib8000_set_agc_config()
1196 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib8000_set_agc_config()
1199 if (state->wbd_ref != 0) in dib8000_set_agc_config()
1200 dib8000_write_word(state, 106, state->wbd_ref); in dib8000_set_agc_config()
1202 dib8000_write_word(state, 106, agc->wbd_ref); in dib8000_set_agc_config()
1204 if (state->revision == 0x8090) { in dib8000_set_agc_config()
1205 reg = dib8000_read_word(state, 922) & (0x3 << 2); in dib8000_set_agc_config()
1206 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); in dib8000_set_agc_config()
1209 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8)); in dib8000_set_agc_config()
1210 dib8000_write_word(state, 108, agc->agc1_max); in dib8000_set_agc_config()
1211 dib8000_write_word(state, 109, agc->agc1_min); in dib8000_set_agc_config()
1212 dib8000_write_word(state, 110, agc->agc2_max); in dib8000_set_agc_config()
1213 dib8000_write_word(state, 111, agc->agc2_min); in dib8000_set_agc_config()
1214 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib8000_set_agc_config()
1215 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib8000_set_agc_config()
1216 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib8000_set_agc_config()
1217 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib8000_set_agc_config()
1219 dib8000_write_word(state, 75, agc->agc1_pt3); in dib8000_set_agc_config()
1220 if (state->revision != 0x8090) in dib8000_set_agc_config()
1221 dib8000_write_word(state, 923, in dib8000_set_agc_config()
1222 (dib8000_read_word(state, 923) & 0xffe3) | in dib8000_set_agc_config()
1230 struct dib8000_state *state = fe->demodulator_priv; in dib8000_pwm_agc_reset() local
1231 dib8000_set_adc_state(state, DIBX000_ADC_ON); in dib8000_pwm_agc_reset()
1232 …dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency /… in dib8000_pwm_agc_reset()
1235 static int dib8000_agc_soft_split(struct dib8000_state *state) in dib8000_agc_soft_split() argument
1239 …if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split… in dib8000_agc_soft_split()
1243 agc = dib8000_read_word(state, 390); in dib8000_agc_soft_split()
1245 if (agc > state->current_agc->split.min_thres) in dib8000_agc_soft_split()
1246 split_offset = state->current_agc->split.min; in dib8000_agc_soft_split()
1247 else if (agc < state->current_agc->split.max_thres) in dib8000_agc_soft_split()
1248 split_offset = state->current_agc->split.max; in dib8000_agc_soft_split()
1250 split_offset = state->current_agc->split.max * in dib8000_agc_soft_split()
1251 (agc - state->current_agc->split.min_thres) / in dib8000_agc_soft_split()
1252 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); in dib8000_agc_soft_split()
1257 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); in dib8000_agc_soft_split()
1263 struct dib8000_state *state = fe->demodulator_priv; in dib8000_agc_startup() local
1264 enum frontend_tune_state *tune_state = &state->tune_state; in dib8000_agc_startup()
1273 if (state->revision != 0x8090) in dib8000_agc_startup()
1274 dib8000_set_adc_state(state, DIBX000_ADC_ON); in dib8000_agc_startup()
1276 dib8000_set_power_mode(state, DIB8000_POWER_ALL); in dib8000_agc_startup()
1278 reg = dib8000_read_word(state, 1947)&0xff00; in dib8000_agc_startup()
1279 dib8000_write_word(state, 1946, in dib8000_agc_startup()
1282 dib8000_write_word(state, 1947, reg | (1<<14) | in dib8000_agc_startup()
1286 reg = dib8000_read_word(state, 1920); in dib8000_agc_startup()
1287 dib8000_write_word(state, 1920, (reg | 0x3) & in dib8000_agc_startup()
1291 …if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequen… in dib8000_agc_startup()
1293 state->status = FE_STATUS_TUNE_FAILED; in dib8000_agc_startup()
1303 if (state->cfg.agc_control) in dib8000_agc_startup()
1304 state->cfg.agc_control(fe, 1); in dib8000_agc_startup()
1306 dib8000_restart_agc(state); in dib8000_agc_startup()
1317 if (dib8000_update_lna(state)) in dib8000_agc_startup()
1325 dib8000_agc_soft_split(state); in dib8000_agc_startup()
1327 if (state->cfg.agc_control) in dib8000_agc_startup()
1328 state->cfg.agc_control(fe, 0); in dib8000_agc_startup()
1333 ret = dib8000_agc_soft_split(state); in dib8000_agc_startup()
1340 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive) in dib8096p_host_bus_drive() argument
1347 reg = dib8000_read_word(state, 1798) & in dib8096p_host_bus_drive()
1350 dib8000_write_word(state, 1798, reg); in dib8096p_host_bus_drive()
1353 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1355 dib8000_write_word(state, 1799, reg); in dib8096p_host_bus_drive()
1358 reg = dib8000_read_word(state, 1800) & in dib8096p_host_bus_drive()
1361 dib8000_write_word(state, 1800, reg); in dib8096p_host_bus_drive()
1364 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1366 dib8000_write_word(state, 1801, reg); in dib8096p_host_bus_drive()
1369 reg = dib8000_read_word(state, 1802) & in dib8096p_host_bus_drive()
1372 dib8000_write_word(state, 1802, reg); in dib8096p_host_bus_drive()
1394 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin, in dib8096p_cfg_DibTx() argument
1400 dib8000_write_word(state, 1615, 1); in dib8096p_cfg_DibTx()
1401 dib8000_write_word(state, 1603, P_Kin); in dib8096p_cfg_DibTx()
1402 dib8000_write_word(state, 1605, P_Kout); in dib8096p_cfg_DibTx()
1403 dib8000_write_word(state, 1606, insertExtSynchro); in dib8096p_cfg_DibTx()
1404 dib8000_write_word(state, 1608, synchroMode); in dib8096p_cfg_DibTx()
1405 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibTx()
1406 dib8000_write_word(state, 1610, syncWord & 0xffff); in dib8096p_cfg_DibTx()
1407 dib8000_write_word(state, 1612, syncSize); in dib8096p_cfg_DibTx()
1408 dib8000_write_word(state, 1615, 0); in dib8096p_cfg_DibTx()
1411 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin, in dib8096p_cfg_DibRx() argument
1422 dib8000_write_word(state, 1542, syncFreq); in dib8096p_cfg_DibRx()
1425 dib8000_write_word(state, 1554, 1); in dib8096p_cfg_DibRx()
1426 dib8000_write_word(state, 1536, P_Kin); in dib8096p_cfg_DibRx()
1427 dib8000_write_word(state, 1537, P_Kout); in dib8096p_cfg_DibRx()
1428 dib8000_write_word(state, 1539, synchroMode); in dib8096p_cfg_DibRx()
1429 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibRx()
1430 dib8000_write_word(state, 1541, syncWord & 0xffff); in dib8096p_cfg_DibRx()
1431 dib8000_write_word(state, 1543, syncSize); in dib8096p_cfg_DibRx()
1432 dib8000_write_word(state, 1544, dataOutRate); in dib8096p_cfg_DibRx()
1433 dib8000_write_word(state, 1554, 0); in dib8096p_cfg_DibRx()
1436 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff) in dib8096p_enMpegMux() argument
1440 reg_1287 = dib8000_read_word(state, 1287); in dib8096p_enMpegMux()
1451 dib8000_write_word(state, 1287, reg_1287); in dib8096p_enMpegMux()
1454 static void dib8096p_configMpegMux(struct dib8000_state *state, in dib8096p_configMpegMux() argument
1461 dib8096p_enMpegMux(state, 0); in dib8096p_configMpegMux()
1464 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1)) in dib8096p_configMpegMux()
1469 dib8000_write_word(state, 1287, reg_1287); in dib8096p_configMpegMux()
1471 dib8096p_enMpegMux(state, 1); in dib8096p_configMpegMux()
1474 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode) in dib8096p_setDibTxMux() argument
1476 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7); in dib8096p_setDibTxMux()
1481 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); in dib8096p_setDibTxMux()
1485 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); in dib8096p_setDibTxMux()
1489 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); in dib8096p_setDibTxMux()
1494 dib8000_write_word(state, 1288, reg_1288); in dib8096p_setDibTxMux()
1497 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode) in dib8096p_setHostBusMux() argument
1499 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4); in dib8096p_setHostBusMux()
1504 dib8096p_enMpegMux(state, 0); in dib8096p_setHostBusMux()
1509 dib8096p_enMpegMux(state, 0); in dib8096p_setHostBusMux()
1519 dib8000_write_word(state, 1288, reg_1288); in dib8096p_setHostBusMux()
1524 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_set_diversity_in() local
1532 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); in dib8096p_set_diversity_in()
1536 reg_1287 = dib8000_read_word(state, 1287); in dib8096p_set_diversity_in()
1541 dib8000_write_word(state, 1287, reg_1287); in dib8096p_set_diversity_in()
1543 state->input_mode_mpeg = 1; in dib8096p_set_diversity_in()
1548 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); in dib8096p_set_diversity_in()
1549 state->input_mode_mpeg = 0; in dib8096p_set_diversity_in()
1553 dib8000_set_diversity_in(state->fe[0], onoff); in dib8096p_set_diversity_in()
1559 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_set_output_mode() local
1564 state->output_mode = mode; in dib8096p_set_output_mode()
1565 dib8096p_host_bus_drive(state, 1); in dib8096p_set_output_mode()
1568 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8096p_set_output_mode()
1569 outreg = dib8000_read_word(state, 1286) & in dib8096p_set_output_mode()
1580 dib8096p_configMpegMux(state, 3, 1, 1); in dib8096p_set_output_mode()
1581 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); in dib8096p_set_output_mode()
1584 dib8096p_setHostBusMux(state, in dib8096p_set_output_mode()
1593 dib8096p_configMpegMux(state, 2, 0, 0); in dib8096p_set_output_mode()
1594 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS); in dib8096p_set_output_mode()
1597 dib8096p_setHostBusMux(state, in dib8096p_set_output_mode()
1605 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); in dib8096p_set_output_mode()
1613 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS); in dib8096p_set_output_mode()
1621 dib8096p_setDibTxMux(state, DIV_ON_DIBTX); in dib8096p_set_output_mode()
1622 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); in dib8096p_set_output_mode()
1627 dib8096p_setDibTxMux(state, ADC_ON_DIBTX); in dib8096p_set_output_mode()
1628 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); in dib8096p_set_output_mode()
1636 state->cfg.output_mpeg2_in_188_bytes); in dib8096p_set_output_mode()
1637 if (state->cfg.output_mpeg2_in_188_bytes) in dib8096p_set_output_mode()
1640 ret |= dib8000_write_word(state, 299, smo_mode); in dib8096p_set_output_mode()
1642 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold); in dib8096p_set_output_mode()
1643 ret |= dib8000_write_word(state, 1286, outreg); in dib8096p_set_output_mode()
1672 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_tuner_write_serpar() local
1678 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_write_serpar()
1683 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); in dib8096p_tuner_write_serpar()
1684 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); in dib8096p_tuner_write_serpar()
1692 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_tuner_read_serpar() local
1699 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_read_serpar()
1704 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); in dib8096p_tuner_read_serpar()
1708 n_empty = dib8000_read_word(state, 1984)&0x1; in dib8096p_tuner_read_serpar()
1714 read_word = dib8000_read_word(state, 1987); in dib8096p_tuner_read_serpar()
1736 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_rw_on_apb() local
1740 dib8000_write_word(state, apb_address, in dib8096p_rw_on_apb()
1743 word = dib8000_read_word(state, apb_address); in dib8096p_rw_on_apb()
1753 struct dib8000_state *state = i2c_get_adapdata(i2c_adap); in dib8096p_tuner_xfer() local
1844 i = ((dib8000_read_word(state, 921) >> 12)&0x3); in dib8096p_tuner_xfer()
1845 word = dib8000_read_word(state, 924+i); in dib8096p_tuner_xfer()
1855 word = (dib8000_read_word(state, 921) & in dib8096p_tuner_xfer()
1858 dib8000_write_word(state, 921, word); in dib8096p_tuner_xfer()
1889 struct dib8000_state *state = fe->demodulator_priv; in dib8096p_tuner_sleep() local
1894 en_cur_state = dib8000_read_word(state, 1922); in dib8096p_tuner_sleep()
1898 state->tuner_enable = en_cur_state ; in dib8096p_tuner_sleep()
1903 if (state->tuner_enable != 0) in dib8096p_tuner_sleep()
1904 en_cur_state = state->tuner_enable; in dib8096p_tuner_sleep()
1907 dib8000_write_word(state, 1922, en_cur_state); in dib8096p_tuner_sleep()
1919 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_adc_power() local
1923 val = dib8000_read32(state, 384); in dib8000_get_adc_power()
1938 struct dib8000_state *state = fe->demodulator_priv; in dib8090p_get_dc_power() local
1943 val = dib8000_read_word(state, 403); in dib8090p_get_dc_power()
1946 val = dib8000_read_word(state, 404); in dib8090p_get_dc_power()
1955 static void dib8000_update_timf(struct dib8000_state *state) in dib8000_update_timf() argument
1957 u32 timf = state->timf = dib8000_read32(state, 435); in dib8000_update_timf()
1959 dib8000_write_word(state, 29, (u16) (timf >> 16)); in dib8000_update_timf()
1960 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); in dib8000_update_timf()
1961 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default); in dib8000_update_timf()
1966 struct dib8000_state *state = fe->demodulator_priv; in dib8000_ctrl_timf() local
1970 state->timf = timf; in dib8000_ctrl_timf()
1973 dib8000_update_timf(state); in dib8000_ctrl_timf()
1978 dib8000_set_bandwidth(state->fe[0], 6000); in dib8000_ctrl_timf()
1980 return state->timf; in dib8000_ctrl_timf()
1989 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation) in dib8000_set_layer() argument
1992 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_layer()
2033 …dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment… in dib8000_set_layer()
2054 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation) in dib8000_adp_fine_tune() argument
2076 dib8000_write_word(state, 215 + i, adp[i]); in dib8000_adp_fine_tune()
2081 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain) in dib8000_update_ana_gain() argument
2085 dib8000_write_word(state, 116, ana_gain); in dib8000_update_ana_gain()
2090 dib8000_write_word(state, 80 + i, adc_target_16dB[i]); in dib8000_update_ana_gain()
2093 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355); in dib8000_update_ana_gain()
2097 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe) in dib8000_load_ana_fe_coefs() argument
2101 if (state->isdbt_cfg_loaded == 0) in dib8000_load_ana_fe_coefs()
2103 dib8000_write_word(state, 117 + mode, ana_fe[mode]); in dib8000_load_ana_fe_coefs()
2116 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel) in dib8000_get_init_prbs() argument
2123 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in dib8000_get_init_prbs()
2134 static void dib8000_set_13seg_channel(struct dib8000_state *state) in dib8000_set_13seg_channel() argument
2139 state->seg_mask = 0x1fff; /* All 13 segments enabled */ in dib8000_set_13seg_channel()
2142 …if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13… in dib8000_set_13seg_channel()
2143 dib8000_write_word(state, 180, (16 << 6) | 9); in dib8000_set_13seg_channel()
2144 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); in dib8000_set_13seg_channel()
2147 dib8000_write_word(state, 181+i, coff_pow); in dib8000_set_13seg_channel()
2151 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); in dib8000_set_13seg_channel()
2154 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); in dib8000_set_13seg_channel()
2156 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); in dib8000_set_13seg_channel()
2158 dib8000_write_word(state, 228, 0); /* default value */ in dib8000_set_13seg_channel()
2159 dib8000_write_word(state, 265, 31); /* default value */ in dib8000_set_13seg_channel()
2160 dib8000_write_word(state, 205, 0x200f); /* init value */ in dib8000_set_13seg_channel()
2168 if (state->cfg.pll->ifreq == 0) in dib8000_set_13seg_channel()
2169 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_s… in dib8000_set_13seg_channel()
2171 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg); in dib8000_set_13seg_channel()
2174 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs) in dib8000_set_subchannel_prbs() argument
2178 reg_1 = dib8000_read_word(state, 1); in dib8000_set_subchannel_prbs()
2179 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */ in dib8000_set_subchannel_prbs()
2182 static void dib8000_small_fine_tune(struct dib8000_state *state) in dib8000_small_fine_tune() argument
2186 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_small_fine_tune()
2188 dib8000_write_word(state, 352, state->seg_diff_mask); in dib8000_small_fine_tune()
2189 dib8000_write_word(state, 353, state->seg_mask); in dib8000_small_fine_tune()
2192 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5); in dib8000_small_fine_tune()
2262 dib8000_write_word(state, 343 + i, ncoeff[i]); in dib8000_small_fine_tune()
2268 static void dib8000_set_sb_channel(struct dib8000_state *state) in dib8000_set_sb_channel() argument
2270 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_sb_channel()
2275 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ in dib8000_set_sb_channel()
2276 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shi… in dib8000_set_sb_channel()
2278 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ in dib8000_set_sb_channel()
2279 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = … in dib8000_set_sb_channel()
2283 state->seg_mask = 0x00E0; in dib8000_set_sb_channel()
2285 state->seg_mask = 0x0040; in dib8000_set_sb_channel()
2287 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_sb_channel()
2291 …dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partia… in dib8000_set_sb_channel()
2293 …dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_fr… in dib8000_set_sb_channel()
2294 …dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres… in dib8000_set_sb_channel()
2299 if (state->mode == 3) in dib8000_set_sb_channel()
2300 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2302 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2305 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); in dib8000_set_sb_channel()
2308 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); in dib8000_set_sb_channel()
2310 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); in dib8000_set_sb_channel()
2314 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */ in dib8000_set_sb_channel()
2315 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ in dib8000_set_sb_channel()
2318 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */ in dib8000_set_sb_channel()
2322 dib8000_write_word(state, 181+i, coff[i]); in dib8000_set_sb_channel()
2323 dib8000_write_word(state, 184+i, coff[i]); in dib8000_set_sb_channel()
2331 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh … in dib8000_set_sb_channel()
2334 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */ in dib8000_set_sb_channel()
2336 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ in dib8000_set_sb_channel()
2339 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching) in dib8000_set_isdbt_common_channel() argument
2345 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_isdbt_common_channel()
2351 dib8000_write_word(state, 10, (seq << 4)); in dib8000_set_isdbt_common_channel()
2354 state->mode = fft_to_mode(state); in dib8000_set_isdbt_common_channel()
2357 tmp = dib8000_read_word(state, 1); in dib8000_set_isdbt_common_channel()
2358 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); in dib8000_set_isdbt_common_channel()
2360 …dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_recep… in dib8000_set_isdbt_common_channel()
2364 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0]; in dib8000_set_isdbt_common_channel()
2368 state->seg_diff_mask |= 1 << permu_seg[i+1]; in dib8000_set_isdbt_common_channel()
2373 state->seg_diff_mask |= 1 << permu_seg[i]; in dib8000_set_isdbt_common_channel()
2376 if (state->seg_diff_mask) in dib8000_set_isdbt_common_channel()
2377 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_isdbt_common_channel()
2379 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */ in dib8000_set_isdbt_common_channel()
2382 max_constellation = dib8000_set_layer(state, i, max_constellation); in dib8000_set_isdbt_common_channel()
2384 state->layer_b_nb_seg = c->layer[1].segment_count; in dib8000_set_isdbt_common_channel()
2385 state->layer_c_nb_seg = c->layer[2].segment_count; in dib8000_set_isdbt_common_channel()
2389 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); in dib8000_set_isdbt_common_channel()
2391 state->differential_constellation = (state->seg_diff_mask != 0); in dib8000_set_isdbt_common_channel()
2394 ana_gain = dib8000_adp_fine_tune(state, max_constellation); in dib8000_set_isdbt_common_channel()
2397 dib8000_update_ana_gain(state, ana_gain); in dib8000_set_isdbt_common_channel()
2401 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg); in dib8000_set_isdbt_common_channel()
2403 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */ in dib8000_set_isdbt_common_channel()
2407 dib8000_set_sb_channel(state); in dib8000_set_isdbt_common_channel()
2409 init_prbs = dib8000_get_init_prbs(state, c->isdbt_sb_subchannel); in dib8000_set_isdbt_common_channel()
2413 dib8000_set_13seg_channel(state); in dib8000_set_isdbt_common_channel()
2418 dib8000_small_fine_tune(state); in dib8000_set_isdbt_common_channel()
2420 dib8000_set_subchannel_prbs(state, init_prbs); in dib8000_set_isdbt_common_channel()
2424 if ((((~state->seg_diff_mask) >> i) & 1) == 1) { in dib8000_set_isdbt_common_channel()
2425 …p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i -… in dib8000_set_isdbt_common_channel()
2426 …p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i … in dib8000_set_isdbt_common_channel()
2429 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */ in dib8000_set_isdbt_common_channel()
2430 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */ in dib8000_set_isdbt_common_channel()
2433 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */ in dib8000_set_isdbt_common_channel()
2434 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */ in dib8000_set_isdbt_common_channel()
2435 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */ in dib8000_set_isdbt_common_channel()
2438 …dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_… in dib8000_set_isdbt_common_channel()
2440 …dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be a… in dib8000_set_isdbt_common_channel()
2442 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */ in dib8000_set_isdbt_common_channel()
2443 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ in dib8000_set_isdbt_common_channel()
2445 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */ in dib8000_set_isdbt_common_channel()
2454 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */ in dib8000_set_isdbt_common_channel()
2455 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */ in dib8000_set_isdbt_common_channel()
2456 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */ in dib8000_set_isdbt_common_channel()
2460 if (state->isdbt_cfg_loaded == 0) in dib8000_set_isdbt_common_channel()
2461 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */ in dib8000_set_isdbt_common_channel()
2463 state->isdbt_cfg_loaded = 0; in dib8000_set_isdbt_common_channel()
2466 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal, in dib8000_wait_lock() argument
2474 if (state->revision == 0x8090) in dib8000_wait_lock()
2482 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); in dib8000_wait_lock()
2483 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); in dib8000_wait_lock()
2490 struct dib8000_state *state = fe->demodulator_priv; in dib8000_autosearch_start() local
2491 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_autosearch_start()
2493 u32 value, internal = state->cfg.pll->internal; in dib8000_autosearch_start()
2495 if (state->revision == 0x8090) in dib8000_autosearch_start()
2496 internal = dib8000_read32(state, 23) / 1000; in dib8000_autosearch_start()
2498 if ((state->revision >= 0x8002) && in dib8000_autosearch_start()
2499 (state->autosearch_state == AS_SEARCHING_FFT)) { in dib8000_autosearch_start()
2500 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */ in dib8000_autosearch_start()
2501 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */ in dib8000_autosearch_start()
2503 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P… in dib8000_autosearch_start()
2504 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ in dib8000_autosearch_start()
2505 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */ in dib8000_autosearch_start()
2506 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */ in dib8000_autosearch_start()
2507 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */ in dib8000_autosearch_start()
2508 …dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P… in dib8000_autosearch_start()
2510 if (state->revision == 0x8090) in dib8000_autosearch_start()
2511 …value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_se… in dib8000_autosearch_start()
2513 …value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_se… in dib8000_autosearch_start()
2515 dib8000_write_word(state, 17, 0); in dib8000_autosearch_start()
2516 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */ in dib8000_autosearch_start()
2517 dib8000_write_word(state, 19, 0); in dib8000_autosearch_start()
2518 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */ in dib8000_autosearch_start()
2519 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */ in dib8000_autosearch_start()
2520 dib8000_write_word(state, 22, value & 0xffff); in dib8000_autosearch_start()
2522 if (state->revision == 0x8090) in dib8000_autosearch_start()
2523 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2525 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2526 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */ in dib8000_autosearch_start()
2529 dib8000_write_word(state, 356, 0); in dib8000_autosearch_start()
2530 dib8000_write_word(state, 357, 0x111); in dib8000_autosearch_start()
2532 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart… in dib8000_autosearch_start()
2533 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart… in dib8000_autosearch_start()
2534 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_… in dib8000_autosearch_start()
2535 } else if ((state->revision >= 0x8002) && in dib8000_autosearch_start()
2536 (state->autosearch_state == AS_SEARCHING_GUARD)) { in dib8000_autosearch_start()
2546 c->transmission_mode = state->found_nfft; in dib8000_autosearch_start()
2548 dib8000_set_isdbt_common_channel(state, slist, 1); in dib8000_autosearch_start()
2551 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2552 if (state->revision == 0x8090) in dib8000_autosearch_start()
2553 …dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock… in dib8000_autosearch_start()
2555 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2556 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2559 if (state->revision == 0x8090) in dib8000_autosearch_start()
2560 …dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_… in dib8000_autosearch_start()
2562 …dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_… in dib8000_autosearch_start()
2564 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */ in dib8000_autosearch_start()
2567 dib8000_write_word(state, 356, 0); in dib8000_autosearch_start()
2568 dib8000_write_word(state, 357, 0xf); in dib8000_autosearch_start()
2570 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2571 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); in dib8000_autosearch_start()
2572 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ in dib8000_autosearch_start()
2573 dib8000_write_word(state, 0, (u16)value); in dib8000_autosearch_start()
2586 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); in dib8000_autosearch_start()
2593 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 t… in dib8000_autosearch_start()
2602 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ in dib8000_autosearch_start()
2609 dib8000_set_isdbt_common_channel(state, slist, 1); in dib8000_autosearch_start()
2612 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2613 if (state->revision == 0x8090) in dib8000_autosearch_start()
2614 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10)); in dib8000_autosearch_start()
2616 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2617 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2620 if (state->revision == 0x8090) in dib8000_autosearch_start()
2621 …dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_… in dib8000_autosearch_start()
2623 …dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_… in dib8000_autosearch_start()
2625 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2626 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); in dib8000_autosearch_start()
2627 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ in dib8000_autosearch_start()
2628 dib8000_write_word(state, 0, (u16)value); in dib8000_autosearch_start()
2635 struct dib8000_state *state = fe->demodulator_priv; in dib8000_autosearch_irq() local
2636 u16 irq_pending = dib8000_read_word(state, 1284); in dib8000_autosearch_irq()
2638 if ((state->revision >= 0x8002) && in dib8000_autosearch_irq()
2639 (state->autosearch_state == AS_SEARCHING_FFT)) { in dib8000_autosearch_irq()
2659 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff) in dib8000_viterbi_state() argument
2663 tmp = dib8000_read_word(state, 771); in dib8000_viterbi_state()
2665 dib8000_write_word(state, 771, tmp & 0xfffd); in dib8000_viterbi_state()
2667 dib8000_write_word(state, 771, tmp | (1<<1)); in dib8000_viterbi_state()
2670 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz) in dib8000_set_dds() argument
2674 u32 dds = state->cfg.pll->ifreq & 0x1ffffff; in dib8000_set_dds()
2675 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25)); in dib8000_set_dds()
2678 if (state->revision == 0x8090) { in dib8000_set_dds()
2680 unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000); in dib8000_set_dds()
2690 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal); in dib8000_set_dds()
2704 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) { in dib8000_set_dds()
2706 dib8000_write_word(state, 26, invert); in dib8000_set_dds()
2707 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff); in dib8000_set_dds()
2708 dib8000_write_word(state, 28, (u16)(dds & 0xffff)); in dib8000_set_dds()
2712 static void dib8000_set_frequency_offset(struct dib8000_state *state) in dib8000_set_frequency_offset() argument
2714 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_frequency_offset()
2719 if (state->fe[0]->ops.tuner_ops.get_frequency) in dib8000_set_frequency_offset()
2720 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf); in dib8000_set_frequency_offset()
2727 state->subchannel = c->isdbt_sb_subchannel; in dib8000_set_frequency_offset()
2729 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */ in dib8000_set_frequency_offset()
2730 dib8000_write_word(state, 26, c->inversion ^ i); in dib8000_set_frequency_offset()
2732 if (state->cfg.pll->ifreq == 0) { /* low if tuner */ in dib8000_set_frequency_offset()
2734 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); in dib8000_set_frequency_offset()
2744 dib8000_set_dds(state, total_dds_offset_khz); in dib8000_set_frequency_offset()
2749 static u32 dib8000_get_symbol_duration(struct dib8000_state *state) in dib8000_get_symbol_duration() argument
2751 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_symbol_duration()
2771 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_st… in dib8000_set_isdbt_loop_params() argument
2773 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_isdbt_loop_params()
2780 …reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha… in dib8000_set_isdbt_loop_params()
2781 …reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 … in dib8000_set_isdbt_loop_params()
2783 …reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha… in dib8000_set_isdbt_loop_params()
2784 …reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P… in dib8000_set_isdbt_loop_params()
2787 …reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6,… in dib8000_set_isdbt_loop_params()
2788 …reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P… in dib8000_set_isdbt_loop_params()
2794 …reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=… in dib8000_set_isdbt_loop_params()
2795 reg_37 = (12-state->mode) | ((5 + state->mode) << 5); in dib8000_set_isdbt_loop_params()
2797 …reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=… in dib8000_set_isdbt_loop_params()
2798 reg_37 = (11-state->mode) | ((5 + state->mode) << 5); in dib8000_set_isdbt_loop_params()
2801 …reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_… in dib8000_set_isdbt_loop_params()
2802 reg_37 = ((5+state->mode) << 5) | (10 - state->mode); in dib8000_set_isdbt_loop_params()
2806 dib8000_write_word(state, 32, reg_32); in dib8000_set_isdbt_loop_params()
2807 dib8000_write_word(state, 37, reg_37); in dib8000_set_isdbt_loop_params()
2810 static void dib8000_demod_restart(struct dib8000_state *state) in dib8000_demod_restart() argument
2812 dib8000_write_word(state, 770, 0x4000); in dib8000_demod_restart()
2813 dib8000_write_word(state, 770, 0x0000); in dib8000_demod_restart()
2817 static void dib8000_set_sync_wait(struct dib8000_state *state) in dib8000_set_sync_wait() argument
2819 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_sync_wait()
2836 if (state->cfg.diversity_delay == 0) in dib8000_set_sync_wait()
2839 …sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add … in dib8000_set_sync_wait()
2841 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); in dib8000_set_sync_wait()
2844 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode … in dib8000_get_timeout() argument
2847 delay *= state->symbol_duration; in dib8000_get_timeout()
2854 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_status() local
2855 return state->status; in dib8000_get_status()
2860 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_tune_state() local
2861 return state->tune_state; in dib8000_get_tune_state()
2866 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_tune_state() local
2868 state->tune_state = tune_state; in dib8000_set_tune_state()
2874 struct dib8000_state *state = fe->demodulator_priv; in dib8000_tune_restart_from_demod() local
2876 state->status = FE_STATUS_TUNE_PENDING; in dib8000_tune_restart_from_demod()
2877 state->tune_state = CT_DEMOD_START; in dib8000_tune_restart_from_demod()
2883 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_lock() local
2885 if (state->revision == 0x8090) in dib8000_read_lock()
2886 return dib8000_read_word(state, 570); in dib8000_read_lock()
2887 return dib8000_read_word(state, 568); in dib8000_read_lock()
2890 static int dib8090p_init_sdram(struct dib8000_state *state) in dib8090p_init_sdram() argument
2895 reg = dib8000_read_word(state, 274) & 0xfff0; in dib8090p_init_sdram()
2896 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ in dib8090p_init_sdram()
2898 dib8000_write_word(state, 1803, (7 << 2)); in dib8090p_init_sdram()
2900 reg = dib8000_read_word(state, 1280); in dib8090p_init_sdram()
2901 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */ in dib8090p_init_sdram()
2902 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */ in dib8090p_init_sdram()
2994 struct dib8000_state *state = fe->demodulator_priv; in dib8000_tune() local
2995 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_tune()
2996 enum frontend_tune_state *tune_state = &state->tune_state; in dib8000_tune()
3001 unsigned long *timeout = &state->timeout; in dib8000_tune()
3013 state->channel_parameters_set, *tune_state, state->autosearch_state, now); in dib8000_tune()
3020 if (state->revision == 0x8090) in dib8000_tune()
3021 dib8090p_init_sdram(state); in dib8000_tune()
3022 state->status = FE_STATUS_TUNE_PENDING; in dib8000_tune()
3023 state->channel_parameters_set = is_manual_mode(c); in dib8000_tune()
3026 state->channel_parameters_set ? "manual" : "auto"); in dib8000_tune()
3028 dib8000_viterbi_state(state, 0); /* force chan dec in restart */ in dib8000_tune()
3031 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); in dib8000_tune()
3033 dib8000_set_frequency_offset(state); in dib8000_tune()
3036 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */ in dib8000_tune()
3038 if (state->revision != 0x8090) { in dib8000_tune()
3039 state->agc1_max = dib8000_read_word(state, 108); in dib8000_tune()
3040 state->agc1_min = dib8000_read_word(state, 109); in dib8000_tune()
3041 state->agc2_max = dib8000_read_word(state, 110); in dib8000_tune()
3042 state->agc2_min = dib8000_read_word(state, 111); in dib8000_tune()
3043 agc1 = dib8000_read_word(state, 388); in dib8000_tune()
3044 agc2 = dib8000_read_word(state, 389); in dib8000_tune()
3045 dib8000_write_word(state, 108, agc1); in dib8000_tune()
3046 dib8000_write_word(state, 109, agc1); in dib8000_tune()
3047 dib8000_write_word(state, 110, agc2); in dib8000_tune()
3048 dib8000_write_word(state, 111, agc2); in dib8000_tune()
3051 state->autosearch_state = AS_SEARCHING_FFT; in dib8000_tune()
3052 state->found_nfft = TRANSMISSION_MODE_AUTO; in dib8000_tune()
3053 state->found_guard = GUARD_INTERVAL_AUTO; in dib8000_tune()
3056 state->autosearch_state = AS_DONE; in dib8000_tune()
3059 state->symbol_duration = dib8000_get_symbol_duration(state); in dib8000_tune()
3064 if (state->revision == 0x8090) in dib8000_tune()
3074 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3075 state->autosearch_state = AS_DONE; in dib8000_tune()
3079 …state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel foun… in dib8000_tune()
3081 if (state->autosearch_state == AS_SEARCHING_GUARD) in dib8000_tune()
3084 state->autosearch_state = AS_DONE; in dib8000_tune()
3093 switch (state->autosearch_state) { in dib8000_tune()
3096 if (state->revision == 0x8090) { in dib8000_tune()
3097 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); in dib8000_tune()
3098 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); in dib8000_tune()
3099 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601)); in dib8000_tune()
3101 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595)); in dib8000_tune()
3102 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); in dib8000_tune()
3103 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); in dib8000_tune()
3115 state->found_nfft = TRANSMISSION_MODE_2K; in dib8000_tune()
3118 state->found_nfft = TRANSMISSION_MODE_4K; in dib8000_tune()
3122 state->found_nfft = TRANSMISSION_MODE_8K; in dib8000_tune()
3128 state->autosearch_state = AS_SEARCHING_GUARD; in dib8000_tune()
3129 if (state->revision == 0x8090) in dib8000_tune()
3136 if (state->revision == 0x8090) in dib8000_tune()
3137 state->found_guard = dib8000_read_word(state, 572) & 0x3; in dib8000_tune()
3139 state->found_guard = dib8000_read_word(state, 570) & 0x3; in dib8000_tune()
3146 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3147 state->autosearch_state = AS_DONE; in dib8000_tune()
3154 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1); in dib8000_tune()
3155 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */ in dib8000_tune()
3160 dib8000_demod_restart(state); in dib8000_tune()
3162 dib8000_set_sync_wait(state); in dib8000_tune()
3163 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); in dib8000_tune()
3165 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */ in dib8000_tune()
3167 *timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON); in dib8000_tune()
3174 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */ in dib8000_tune()
3175 if (!state->differential_constellation) { in dib8000_tune()
3177 …*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEP… in dib8000_tune()
3188 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) { in dib8000_tune()
3190 …if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input… in dib8000_tune()
3192 …else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input faill… in dib8000_tune()
3194 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ in dib8000_tune()
3195 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); in dib8000_tune()
3196 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3199 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ in dib8000_tune()
3200 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); in dib8000_tune()
3202 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3216 dib8000_viterbi_state(state, 1); /* start viterbi chandec */ in dib8000_tune()
3217 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2); in dib8000_tune()
3222 && !state->differential_constellation) { in dib8000_tune()
3223 state->subchannel = 0; in dib8000_tune()
3227 state->status = FE_STATUS_LOCKED; in dib8000_tune()
3232 …if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable … in dib8000_tune()
3239 state->longest_intlv_layer = i; in dib8000_tune()
3251 if (state->diversity_onoff != 0) /* because of diversity sync */ in dib8000_tune()
3256 deeper_interleaver, state->longest_intlv_layer, locks, *timeout); in dib8000_tune()
3265 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */ in dib8000_tune()
3272 && !state->differential_constellation) in dib8000_tune()
3274 state->status = FE_STATUS_DEMOD_SUCCESS; in dib8000_tune()
3276 state->status = FE_STATUS_DATA_LOCKED; in dib8000_tune()
3281 && !state->differential_constellation) { /* continue to try init prbs autosearch */ in dib8000_tune()
3282 state->subchannel += 3; in dib8000_tune()
3292 state->status = FE_STATUS_DATA_LOCKED; in dib8000_tune()
3294 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3301 if (state->subchannel <= 41) { in dib8000_tune()
3302 dib8000_set_subchannel_prbs(state, dib8000_get_init_prbs(state, state->subchannel)); in dib8000_tune()
3306 state->status = FE_STATUS_TUNE_FAILED; in dib8000_tune()
3318 if ((state->revision != 0x8090) && (state->agc1_max != 0)) { in dib8000_tune()
3319 dib8000_write_word(state, 108, state->agc1_max); in dib8000_tune()
3320 dib8000_write_word(state, 109, state->agc1_min); in dib8000_tune()
3321 dib8000_write_word(state, 110, state->agc2_max); in dib8000_tune()
3322 dib8000_write_word(state, 111, state->agc2_min); in dib8000_tune()
3323 state->agc1_max = 0; in dib8000_tune()
3324 state->agc1_min = 0; in dib8000_tune()
3325 state->agc2_max = 0; in dib8000_tune()
3326 state->agc2_min = 0; in dib8000_tune()
3336 return ret * state->symbol_duration; in dib8000_tune()
3337 if ((ret > 0) && (ret < state->symbol_duration)) in dib8000_tune()
3338 return state->symbol_duration; /* at least one symbol */ in dib8000_tune()
3344 struct dib8000_state *state = fe->demodulator_priv; in dib8000_wakeup() local
3348 dib8000_set_power_mode(state, DIB8000_POWER_ALL); in dib8000_wakeup()
3349 dib8000_set_adc_state(state, DIBX000_ADC_ON); in dib8000_wakeup()
3350 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) in dib8000_wakeup()
3353 if (state->revision == 0x8090) in dib8000_wakeup()
3354 dib8000_sad_calib(state); in dib8000_wakeup()
3356 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_wakeup()
3357 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]); in dib8000_wakeup()
3367 struct dib8000_state *state = fe->demodulator_priv; in dib8000_sleep() local
3371 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_sleep()
3372 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]); in dib8000_sleep()
3377 if (state->revision != 0x8090) in dib8000_sleep()
3379 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY); in dib8000_sleep()
3380 …return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_A… in dib8000_sleep()
3387 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_frontend() local
3404 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_get_frontend()
3405 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat); in dib8000_get_frontend()
3409 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]); in dib8000_get_frontend()
3410 …for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_inde… in dib8000_get_frontend()
3412 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_p… in dib8000_get_frontend()
3413 …state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_prope… in dib8000_get_frontend()
3414 …state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->d… in dib8000_get_frontend()
3415 …state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_… in dib8000_get_frontend()
3416 …state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_fronte… in dib8000_get_frontend()
3418 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_fronten… in dib8000_get_frontend()
3419 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend… in dib8000_get_frontend()
3420 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_pr… in dib8000_get_frontend()
3421 …state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]-… in dib8000_get_frontend()
3429 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; in dib8000_get_frontend()
3431 if (state->revision == 0x8090) in dib8000_get_frontend()
3432 val = dib8000_read_word(state, 572); in dib8000_get_frontend()
3434 val = dib8000_read_word(state, 570); in dib8000_get_frontend()
3471 val = dib8000_read_word(state, 505); in dib8000_get_frontend()
3478 val = dib8000_read_word(state, 493 + i) & 0x0f; in dib8000_get_frontend()
3490 val = dib8000_read_word(state, 499 + i) & 0x3; in dib8000_get_frontend()
3499 val = dib8000_read_word(state, 481 + i); in dib8000_get_frontend()
3528 val = dib8000_read_word(state, 487 + i); in dib8000_get_frontend()
3555 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_get_frontend()
3556 …state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode; in dib8000_get_frontend()
3557 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion; in dib8000_get_frontend()
3558 …state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmiss… in dib8000_get_frontend()
3559 …state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interv… in dib8000_get_frontend()
3560 …state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isd… in dib8000_get_frontend()
3562 …state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.laye… in dib8000_get_frontend()
3563 …state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer… in dib8000_get_frontend()
3564 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec; in dib8000_get_frontend()
3565 …state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i… in dib8000_get_frontend()
3573 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_frontend() local
3574 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_frontend()
3589 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3591 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT; in dib8000_set_frontend()
3592 …memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_… in dib8000_set_frontend()
3595 if (state->revision != 0x8090) { in dib8000_set_frontend()
3596 dib8000_set_diversity_in(state->fe[index_frontend], 1); in dib8000_set_frontend()
3598 dib8000_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
3601 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); in dib8000_set_frontend()
3603 dib8096p_set_diversity_in(state->fe[index_frontend], 1); in dib8000_set_frontend()
3605 dib8096p_set_output_mode(state->fe[index_frontend], in dib8000_set_frontend()
3608 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); in dib8000_set_frontend()
3612 if (state->fe[index_frontend]->ops.tuner_ops.set_params) in dib8000_set_frontend()
3613 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]); in dib8000_set_frontend()
3615 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START); in dib8000_set_frontend()
3619 if (state->revision != 0x8090) in dib8000_set_frontend()
3620 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0); in dib8000_set_frontend()
3622 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0); in dib8000_set_frontend()
3626 time = dib8000_agc_startup(state->fe[0]); in dib8000_set_frontend()
3627 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3628 time_slave = dib8000_agc_startup(state->fe[index_frontend]); in dib8000_set_frontend()
3648 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3649 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) { in dib8000_set_frontend()
3656 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3657 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START); in dib8000_set_frontend()
3662 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3663 delay = dib8000_tune(state->fe[index_frontend]); in dib8000_set_frontend()
3671 if (state->channel_parameters_set == 0) { /* searching */ in dib8000_set_frontend()
3672 …if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_sta… in dib8000_set_frontend()
3674 …dib8000_get_frontend(state->fe[index_frontend]); /* we read the channel parameters from the fronte… in dib8000_set_frontend()
3675 state->channel_parameters_set = 1; in dib8000_set_frontend()
3677 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) { in dib8000_set_frontend()
3680 dib8000_tune_restart_from_demod(state->fe[l]); in dib8000_set_frontend()
3682 …state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isd… in dib8000_set_frontend()
3683 …state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversi… in dib8000_set_frontend()
3684 …state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache… in dib8000_set_frontend()
3685 …state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.gu… in dib8000_set_frontend()
3686 …state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property… in dib8000_set_frontend()
3688 …state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_… in dib8000_set_frontend()
3689 …state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_c… in dib8000_set_frontend()
3690 …state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.laye… in dib8000_set_frontend()
3691 …state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cac… in dib8000_set_frontend()
3700 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED || in dib8000_set_frontend()
3701 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED || in dib8000_set_frontend()
3702 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) { in dib8000_set_frontend()
3705 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3706 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP) in dib8000_set_frontend()
3710 dprintk("tuning done with status %d", dib8000_get_status(state->fe[0])); in dib8000_set_frontend()
3723 if (state->revision != 0x8090) in dib8000_set_frontend()
3724 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3726 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3727 if (state->cfg.enMpegOutput == 0) { in dib8000_set_frontend()
3728 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX); in dib8000_set_frontend()
3729 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS); in dib8000_set_frontend()
3740 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_status() local
3745 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_status()
3746 lock_slave |= dib8000_read_lock(state->fe[index_frontend]); in dib8000_read_status()
3763 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */ in dib8000_read_status()
3767 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */ in dib8000_read_status()
3771 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */ in dib8000_read_status()
3782 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_ber() local
3785 if (state->revision == 0x8090) in dib8000_read_ber()
3786 *ber = (dib8000_read_word(state, 562) << 16) | in dib8000_read_ber()
3787 dib8000_read_word(state, 563); in dib8000_read_ber()
3789 *ber = (dib8000_read_word(state, 560) << 16) | in dib8000_read_ber()
3790 dib8000_read_word(state, 561); in dib8000_read_ber()
3796 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_unc_blocks() local
3799 if (state->revision == 0x8090) in dib8000_read_unc_blocks()
3800 *unc = dib8000_read_word(state, 567); in dib8000_read_unc_blocks()
3802 *unc = dib8000_read_word(state, 565); in dib8000_read_unc_blocks()
3808 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_signal_strength() local
3813 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_signal_strength()
3814 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val); in dib8000_read_signal_strength()
3821 val = 65535 - dib8000_read_word(state, 390); in dib8000_read_signal_strength()
3831 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_snr() local
3835 if (state->revision != 0x8090) in dib8000_get_snr()
3836 val = dib8000_read_word(state, 542); in dib8000_get_snr()
3838 val = dib8000_read_word(state, 544); in dib8000_get_snr()
3845 if (state->revision != 0x8090) in dib8000_get_snr()
3846 val = dib8000_read_word(state, 543); in dib8000_get_snr()
3848 val = dib8000_read_word(state, 545); in dib8000_get_snr()
3864 struct dib8000_state *state = fe->demodulator_priv; in dib8000_read_snr() local
3869 …for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_read_snr()
3870 snr_master += dib8000_get_snr(state->fe[index_frontend]); in dib8000_read_snr()
3980 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_time_us() local
3981 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_time_us()
4094 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_stats() local
4095 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_stats()
4127 if (time_after(jiffies, state->per_jiffies_stats)) { in dib8000_get_stats()
4128 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000); in dib8000_get_stats()
4133 if (state->fe[i]) in dib8000_get_stats()
4134 snr += dib8000_get_snr(state->fe[i]); in dib8000_get_stats()
4149 if (val < state->init_ucb) in dib8000_get_stats()
4150 state->init_ucb += 0x100000000LL; in dib8000_get_stats()
4153 c->block_error.stat[0].uvalue = val + state->init_ucb; in dib8000_get_stats()
4170 if (time_after(jiffies, state->ber_jiffies_stats)) { in dib8000_get_stats()
4172 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000); in dib8000_get_stats()
4184 if (state->revision < 0x8002) in dib8000_get_stats()
4199 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) { in dib8000_get_stats()
4202 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000); in dib8000_get_stats()
4206 val = dib8000_read_word(state, per_layer_regs[i].ber); in dib8000_get_stats()
4215 val = dib8000_read_word(state, per_layer_regs[i].per); in dib8000_get_stats()
4235 struct dib8000_state *state = fe->demodulator_priv; in dib8000_set_slave_frontend() local
4238 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) in dib8000_set_slave_frontend()
4242 state->fe[index_frontend] = fe_slave; in dib8000_set_slave_frontend()
4252 struct dib8000_state *state = fe->demodulator_priv; in dib8000_remove_slave_frontend() local
4255 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL)) in dib8000_remove_slave_frontend()
4258 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1); in dib8000_remove_slave_frontend()
4259 state->fe[index_frontend] = NULL; in dib8000_remove_slave_frontend()
4269 struct dib8000_state *state = fe->demodulator_priv; in dib8000_get_slave_frontend() local
4273 return state->fe[slave_index]; in dib8000_get_slave_frontend()
4431 struct dib8000_state *state; in dib8000_init() local
4435 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL); in dib8000_init()
4436 if (state == NULL) in dib8000_init()
4442 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); in dib8000_init()
4443 state->i2c.adap = i2c_adap; in dib8000_init()
4444 state->i2c.addr = i2c_addr; in dib8000_init()
4445 state->i2c.i2c_write_buffer = state->i2c_write_buffer; in dib8000_init()
4446 state->i2c.i2c_read_buffer = state->i2c_read_buffer; in dib8000_init()
4447 mutex_init(&state->i2c_buffer_lock); in dib8000_init()
4448 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock; in dib8000_init()
4449 state->gpio_val = cfg->gpio_val; in dib8000_init()
4450 state->gpio_dir = cfg->gpio_dir; in dib8000_init()
4455 …if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_P… in dib8000_init()
4456 state->cfg.output_mode = OUTMODE_MPEG2_FIFO; in dib8000_init()
4458 state->fe[0] = fe; in dib8000_init()
4459 fe->demodulator_priv = state; in dib8000_init()
4460 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); in dib8000_init()
4462 state->timf_default = cfg->pll->timf; in dib8000_init()
4464 if (dib8000_identify(&state->i2c) == 0) in dib8000_init()
4467 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr); in dib8000_init()
4470 strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface", in dib8000_init()
4471 sizeof(state->dib8096p_tuner_adap.name)); in dib8000_init()
4472 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo; in dib8000_init()
4473 state->dib8096p_tuner_adap.algo_data = NULL; in dib8000_init()
4474 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent; in dib8000_init()
4475 i2c_set_adapdata(&state->dib8096p_tuner_adap, state); in dib8000_init()
4476 i2c_add_adapter(&state->dib8096p_tuner_adap); in dib8000_init()
4480 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len … in dib8000_init()
4481 state->current_demod_bw = 6000; in dib8000_init()
4486 kfree(state); in dib8000_init()