Lines Matching refs:state

59 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)  in ves1820_writereg()  argument
62 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 }; in ves1820_writereg()
65 ret = i2c_transfer(state->i2c, &msg, 1); in ves1820_writereg()
74 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg) in ves1820_readreg() argument
79 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2}, in ves1820_readreg()
80 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1} in ves1820_readreg()
84 ret = i2c_transfer(state->i2c, msg, 2); in ves1820_readreg()
93 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversi… in ves1820_setup_reg0() argument
95 reg0 |= state->reg0 & 0x62; in ves1820_setup_reg0()
98 if (!state->config->invert) reg0 |= 0x20; in ves1820_setup_reg0()
101 if (!state->config->invert) reg0 &= ~0x20; in ves1820_setup_reg0()
105 ves1820_writereg(state, 0x00, reg0 & 0xfe); in ves1820_setup_reg0()
106 ves1820_writereg(state, 0x00, reg0 | 0x01); in ves1820_setup_reg0()
108 state->reg0 = reg0; in ves1820_setup_reg0()
113 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate) in ves1820_set_symbolrate() argument
125 if (symbolrate > state->config->xin / 2) in ves1820_set_symbolrate()
126 symbolrate = state->config->xin / 2; in ves1820_set_symbolrate()
131 if (symbolrate < state->config->xin / 16) in ves1820_set_symbolrate()
133 if (symbolrate < state->config->xin / 32) in ves1820_set_symbolrate()
135 if (symbolrate < state->config->xin / 64) in ves1820_set_symbolrate()
139 fpxin = state->config->xin * 10; in ves1820_set_symbolrate()
162 fin = state->config->xin >> 4; in ves1820_set_symbolrate()
171 BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2; in ves1820_set_symbolrate()
180 ves1820_writereg(state, 0x03, NDEC); in ves1820_set_symbolrate()
181 ves1820_writereg(state, 0x0a, BDR & 0xff); in ves1820_set_symbolrate()
182 ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff); in ves1820_set_symbolrate()
183 ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f); in ves1820_set_symbolrate()
185 ves1820_writereg(state, 0x0d, BDRI); in ves1820_set_symbolrate()
186 ves1820_writereg(state, 0x0e, SFIL); in ves1820_set_symbolrate()
193 struct ves1820_state* state = fe->demodulator_priv; in ves1820_init() local
196 ves1820_writereg(state, 0, 0); in ves1820_init()
199 ves1820_writereg(state, i, ves1820_inittab[i]); in ves1820_init()
200 if (state->config->selagc) in ves1820_init()
201 ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08); in ves1820_init()
203 ves1820_writereg(state, 0x34, state->pwm); in ves1820_init()
211 struct ves1820_state* state = fe->demodulator_priv; in ves1820_set_parameters() local
227 ves1820_set_symbolrate(state, p->symbol_rate); in ves1820_set_parameters()
228 ves1820_writereg(state, 0x34, state->pwm); in ves1820_set_parameters()
230 ves1820_writereg(state, 0x01, reg0x01[real_qam]); in ves1820_set_parameters()
231 ves1820_writereg(state, 0x05, reg0x05[real_qam]); in ves1820_set_parameters()
232 ves1820_writereg(state, 0x08, reg0x08[real_qam]); in ves1820_set_parameters()
233 ves1820_writereg(state, 0x09, reg0x09[real_qam]); in ves1820_set_parameters()
235 ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion); in ves1820_set_parameters()
236 ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0)); in ves1820_set_parameters()
242 struct ves1820_state* state = fe->demodulator_priv; in ves1820_read_status() local
246 sync = ves1820_readreg(state, 0x11); in ves1820_read_status()
268 struct ves1820_state* state = fe->demodulator_priv; in ves1820_read_ber() local
270 u32 _ber = ves1820_readreg(state, 0x14) | in ves1820_read_ber()
271 (ves1820_readreg(state, 0x15) << 8) | in ves1820_read_ber()
272 ((ves1820_readreg(state, 0x16) & 0x0f) << 16); in ves1820_read_ber()
280 struct ves1820_state* state = fe->demodulator_priv; in ves1820_read_signal_strength() local
282 u8 gain = ves1820_readreg(state, 0x17); in ves1820_read_signal_strength()
290 struct ves1820_state* state = fe->demodulator_priv; in ves1820_read_snr() local
292 u8 quality = ~ves1820_readreg(state, 0x18); in ves1820_read_snr()
300 struct ves1820_state* state = fe->demodulator_priv; in ves1820_read_ucblocks() local
302 *ucblocks = ves1820_readreg(state, 0x13) & 0x7f; in ves1820_read_ucblocks()
307 ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf); in ves1820_read_ucblocks()
308 ves1820_writereg(state, 0x10, ves1820_inittab[0x10]); in ves1820_read_ucblocks()
316 struct ves1820_state* state = fe->demodulator_priv; in ves1820_get_frontend() local
320 sync = ves1820_readreg(state, 0x11); in ves1820_get_frontend()
321 afc = ves1820_readreg(state, 0x19); in ves1820_get_frontend()
328 if (!state->config->invert) { in ves1820_get_frontend()
329 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF; in ves1820_get_frontend()
331 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF; in ves1820_get_frontend()
334 p->modulation = ((state->reg0 >> 2) & 7) + QAM_16; in ves1820_get_frontend()
347 struct ves1820_state* state = fe->demodulator_priv; in ves1820_sleep() local
349 ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */ in ves1820_sleep()
350 ves1820_writereg(state, 0x00, 0x80); /* standby */ in ves1820_sleep()
366 struct ves1820_state* state = fe->demodulator_priv; in ves1820_release() local
367 kfree(state); in ves1820_release()
376 struct ves1820_state* state = NULL; in ves1820_attach() local
379 state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL); in ves1820_attach()
380 if (state == NULL) in ves1820_attach()
384 state->reg0 = ves1820_inittab[0]; in ves1820_attach()
385 state->config = config; in ves1820_attach()
386 state->i2c = i2c; in ves1820_attach()
387 state->pwm = pwm; in ves1820_attach()
390 if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70) in ves1820_attach()
394 printk("ves1820: pwm=0x%02x\n", state->pwm); in ves1820_attach()
397 memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops)); in ves1820_attach()
398state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN… in ves1820_attach()
399 state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */ in ves1820_attach()
400 state->frontend.demodulator_priv = state; in ves1820_attach()
402 return &state->frontend; in ves1820_attach()
405 kfree(state); in ves1820_attach()