Lines Matching refs:state
242 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) in nv3_iterate() argument
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; in nv3_iterate()
277 if (state->enable_mp) in nv3_iterate()
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; in nv3_iterate()
290 if (!state->gr_during_vid && ainfo->vid_en) in nv3_iterate()
340 … ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; in nv3_iterate()
344 …ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mcl… in nv3_iterate()
356 … ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; in nv3_iterate()
360 …ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mcl… in nv3_iterate()
370 … ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; in nv3_iterate()
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; in nv3_iterate()
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; in nv3_iterate()
427 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) in nv3_arb() argument
433 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; in nv3_arb()
435 if (state->mem_aligned) gmisses = 2; in nv3_arb()
438 eburst_size = state->memory_width * 1; in nv3_arb()
440 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; in nv3_arb()
451 …ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->… in nv3_arb()
452 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; in nv3_arb()
459 nv3_iterate(res_info, state,ainfo); in nv3_arb()
461 if (state->enable_mp) in nv3_arb()
463 …mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycl… in nv3_arb()
464 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; in nv3_arb()
471 nv3_iterate(res_info, state,ainfo); in nv3_arb()
478 …gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh… in nv3_arb()
481 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; in nv3_arb()
483 nv3_iterate(res_info, state,ainfo); in nv3_arb()
490 …vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh… in nv3_arb()
493 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; in nv3_arb()
495 nv3_iterate(res_info, state, ainfo); in nv3_arb()
533 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) in nv3_get_param() argument
547 done = nv3_arb(res_info, state,ainfo); in nv3_get_param()
563 nv3_sim_state * state in nv3CalcArbitration() argument
571 ainfo.vid_en = state->enable_video; in nv3CalcArbitration()
574 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); in nv3CalcArbitration()
575 ainfo.vdrain_rate = (int) state->pclk_khz * 2; in nv3CalcArbitration()
576 if (state->video_scale != 0) in nv3CalcArbitration()
577 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; in nv3CalcArbitration()
580 if (!state->gr_during_vid && state->enable_video) in nv3CalcArbitration()
585 res_vid = nv3_get_param(res_info, state, &ainfo); in nv3CalcArbitration()
592 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); in nv3CalcArbitration()
594 res_gr = nv3_get_param(res_info, state, &ainfo); in nv3CalcArbitration()
604 res_gr = nv3_get_param(res_info, state, &ainfo); in nv3CalcArbitration()
1236 RIVA_HW_STATE *state, in CalcStateExt() argument
1251 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ in CalcStateExt()
1252 state->width = width; in CalcStateExt()
1253 state->height = height; in CalcStateExt()
1266 &(state->arbitration0), in CalcStateExt()
1267 &(state->arbitration1), in CalcStateExt()
1269 state->cursor0 = 0x00; in CalcStateExt()
1270 state->cursor1 = 0x78; in CalcStateExt()
1271 state->cursor2 = 0x00000000; in CalcStateExt()
1272 state->pllsel = 0x10010100; in CalcStateExt()
1273 state->config = ((width + 31)/32) in CalcStateExt()
1276 state->general = 0x00100100; in CalcStateExt()
1277 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; in CalcStateExt()
1282 &(state->arbitration0), in CalcStateExt()
1283 &(state->arbitration1), in CalcStateExt()
1285 state->cursor0 = 0x00; in CalcStateExt()
1286 state->cursor1 = 0xFC; in CalcStateExt()
1287 state->cursor2 = 0x00000000; in CalcStateExt()
1288 state->pllsel = 0x10000700; in CalcStateExt()
1289 state->config = 0x00001114; in CalcStateExt()
1290 state->general = bpp == 16 ? 0x00101100 : 0x00100100; in CalcStateExt()
1291 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; in CalcStateExt()
1301 &(state->arbitration0), in CalcStateExt()
1302 &(state->arbitration1), in CalcStateExt()
1307 &(state->arbitration0), in CalcStateExt()
1308 &(state->arbitration1), in CalcStateExt()
1311 state->cursor0 = 0x80 | (chip->CursorStart >> 17); in CalcStateExt()
1312 state->cursor1 = (chip->CursorStart >> 11) << 2; in CalcStateExt()
1313 state->cursor2 = chip->CursorStart >> 24; in CalcStateExt()
1314 state->pllsel = 0x10000700; in CalcStateExt()
1315 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); in CalcStateExt()
1316 state->general = bpp == 16 ? 0x00101100 : 0x00100100; in CalcStateExt()
1317 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; in CalcStateExt()
1324 state->general |= 0x00000030; in CalcStateExt()
1326 state->vpll = (p << 16) | (n << 8) | m; in CalcStateExt()
1327 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; in CalcStateExt()
1328 state->pixel = pixelDepth > 2 ? 3 : pixelDepth; in CalcStateExt()
1329 state->offset0 = in CalcStateExt()
1330 state->offset1 = in CalcStateExt()
1331 state->offset2 = in CalcStateExt()
1332 state->offset3 = 0; in CalcStateExt()
1333 state->pitch0 = in CalcStateExt()
1334 state->pitch1 = in CalcStateExt()
1335 state->pitch2 = in CalcStateExt()
1336 state->pitch3 = pixelDepth * width; in CalcStateExt()
1407 RIVA_HW_STATE *state in LoadStateExt() argument
1423 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1427 switch (state->bpp) in LoadStateExt()
1450 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); in LoadStateExt()
1451 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); in LoadStateExt()
1452 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); in LoadStateExt()
1453 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); in LoadStateExt()
1454 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); in LoadStateExt()
1455 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); in LoadStateExt()
1456 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); in LoadStateExt()
1457 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); in LoadStateExt()
1463 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1467 switch (state->bpp) in LoadStateExt()
1492 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1493 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1494 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1495 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1496 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1497 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1498 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1499 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1506 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); in LoadStateExt()
1513 switch (state->bpp) in LoadStateExt()
1540 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); in LoadStateExt()
1541 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); in LoadStateExt()
1542 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); in LoadStateExt()
1543 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); in LoadStateExt()
1544 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); in LoadStateExt()
1545 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); in LoadStateExt()
1546 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); in LoadStateExt()
1547 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); in LoadStateExt()
1548 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); in LoadStateExt()
1550 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); in LoadStateExt()
1551 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); in LoadStateExt()
1552 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); in LoadStateExt()
1553 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); in LoadStateExt()
1554 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); in LoadStateExt()
1555 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); in LoadStateExt()
1556 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); in LoadStateExt()
1557 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); in LoadStateExt()
1558 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); in LoadStateExt()
1559 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); in LoadStateExt()
1564 NV_WR32(chip->PCRTC0, 0x00000860, state->head); in LoadStateExt()
1565 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); in LoadStateExt()
1660 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); in LoadStateExt()
1664 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); in LoadStateExt()
1667 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); in LoadStateExt()
1679 VGA_WR08(chip->PCIO, 0x03D5, state->extra); in LoadStateExt()
1687 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); in LoadStateExt()
1689 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); in LoadStateExt()
1691 VGA_WR08(chip->PCIO, 0x03D5, state->screen); in LoadStateExt()
1693 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); in LoadStateExt()
1695 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); in LoadStateExt()
1697 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); in LoadStateExt()
1699 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); in LoadStateExt()
1701 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); in LoadStateExt()
1703 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); in LoadStateExt()
1705 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); in LoadStateExt()
1707 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); in LoadStateExt()
1710 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); in LoadStateExt()
1711 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); in LoadStateExt()
1713 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); in LoadStateExt()
1715 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); in LoadStateExt()
1717 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); in LoadStateExt()
1731 chip->CurrentState = state; in LoadStateExt()
1742 RIVA_HW_STATE *state in UnloadStateExt() argument
1749 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1751 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1753 state->screen = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1755 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1757 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1759 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1761 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1763 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1765 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1767 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1769 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1770 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); in UnloadStateExt()
1771 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); in UnloadStateExt()
1772 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); in UnloadStateExt()
1773 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); in UnloadStateExt()
1774 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); in UnloadStateExt()
1775 state->config = NV_RD32(chip->PFB, 0x00000200); in UnloadStateExt()
1779 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); in UnloadStateExt()
1780 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); in UnloadStateExt()
1781 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); in UnloadStateExt()
1782 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); in UnloadStateExt()
1783 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); in UnloadStateExt()
1784 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); in UnloadStateExt()
1785 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); in UnloadStateExt()
1786 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); in UnloadStateExt()
1789 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1790 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1791 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1792 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1793 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1794 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1795 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1796 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1801 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); in UnloadStateExt()
1802 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); in UnloadStateExt()
1803 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); in UnloadStateExt()
1804 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); in UnloadStateExt()
1805 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); in UnloadStateExt()
1806 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); in UnloadStateExt()
1807 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); in UnloadStateExt()
1808 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); in UnloadStateExt()
1810 state->head = NV_RD32(chip->PCRTC0, 0x00000860); in UnloadStateExt()
1811 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); in UnloadStateExt()
1813 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1816 state->extra = VGA_RD08(chip->PCIO, 0x03D5); in UnloadStateExt()
1817 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); in UnloadStateExt()
1820 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); in UnloadStateExt()
1823 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); in UnloadStateExt()