216 static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)  in dib0090_read_reg()  argument
220 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib0090_read_reg()
225 	state->i2c_write_buffer[0] = reg;  in dib0090_read_reg()
227 	memset(state->msg, 0, 2 * sizeof(struct i2c_msg));  in dib0090_read_reg()
228 	state->msg[0].addr = state->config->i2c_address;  in dib0090_read_reg()
229 	state->msg[0].flags = 0;  in dib0090_read_reg()
230 	state->msg[0].buf = state->i2c_write_buffer;  in dib0090_read_reg()
231 	state->msg[0].len = 1;  in dib0090_read_reg()
232 	state->msg[1].addr = state->config->i2c_address;  in dib0090_read_reg()
233 	state->msg[1].flags = I2C_M_RD;  in dib0090_read_reg()
234 	state->msg[1].buf = state->i2c_read_buffer;  in dib0090_read_reg()
235 	state->msg[1].len = 2;  in dib0090_read_reg()
237 	if (i2c_transfer(state->i2c, state->msg, 2) != 2) {  in dib0090_read_reg()
241 		ret = (state->i2c_read_buffer[0] << 8)  in dib0090_read_reg()
242 			| state->i2c_read_buffer[1];  in dib0090_read_reg()
244 	mutex_unlock(&state->i2c_buffer_lock);  in dib0090_read_reg()
248 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)  in dib0090_write_reg()  argument
252 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib0090_write_reg()
257 	state->i2c_write_buffer[0] = reg & 0xff;  in dib0090_write_reg()
258 	state->i2c_write_buffer[1] = val >> 8;  in dib0090_write_reg()
259 	state->i2c_write_buffer[2] = val & 0xff;  in dib0090_write_reg()
261 	memset(state->msg, 0, sizeof(struct i2c_msg));  in dib0090_write_reg()
262 	state->msg[0].addr = state->config->i2c_address;  in dib0090_write_reg()
263 	state->msg[0].flags = 0;  in dib0090_write_reg()
264 	state->msg[0].buf = state->i2c_write_buffer;  in dib0090_write_reg()
265 	state->msg[0].len = 3;  in dib0090_write_reg()
267 	if (i2c_transfer(state->i2c, state->msg, 1) != 1) {  in dib0090_write_reg()
273 	mutex_unlock(&state->i2c_buffer_lock);  in dib0090_write_reg()
277 static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)  in dib0090_fw_read_reg()  argument
281 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib0090_fw_read_reg()
286 	state->i2c_write_buffer[0] = reg;  in dib0090_fw_read_reg()
288 	memset(&state->msg, 0, sizeof(struct i2c_msg));  in dib0090_fw_read_reg()
289 	state->msg.addr = reg;  in dib0090_fw_read_reg()
290 	state->msg.flags = I2C_M_RD;  in dib0090_fw_read_reg()
291 	state->msg.buf = state->i2c_read_buffer;  in dib0090_fw_read_reg()
292 	state->msg.len = 2;  in dib0090_fw_read_reg()
293 	if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {  in dib0090_fw_read_reg()
297 		ret = (state->i2c_read_buffer[0] << 8)  in dib0090_fw_read_reg()
298 			| state->i2c_read_buffer[1];  in dib0090_fw_read_reg()
300 	mutex_unlock(&state->i2c_buffer_lock);  in dib0090_fw_read_reg()
304 static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)  in dib0090_fw_write_reg()  argument
308 	if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {  in dib0090_fw_write_reg()
313 	state->i2c_write_buffer[0] = val >> 8;  in dib0090_fw_write_reg()
314 	state->i2c_write_buffer[1] = val & 0xff;  in dib0090_fw_write_reg()
316 	memset(&state->msg, 0, sizeof(struct i2c_msg));  in dib0090_fw_write_reg()
317 	state->msg.addr = reg;  in dib0090_fw_write_reg()
318 	state->msg.flags = 0;  in dib0090_fw_write_reg()
319 	state->msg.buf = state->i2c_write_buffer;  in dib0090_fw_write_reg()
320 	state->msg.len = 2;  in dib0090_fw_write_reg()
321 	if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {  in dib0090_fw_write_reg()
327 	mutex_unlock(&state->i2c_buffer_lock);  in dib0090_fw_write_reg()
331 #define HARD_RESET(state) do {  if (cfg->reset) {  if (cfg->sleep) cfg->sleep(fe, 0); msleep(10);  …  argument
336 static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, u8 c)  in dib0090_write_regs()  argument
339 		dib0090_write_reg(state, r++, *b++);  in dib0090_write_regs()
345 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_identify()  local
347 	struct dib0090_identity *identity = &state->identity;  in dib0090_identify()
349 	v = dib0090_read_reg(state, 0x1a);  in dib0090_identify()
437 	struct dib0090_fw_state *state = fe->tuner_priv;  in dib0090_fw_identify()  local
438 	struct dib0090_identity *identity = &state->identity;  in dib0090_fw_identify()
440 	u16 v = dib0090_fw_read_reg(state, 0x1a);  in dib0090_fw_identify()
527 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_reset_digital()  local
530 	HARD_RESET(state);  in dib0090_reset_digital()
531 	dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);  in dib0090_reset_digital()
535 …dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL);	/* PLL, DIG_CLK and CRYSTAL remai…  in dib0090_reset_digital()
537 …dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 <…  in dib0090_reset_digital()
539 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | …  in dib0090_reset_digital()
542 …dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | …  in dib0090_reset_digital()
546 	PllCfg = dib0090_read_reg(state, 0x21);  in dib0090_reset_digital()
554 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
558 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
562 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
566 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
571 			v = !!(dib0090_read_reg(state, 0x1a) & 0x800);  in dib0090_reset_digital()
583 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
588 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
594 	struct dib0090_fw_state *state = fe->tuner_priv;  in dib0090_fw_reset_digital()  local
600 	HARD_RESET(state);  in dib0090_fw_reset_digital()
602 	dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);  in dib0090_fw_reset_digital()
603 …dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL);	/* PLL, DIG_CLK and CRYSTAL re…  in dib0090_fw_reset_digital()
605 	dib0090_fw_write_reg(state, 0x20,  in dib0090_fw_reset_digital()
615 	dib0090_fw_write_reg(state, 0x23, v);  in dib0090_fw_reset_digital()
618 	PllCfg = dib0090_fw_read_reg(state, 0x21);  in dib0090_fw_reset_digital()
625 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
629 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
633 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
637 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
642 			v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);  in dib0090_fw_reset_digital()
654 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
659 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
667 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_wakeup()  local
668 	if (state->config->sleep)  in dib0090_wakeup()
669 		state->config->sleep(fe, 0);  in dib0090_wakeup()
672 	dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));  in dib0090_wakeup()
678 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_sleep()  local
679 	if (state->config->sleep)  in dib0090_sleep()
680 		state->config->sleep(fe, 1);  in dib0090_sleep()
686 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_dcc_freq()  local
688 		dib0090_write_reg(state, 0x04, 0);  in dib0090_dcc_freq()
690 		dib0090_write_reg(state, 0x04, 1);  in dib0090_dcc_freq()
892 static s16 dib0090_wbd_to_db(struct dib0090_state *state, u16 wbd)  in dib0090_wbd_to_db()  argument
895 	if (wbd < state->wbd_offset)  in dib0090_wbd_to_db()
898 		wbd -= state->wbd_offset;  in dib0090_wbd_to_db()
903 static void dib0090_wbd_target(struct dib0090_state *state, u32 rf)  in dib0090_wbd_target()  argument
909 	if (state->current_band == BAND_VHF)  in dib0090_wbd_target()
912 	if (state->current_band == BAND_VHF)  in dib0090_wbd_target()
913 		offset = state->config->wbd_vhf_offset;  in dib0090_wbd_target()
914 	if (state->current_band == BAND_CBAND)  in dib0090_wbd_target()
915 		offset = state->config->wbd_cband_offset;  in dib0090_wbd_target()
918 	state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + offset);  in dib0090_wbd_target()
919 	dprintk("wbd-target: %d dB", (u32) state->wbd_target);  in dib0090_wbd_target()
926 static void dib0090_gain_apply(struct dib0090_state *state, s16 gain_delta, s16 top_delta, u8 force)  in dib0090_gain_apply()  argument
942 	if (top_delta >= ((s16) (state->rf_ramp[0] << WBD_ALPHA) - state->rf_gain_limit))	/* overflow */  in dib0090_gain_apply()
943 		state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;  in dib0090_gain_apply()
945 		state->rf_gain_limit += top_delta;  in dib0090_gain_apply()
947 	if (state->rf_gain_limit < 0)	/*underflow */  in dib0090_gain_apply()
948 		state->rf_gain_limit = 0;  in dib0090_gain_apply()
951 	gain = ((state->rf_gain_limit >> WBD_ALPHA) + state->bb_ramp[0]) << GAIN_ALPHA;  in dib0090_gain_apply()
952 	if (gain_delta >= ((s16) gain - state->current_gain))	/* overflow */  in dib0090_gain_apply()
953 		state->current_gain = gain;  in dib0090_gain_apply()
955 		state->current_gain += gain_delta;  in dib0090_gain_apply()
957 	if (state->current_gain < 0)  in dib0090_gain_apply()
958 		state->current_gain = 0;  in dib0090_gain_apply()
961 	gain = state->current_gain >> GAIN_ALPHA;  in dib0090_gain_apply()
964 	if (gain > (state->rf_gain_limit >> WBD_ALPHA)) {  in dib0090_gain_apply()
965 		rf = state->rf_gain_limit >> WBD_ALPHA;  in dib0090_gain_apply()
967 		if (bb > state->bb_ramp[0])  in dib0090_gain_apply()
968 			bb = state->bb_ramp[0];  in dib0090_gain_apply()
974 	state->gain[0] = rf;  in dib0090_gain_apply()
975 	state->gain[1] = bb;  in dib0090_gain_apply()
979 	g = state->rf_ramp + 1;	/* point on RF LNA1 max gain */  in dib0090_gain_apply()
998 			gain_reg[2] = v | state->rf_lt_def;  in dib0090_gain_apply()
1008 			g = state->bb_ramp + 1;	/* point on BB gain 1 max gain */  in dib0090_gain_apply()
1012 	gain_reg[3] |= state->bb_1_def;  in dib0090_gain_apply()
1023 		if (force || state->gain_reg[i] != v) {  in dib0090_gain_apply()
1024 			state->gain_reg[i] = v;  in dib0090_gain_apply()
1025 			dib0090_write_reg(state, gain_reg_addr[i], v);  in dib0090_gain_apply()
1030 static void dib0090_set_boost(struct dib0090_state *state, int onoff)  in dib0090_set_boost()  argument
1032 	state->bb_1_def &= 0xdfff;  in dib0090_set_boost()
1033 	state->bb_1_def |= onoff << 13;  in dib0090_set_boost()
1036 static void dib0090_set_rframp(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_rframp()  argument
1038 	state->rf_ramp = cfg;  in dib0090_set_rframp()
1041 static void dib0090_set_rframp_pwm(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_rframp_pwm()  argument
1043 	state->rf_ramp = cfg;  in dib0090_set_rframp_pwm()
1045 	dib0090_write_reg(state, 0x2a, 0xffff);  in dib0090_set_rframp_pwm()
1047 	dprintk("total RF gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x2a));  in dib0090_set_rframp_pwm()
1049 	dib0090_write_regs(state, 0x2c, cfg + 3, 6);  in dib0090_set_rframp_pwm()
1050 	dib0090_write_regs(state, 0x3e, cfg + 9, 2);  in dib0090_set_rframp_pwm()
1053 static void dib0090_set_bbramp(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_bbramp()  argument
1055 	state->bb_ramp = cfg;  in dib0090_set_bbramp()
1056 	dib0090_set_boost(state, cfg[0] > 500);	/* we want the boost if the gain is higher that 50dB */  in dib0090_set_bbramp()
1059 static void dib0090_set_bbramp_pwm(struct dib0090_state *state, const u16 * cfg)  in dib0090_set_bbramp_pwm()  argument
1061 	state->bb_ramp = cfg;  in dib0090_set_bbramp_pwm()
1063 	dib0090_set_boost(state, cfg[0] > 500);	/* we want the boost if the gain is higher that 50dB */  in dib0090_set_bbramp_pwm()
1065 	dib0090_write_reg(state, 0x33, 0xffff);  in dib0090_set_bbramp_pwm()
1066 	dprintk("total BB gain: %ddB, step: %d", (u32) cfg[0], dib0090_read_reg(state, 0x33));  in dib0090_set_bbramp_pwm()
1067 	dib0090_write_regs(state, 0x35, cfg + 3, 4);  in dib0090_set_bbramp_pwm()
1072 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_pwm_gain_reset()  local
1078 	if (state->config->use_pwm_agc) {  in dib0090_pwm_gain_reset()
1079 		if (state->current_band == BAND_CBAND) {  in dib0090_pwm_gain_reset()
1080 			if (state->identity.in_soc) {  in dib0090_pwm_gain_reset()
1082 …		if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)  in dib0090_pwm_gain_reset()
1084 …else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_2…  in dib0090_pwm_gain_reset()
1085 					if (state->config->is_dib7090e) {  in dib0090_pwm_gain_reset()
1086 						if (state->rf_ramp == NULL)  in dib0090_pwm_gain_reset()
1089 							rf_ramp = (u16 *)state->rf_ramp;  in dib0090_pwm_gain_reset()
1097 			if (state->current_band == BAND_VHF) {  in dib0090_pwm_gain_reset()
1098 				if (state->identity.in_soc) {  in dib0090_pwm_gain_reset()
1103 			} else if (state->current_band == BAND_UHF) {  in dib0090_pwm_gain_reset()
1104 				if (state->identity.in_soc) {  in dib0090_pwm_gain_reset()
1106 …		if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)  in dib0090_pwm_gain_reset()
1108 …else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_2…  in dib0090_pwm_gain_reset()
1114 			dib0090_set_rframp_pwm(state, rf_ramp);  in dib0090_pwm_gain_reset()
1115 		dib0090_set_bbramp_pwm(state, bb_ramp);  in dib0090_pwm_gain_reset()
1118 …ain = %d BAND = %s version = %d", state->rf_ramp[0], (state->current_band == BAND_CBAND) ? "CBAND"…  in dib0090_pwm_gain_reset()
1120 …if ((state->rf_ramp[0] == 0) || (state->current_band == BAND_CBAND && (state->identity.version & 0…  in dib0090_pwm_gain_reset()
1126 		dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11));  in dib0090_pwm_gain_reset()
1129 		if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)  in dib0090_pwm_gain_reset()
1130 			dib0090_write_reg(state, 0x04, 3);  in dib0090_pwm_gain_reset()
1132 			dib0090_write_reg(state, 0x04, 1);  in dib0090_pwm_gain_reset()
1133 		dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */  in dib0090_pwm_gain_reset()
1140 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_set_dc_servo()  local
1142 		dib0090_write_reg(state, 0x04, DC_servo_cutoff);  in dib0090_set_dc_servo()
1146 static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)  in dib0090_get_slow_adc_val()  argument
1148 	u16 adc_val = dib0090_read_reg(state, 0x1d);  in dib0090_get_slow_adc_val()
1149 	if (state->identity.in_soc)  in dib0090_get_slow_adc_val()
1156 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_gain_control()  local
1157 	enum frontend_tune_state *tune_state = &state->tune_state;  in dib0090_gain_control()
1165 		state->agc_freeze = 0;  in dib0090_gain_control()
1166 		dib0090_write_reg(state, 0x04, 0x0);  in dib0090_gain_control()
1169 		if (state->current_band == BAND_SBAND) {  in dib0090_gain_control()
1170 			dib0090_set_rframp(state, rf_ramp_sband);  in dib0090_gain_control()
1171 			dib0090_set_bbramp(state, bb_ramp_boost);  in dib0090_gain_control()
1175 		if (state->current_band == BAND_VHF && !state->identity.p1g) {  in dib0090_gain_control()
1176 			dib0090_set_rframp(state, rf_ramp_pwm_vhf);  in dib0090_gain_control()
1177 			dib0090_set_bbramp(state, bb_ramp_pwm_normal);  in dib0090_gain_control()
1181 		if (state->current_band == BAND_CBAND && !state->identity.p1g) {  in dib0090_gain_control()
1182 			dib0090_set_rframp(state, rf_ramp_pwm_cband);  in dib0090_gain_control()
1183 			dib0090_set_bbramp(state, bb_ramp_pwm_normal);  in dib0090_gain_control()
1186 …if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g)…  in dib0090_gain_control()
1187 			dib0090_set_rframp(state, rf_ramp_pwm_cband_7090p);  in dib0090_gain_control()
1188 			dib0090_set_bbramp(state, bb_ramp_pwm_normal_socs);  in dib0090_gain_control()
1190 			dib0090_set_rframp(state, rf_ramp_pwm_uhf);  in dib0090_gain_control()
1191 			dib0090_set_bbramp(state, bb_ramp_pwm_normal);  in dib0090_gain_control()
1194 		dib0090_write_reg(state, 0x32, 0);  in dib0090_gain_control()
1195 		dib0090_write_reg(state, 0x39, 0);  in dib0090_gain_control()
1197 		dib0090_wbd_target(state, state->current_rf);  in dib0090_gain_control()
1199 		state->rf_gain_limit = state->rf_ramp[0] << WBD_ALPHA;  in dib0090_gain_control()
1200 		state->current_gain = ((state->rf_ramp[0] + state->bb_ramp[0]) / 2) << GAIN_ALPHA;  in dib0090_gain_control()
1203 	} else if (!state->agc_freeze) {  in dib0090_gain_control()
1207 		wbd_val = dib0090_get_slow_adc_val(state);  in dib0090_gain_control()
1215 			wbd_val = dib0090_get_slow_adc_val(state);  in dib0090_gain_control()
1216 			wbd += dib0090_wbd_to_db(state, wbd_val);  in dib0090_gain_control()
1219 		wbd_error = state->wbd_target - wbd;  in dib0090_gain_control()
1222 			if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {  in dib0090_gain_control()
1225 				u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;  in dib0090_gain_control()
1226 				if (state->current_band == BAND_CBAND && ltg2) {  in dib0090_gain_control()
1228 					state->rf_lt_def &= ltg2 << 10;	/* reduce in 3 steps from 7 to 0 */  in dib0090_gain_control()
1232 				state->agc_step = 0;  in dib0090_gain_control()
1237 			adc = state->config->get_adc_power(fe);  in dib0090_gain_control()
1242 			if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)  in dib0090_gain_control()
1246 			if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&  in dib0090_gain_control()
1247 …(state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation ==…  in dib0090_gain_control()
1251 …if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cac…  in dib0090_gain_control()
1254 							((state->fe->dtv_property_cache.layer[0].modulation ==  in dib0090_gain_control()
1256 							 || (state->fe->dtv_property_cache.  in dib0090_gain_control()
1259 						((state->fe->dtv_property_cache.layer[1].segment_count >  in dib0090_gain_control()
1262 						 ((state->fe->dtv_property_cache.layer[1].modulation ==  in dib0090_gain_control()
1264 						  || (state->fe->dtv_property_cache.  in dib0090_gain_control()
1267 						((state->fe->dtv_property_cache.layer[2].segment_count >  in dib0090_gain_control()
1270 						 ((state->fe->dtv_property_cache.layer[2].modulation ==  in dib0090_gain_control()
1272 						  || (state->fe->dtv_property_cache.  in dib0090_gain_control()
1280 				if (ABS(adc_error) < 50 || state->agc_step++ > 5) {  in dib0090_gain_control()
1283 					if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) {  in dib0090_gain_control()
1284 …dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63));	/* cap value = 63 : nar…  in dib0090_gain_control()
1285 						dib0090_write_reg(state, 0x04, 0x0);  in dib0090_gain_control()
1289 						dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));  in dib0090_gain_control()
1290 …dib0090_write_reg(state, 0x04, 0x01);	/*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fa…  in dib0090_gain_control()
1305 			 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));  in dib0090_gain_control()
1310 	if (!state->agc_freeze)  in dib0090_gain_control()
1311 		dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);  in dib0090_gain_control()
1319 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_get_current_gain()  local
1321 		*rf = state->gain[0];  in dib0090_get_current_gain()
1323 		*bb = state->gain[1];  in dib0090_get_current_gain()
1325 		*rf_gain_limit = state->rf_gain_limit;  in dib0090_get_current_gain()
1327 		*rflt = (state->rf_lt_def >> 10) & 0x7;  in dib0090_get_current_gain()
1334 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_get_wbd_target()  local
1335 	u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;  in dib0090_get_wbd_target()
1336 	s32 current_temp = state->temperature;  in dib0090_get_wbd_target()
1338 	const struct dib0090_wbd_slope *wbd = state->current_wbd_table;  in dib0090_get_wbd_target()
1350 	state->wbdmux &= ~(7 << 13);  in dib0090_get_wbd_target()
1352 		state->wbdmux |= (wbd->wbd_gain << 13);  in dib0090_get_wbd_target()
1354 		state->wbdmux |= (4 << 13);  in dib0090_get_wbd_target()
1356 	dib0090_write_reg(state, 0x10, state->wbdmux);  in dib0090_get_wbd_target()
1363 	state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold);  in dib0090_get_wbd_target()
1364 	dprintk("wbd-target: %d dB", (u32) state->wbd_target);  in dib0090_get_wbd_target()
1367 	return state->wbd_offset + wbd_tcold;  in dib0090_get_wbd_target()
1373 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_get_wbd_offset()  local
1374 	return state->wbd_offset;  in dib0090_get_wbd_offset()
1380 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_set_switch()  local
1382 	dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)  in dib0090_set_switch()
1391 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_set_vga()  local
1393 	dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)  in dib0090_set_vga()
1401 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_update_rframp_7090()  local
1403 	if ((!state->identity.p1g) || (!state->identity.in_soc)  in dib0090_update_rframp_7090()
1404 			|| ((state->identity.version != SOC_7090_P1G_21R1)  in dib0090_update_rframp_7090()
1405 				&& (state->identity.version != SOC_7090_P1G_11R1))) {  in dib0090_update_rframp_7090()
1411 		state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_sensitivity;  in dib0090_update_rframp_7090()
1413 		state->rf_ramp = (const u16 *)&rf_ramp_pwm_cband_7090e_aci;  in dib0090_update_rframp_7090()
1483 static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)  in dib0090_set_default_config()  argument
1491 			dib0090_write_reg(state, r, pgm_read_word(n++));  in dib0090_set_default_config()
1505 static void dib0090_set_EFUSE(struct dib0090_state *state)  in dib0090_set_EFUSE()  argument
1511 	e2 = dib0090_read_reg(state, 0x26);  in dib0090_set_EFUSE()
1512 	e4 = dib0090_read_reg(state, 0x28);  in dib0090_set_EFUSE()
1514 	if ((state->identity.version == P1D_E_F) ||  in dib0090_set_EFUSE()
1515 			(state->identity.version == P1G) || (e2 == 0xffff)) {  in dib0090_set_EFUSE()
1517 		dib0090_write_reg(state, 0x22, 0x10);  in dib0090_set_EFUSE()
1518 		cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;  in dib0090_set_EFUSE()
1543 		dib0090_write_reg(state, 0x13, (h << 10));  in dib0090_set_EFUSE()
1545 		dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */  in dib0090_set_EFUSE()
1551 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_reset()  local
1553 	dib0090_reset_digital(fe, state->config);  in dib0090_reset()
1558 	if (!(state->identity.version & 0x1))	/* it is P1B - reset is already done */  in dib0090_reset()
1562 	if (!state->identity.in_soc) {  in dib0090_reset()
1563 		if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)  in dib0090_reset()
1564 			dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));  in dib0090_reset()
1566 			dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));  in dib0090_reset()
1569 	dib0090_set_default_config(state, dib0090_defaults);  in dib0090_reset()
1571 	if (state->identity.in_soc)  in dib0090_reset()
1572 		dib0090_write_reg(state, 0x18, 0x2910);  /* charge pump current = 0 */  in dib0090_reset()
1574 	if (state->identity.p1g)  in dib0090_reset()
1575 		dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);  in dib0090_reset()
1578 	if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc))  in dib0090_reset()
1579 		dib0090_set_EFUSE(state);  in dib0090_reset()
1582 	if (state->config->force_crystal_mode != 0)  in dib0090_reset()
1583 		dib0090_write_reg(state, 0x14,  in dib0090_reset()
1584 				state->config->force_crystal_mode & 3);  in dib0090_reset()
1585 	else if (state->config->io.clock_khz >= 24000)  in dib0090_reset()
1586 		dib0090_write_reg(state, 0x14, 1);  in dib0090_reset()
1588 		dib0090_write_reg(state, 0x14, 2);  in dib0090_reset()
1589 	dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);  in dib0090_reset()
1591 …state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL;	/* enable iq-offset-calibration and wbd-calibratio…  in dib0090_reset()
1598 static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_state *tune_state)  in dib0090_get_offset()  argument
1605 		dib0090_write_reg(state, 0x1f, 0x7);  in dib0090_get_offset()
1610 		state->adc_diff = dib0090_read_reg(state, 0x1d);  in dib0090_get_offset()
1613 		dib0090_write_reg(state, 0x1f, 0x4);  in dib0090_get_offset()
1618 		state->adc_diff -= dib0090_read_reg(state, 0x1d);  in dib0090_get_offset()
1659 static void dib0090_set_trim(struct dib0090_state *state)  in dib0090_set_trim()  argument
1663 	if (state->dc->addr == 0x07)  in dib0090_set_trim()
1664 		val = &state->bb7;  in dib0090_set_trim()
1666 		val = &state->bb6;  in dib0090_set_trim()
1668 	*val &= ~(0x1f << state->dc->offset);  in dib0090_set_trim()
1669 	*val |= state->step << state->dc->offset;  in dib0090_set_trim()
1671 	dib0090_write_reg(state, state->dc->addr, *val);  in dib0090_set_trim()
1674 static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tun…  in dib0090_dc_offset_calibration()  argument
1684 		state->bb6 = 0;  in dib0090_dc_offset_calibration()
1685 		state->bb7 = 0x040d;  in dib0090_dc_offset_calibration()
1688 		reg = dib0090_read_reg(state, 0x24) & 0x0ffb;	/* shutdown lna and lo */  in dib0090_dc_offset_calibration()
1689 		dib0090_write_reg(state, 0x24, reg);  in dib0090_dc_offset_calibration()
1691 		state->wbdmux = dib0090_read_reg(state, 0x10);  in dib0090_dc_offset_calibration()
1692 		dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);  in dib0090_dc_offset_calibration()
1693 		dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));  in dib0090_dc_offset_calibration()
1695 		state->dc = dc_table;  in dib0090_dc_offset_calibration()
1697 		if (state->identity.p1g)  in dib0090_dc_offset_calibration()
1698 			state->dc = dc_p1g_table;  in dib0090_dc_offset_calibration()
1704 		dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");  in dib0090_dc_offset_calibration()
1705 		dib0090_write_reg(state, 0x01, state->dc->bb1);  in dib0090_dc_offset_calibration()
1706 		dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));  in dib0090_dc_offset_calibration()
1708 		state->step = 0;  in dib0090_dc_offset_calibration()
1709 		state->min_adc_diff = 1023;  in dib0090_dc_offset_calibration()
1715 		dib0090_set_trim(state);  in dib0090_dc_offset_calibration()
1722 		ret = dib0090_get_offset(state, tune_state);  in dib0090_dc_offset_calibration()
1726 		dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);  in dib0090_dc_offset_calibration()
1727 		if (state->step == 0 && state->adc_diff < 0) {  in dib0090_dc_offset_calibration()
1728 			state->min_adc_diff = -1023;  in dib0090_dc_offset_calibration()
1732 …("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state…  in dib0090_dc_offset_calibration()
1735 		if (state->step == 0) {  in dib0090_dc_offset_calibration()
1736 			if (state->dc->pga && state->adc_diff < 0)  in dib0090_dc_offset_calibration()
1737 				state->step = 0x10;  in dib0090_dc_offset_calibration()
1738 			if (state->dc->pga == 0 && state->adc_diff > 0)  in dib0090_dc_offset_calibration()
1739 				state->step = 0x10;  in dib0090_dc_offset_calibration()
1743 		if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {  in dib0090_dc_offset_calibration()
1745 			state->step++;  in dib0090_dc_offset_calibration()
1746 			state->min_adc_diff = state->adc_diff;  in dib0090_dc_offset_calibration()
1750 			if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) {  in dib0090_dc_offset_calibration()
1751 … adc_diff N = %d  > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_d…  in dib0090_dc_offset_calibration()
1752 				state->step--;  in dib0090_dc_offset_calibration()
1755 			dib0090_set_trim(state);  in dib0090_dc_offset_calibration()
1756 …ntk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->…  in dib0090_dc_offset_calibration()
1758 			state->dc++;  in dib0090_dc_offset_calibration()
1759 			if (state->dc->addr == 0)	/* done */  in dib0090_dc_offset_calibration()
1768 		dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);  in dib0090_dc_offset_calibration()
1769 		dib0090_write_reg(state, 0x1f, 0x7);  in dib0090_dc_offset_calibration()
1771 		state->calibrate &= ~DC_CAL;  in dib0090_dc_offset_calibration()
1778 static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_stat…  in dib0090_wbd_calibration()  argument
1781 	const struct dib0090_wbd_slope *wbd = state->current_wbd_table;  in dib0090_wbd_calibration()
1785 		while (state->current_rf / 1000 > wbd->max_freq)  in dib0090_wbd_calibration()
1792 			if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))  in dib0090_wbd_calibration()
1797 		if (wbd_gain == state->wbd_calibration_gain) {	/* the WBD calibration has already been done */  in dib0090_wbd_calibration()
1799 			state->calibrate &= ~WBD_CAL;  in dib0090_wbd_calibration()
1803 		dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));  in dib0090_wbd_calibration()
1805 		dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));  in dib0090_wbd_calibration()
1807 		state->wbd_calibration_gain = wbd_gain;  in dib0090_wbd_calibration()
1811 		state->wbd_offset = dib0090_get_slow_adc_val(state);  in dib0090_wbd_calibration()
1812 		dprintk("WBD calibration offset = %d", state->wbd_offset);  in dib0090_wbd_calibration()
1814 		state->calibrate &= ~WBD_CAL;  in dib0090_wbd_calibration()
1823 static void dib0090_set_bandwidth(struct dib0090_state *state)  in dib0090_set_bandwidth()  argument
1827 	if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 5000)  in dib0090_set_bandwidth()
1829 	else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 6000)  in dib0090_set_bandwidth()
1831 	else if (state->fe->dtv_property_cache.bandwidth_hz / 1000 <= 7000)  in dib0090_set_bandwidth()
1836 	state->bb_1_def &= 0x3fff;  in dib0090_set_bandwidth()
1837 	state->bb_1_def |= tmp;  in dib0090_set_bandwidth()
1839 	dib0090_write_reg(state, 0x01, state->bb_1_def);	/* be sure that we have the right bb-filter */  in dib0090_set_bandwidth()
1841 …dib0090_write_reg(state, 0x03, 0x6008);	/* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filte…  in dib0090_set_bandwidth()
1842 …dib0090_write_reg(state, 0x04, 0x1);	/* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fa…  in dib0090_set_bandwidth()
1843 	if (state->identity.in_soc) {  in dib0090_set_bandwidth()
1844 …dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; n…  in dib0090_set_bandwidth()
1846 		dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f));	/* 22 = cap_value */  in dib0090_set_bandwidth()
1847 …dib0090_write_reg(state, 0x05, 0xabcd);	/* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias…  in dib0090_set_bandwidth()
2045 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_update_tuning_table_7090()  local
2054 	if ((!state->identity.p1g) || (!state->identity.in_soc)  in dib0090_update_tuning_table_7090()
2055 			|| ((state->identity.version != SOC_7090_P1G_21R1)  in dib0090_update_tuning_table_7090()
2056 				&& (state->identity.version != SOC_7090_P1G_11R1))) {  in dib0090_update_tuning_table_7090()
2066 	while (state->rf_request > tune->max_freq)  in dib0090_update_tuning_table_7090()
2069 	dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)  in dib0090_update_tuning_table_7090()
2071 	dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)  in dib0090_update_tuning_table_7090()
2077 static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)  in dib0090_captrim_search()  argument
2087 	if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)  in dib0090_captrim_search()
2092 		dib0090_write_reg(state, 0x10, 0x2B1);  in dib0090_captrim_search()
2093 		dib0090_write_reg(state, 0x1e, 0x0032);  in dib0090_captrim_search()
2095 		if (!state->tuner_is_tuned) {  in dib0090_captrim_search()
2097 			if (!state->identity.p1g || force_soft_search)  in dib0090_captrim_search()
2098 				state->step = state->captrim = state->fcaptrim = 64;  in dib0090_captrim_search()
2100 			state->current_rf = state->rf_request;  in dib0090_captrim_search()
2102 			if (!state->identity.p1g || force_soft_search) {  in dib0090_captrim_search()
2104 				state->step = 4;  in dib0090_captrim_search()
2105 				state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;  in dib0090_captrim_search()
2108 		state->adc_diff = 3000;  in dib0090_captrim_search()
2112 		if (state->identity.p1g && !force_soft_search) {  in dib0090_captrim_search()
2115 			dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);  in dib0090_captrim_search()
2116 			dib0090_read_reg(state, 0x40);  in dib0090_captrim_search()
2119 			state->step /= 2;  in dib0090_captrim_search()
2120 			dib0090_write_reg(state, 0x18, lo4 | state->captrim);  in dib0090_captrim_search()
2122 			if (state->identity.in_soc)  in dib0090_captrim_search()
2128 		if (state->identity.p1g && !force_soft_search) {  in dib0090_captrim_search()
2129 			dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);  in dib0090_captrim_search()
2130 			dib0090_read_reg(state, 0x40);  in dib0090_captrim_search()
2132 			state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;  in dib0090_captrim_search()
2133 			dprintk("***Final Captrim= 0x%x", state->fcaptrim);  in dib0090_captrim_search()
2138 			adc = dib0090_get_slow_adc_val(state);  in dib0090_captrim_search()
2139 …dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) …  in dib0090_captrim_search()
2141 …if (state->rest == 0 || state->identity.in_soc) {	/* Just for 8090P SOCS where auto captrim HW bug…  in dib0090_captrim_search()
2154 			if (adc < state->adc_diff) {  in dib0090_captrim_search()
2155 …dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->ad…  in dib0090_captrim_search()
2156 				state->adc_diff = adc;  in dib0090_captrim_search()
2157 				state->fcaptrim = state->captrim;  in dib0090_captrim_search()
2160 			state->captrim += step_sign * state->step;  in dib0090_captrim_search()
2161 			if (state->step >= 1)  in dib0090_captrim_search()
2170 		dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);  in dib0090_captrim_search()
2175 		state->calibrate &= ~CAPTRIM_CAL;  in dib0090_captrim_search()
2182 static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_stat…  in dib0090_get_temperature()  argument
2189 		state->wbdmux = dib0090_read_reg(state, 0x10);  in dib0090_get_temperature()
2190 		dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));  in dib0090_get_temperature()
2192 		state->bias = dib0090_read_reg(state, 0x13);  in dib0090_get_temperature()
2193 		dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));  in dib0090_get_temperature()
2200 		state->adc_diff = dib0090_get_slow_adc_val(state);  in dib0090_get_temperature()
2201 		dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));  in dib0090_get_temperature()
2206 		val = dib0090_get_slow_adc_val(state);  in dib0090_get_temperature()
2207 		state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55;  in dib0090_get_temperature()
2209 		dprintk("temperature: %d C", state->temperature - 30);  in dib0090_get_temperature()
2215 		dib0090_write_reg(state, 0x13, state->bias);  in dib0090_get_temperature()
2216 		dib0090_write_reg(state, 0x10, state->wbdmux);	/* write back original WBDMUX */  in dib0090_get_temperature()
2219 		state->calibrate &= ~TEMP_CAL;  in dib0090_get_temperature()
2220 		if (state->config->analog_output == 0)  in dib0090_get_temperature()
2221 			dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));  in dib0090_get_temperature()
2235 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_tune()  local
2236 	const struct dib0090_tuning *tune = state->current_tune_table_index;  in dib0090_tune()
2237 	const struct dib0090_pll *pll = state->current_pll_table_index;  in dib0090_tune()
2238 	enum frontend_tune_state *tune_state = &state->tune_state;  in dib0090_tune()
2253 		if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))  in dib0090_tune()
2254 			dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));  in dib0090_tune()
2257 			if (state->config->analog_output == 0)  in dib0090_tune()
2258 				dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));  in dib0090_tune()
2261 	if (state->calibrate & DC_CAL)  in dib0090_tune()
2262 		return dib0090_dc_offset_calibration(state, tune_state);  in dib0090_tune()
2263 	else if (state->calibrate & WBD_CAL) {  in dib0090_tune()
2264 		if (state->current_rf == 0)  in dib0090_tune()
2265 			state->current_rf = state->fe->dtv_property_cache.frequency / 1000;  in dib0090_tune()
2266 		return dib0090_wbd_calibration(state, tune_state);  in dib0090_tune()
2267 	} else if (state->calibrate & TEMP_CAL)  in dib0090_tune()
2268 		return dib0090_get_temperature(state, tune_state);  in dib0090_tune()
2269 	else if (state->calibrate & CAPTRIM_CAL)  in dib0090_tune()
2270 		return dib0090_captrim_search(state, tune_state);  in dib0090_tune()
2274 		if (state->config->use_pwm_agc && state->identity.in_soc) {  in dib0090_tune()
2275 			tmp = dib0090_read_reg(state, 0x39);  in dib0090_tune()
2277 				dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));  in dib0090_tune()
2280 		state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);  in dib0090_tune()
2281 		state->rf_request =  in dib0090_tune()
2282 			state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==  in dib0090_tune()
2283 					BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->  in dib0090_tune()
2287 …if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.i…  in dib0090_tune()
2288 					&& state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {  in dib0090_tune()
2289 			const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;  in dib0090_tune()
2295 					if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))  in dib0090_tune()
2296 								&& (state->rf_request < (LUT_offset->RF_freq + margin_khz)))  in dib0090_tune()
2297 							&& LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {  in dib0090_tune()
2298 						state->rf_request += LUT_offset->offset_khz;  in dib0090_tune()
2307 				state->rf_request += 400;  in dib0090_tune()
2309 …if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_…  in dib0090_tune()
2310 			state->tuner_is_tuned = 0;  in dib0090_tune()
2311 			state->current_rf = 0;  in dib0090_tune()
2312 			state->current_standard = 0;  in dib0090_tune()
2315 			if (state->identity.p1g)  in dib0090_tune()
2318 			tmp = (state->identity.version >> 5) & 0x7;  in dib0090_tune()
2320 			if (state->identity.in_soc) {  in dib0090_tune()
2321 				if (state->config->force_cband_input) {	/* Use the CBAND input for all band */  in dib0090_tune()
2322 …if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAN…  in dib0090_tune()
2323 							|| state->current_band & BAND_UHF) {  in dib0090_tune()
2324 						state->current_band = BAND_CBAND;  in dib0090_tune()
2325 						if (state->config->is_dib7090e)  in dib0090_tune()
2331 …if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAN…  in dib0090_tune()
2332 						state->current_band = BAND_CBAND;  in dib0090_tune()
2333 						if (state->config->is_dib7090e)  in dib0090_tune()
2342 …if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == …  in dib0090_tune()
2343 					state->current_band = BAND_CBAND;	/* Force CBAND */  in dib0090_tune()
2346 					if (state->identity.p1g)  in dib0090_tune()
2352 			if (state->identity.p1g)  in dib0090_tune()
2356 			while (state->rf_request > tune->max_freq)  in dib0090_tune()
2358 			while (state->rf_request > pll->max_freq)  in dib0090_tune()
2361 			state->current_tune_table_index = tune;  in dib0090_tune()
2362 			state->current_pll_table_index = pll;  in dib0090_tune()
2364 			dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));  in dib0090_tune()
2366 			VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;  in dib0090_tune()
2368 			FREF = state->config->io.clock_khz;  in dib0090_tune()
2369 			if (state->config->fref_clock_ratio != 0)  in dib0090_tune()
2370 				FREF /= state->config->fref_clock_ratio;  in dib0090_tune()
2385 			state->rest = Rest;  in dib0090_tune()
2399 				else if (state->config->analog_output)  in dib0090_tune()
2405 			if (state->identity.p1g) {	/* Bias is done automatically in P1G */  in dib0090_tune()
2406 				if (state->identity.in_soc) {  in dib0090_tune()
2407 					if (state->identity.version == SOC_8090_P1G_11R1)  in dib0090_tune()
2417 			if (!state->config->io.pll_int_loop_filt) {  in dib0090_tune()
2418 				if (state->identity.in_soc)  in dib0090_tune()
2420 				else if (state->identity.p1g || (Rest == 0))  in dib0090_tune()
2425 				lo6 = (state->config->io.pll_int_loop_filt << 3);  in dib0090_tune()
2430 				if (state->config->analog_output)  in dib0090_tune()
2433 					if (state->identity.in_soc)  in dib0090_tune()
2440 			dib0090_write_reg(state, 0x15, (u16) FBDiv);  in dib0090_tune()
2441 			if (state->config->fref_clock_ratio != 0)  in dib0090_tune()
2442 				dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);  in dib0090_tune()
2444 				dib0090_write_reg(state, 0x16, (Den << 8) | 1);  in dib0090_tune()
2445 			dib0090_write_reg(state, 0x17, (u16) Rest);  in dib0090_tune()
2446 			dib0090_write_reg(state, 0x19, lo5);  in dib0090_tune()
2447 			dib0090_write_reg(state, 0x1c, lo6);  in dib0090_tune()
2450 			if (state->config->analog_output)  in dib0090_tune()
2453 			dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);  in dib0090_tune()
2457 		state->current_rf = state->rf_request;  in dib0090_tune()
2458 		state->current_standard = state->fe->dtv_property_cache.delivery_system;  in dib0090_tune()
2461 		state->calibrate = CAPTRIM_CAL;	/* captrim serach now */  in dib0090_tune()
2465 		const struct dib0090_wbd_slope *wbd = state->current_wbd_table;  in dib0090_tune()
2467 		while (state->current_rf / 1000 > wbd->max_freq)  in dib0090_tune()
2470 		dib0090_write_reg(state, 0x1e, 0x07ff);  in dib0090_tune()
2471 		dprintk("Final Captrim: %d", (u32) state->fcaptrim);  in dib0090_tune()
2474 …n kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) …  in dib0090_tune()
2475 		dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);  in dib0090_tune()
2476 …dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, …  in dib0090_tune()
2477 …ntk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state…  in dib0090_tune()
2478 			(u32) dib0090_read_reg(state, 0x1c) & 0x3);  in dib0090_tune()
2487 		state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));  in dib0090_tune()
2488 		dib0090_write_reg(state, 0x10, state->wbdmux);  in dib0090_tune()
2490 		if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {  in dib0090_tune()
2492 			dib0090_write_reg(state, 0x09, tune->lna_bias);  in dib0090_tune()
2493 			dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));  in dib0090_tune()
2495 			dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);  in dib0090_tune()
2497 		dib0090_write_reg(state, 0x0c, tune->v2i);  in dib0090_tune()
2498 		dib0090_write_reg(state, 0x0d, tune->mix);  in dib0090_tune()
2499 		dib0090_write_reg(state, 0x0e, tune->load);  in dib0090_tune()
2504 		state->rf_lt_def = 0x7c00;  in dib0090_tune()
2506 		dib0090_set_bandwidth(state);  in dib0090_tune()
2507 		state->tuner_is_tuned = 1;  in dib0090_tune()
2509 		state->calibrate |= WBD_CAL;  in dib0090_tune()
2510 		state->calibrate |= TEMP_CAL;  in dib0090_tune()
2526 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_get_tune_state()  local
2528 	return state->tune_state;  in dib0090_get_tune_state()
2535 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_set_tune_state()  local
2537 	state->tune_state = tune_state;  in dib0090_set_tune_state()
2545 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_get_frequency()  local
2547 	*frequency = 1000 * state->current_rf;  in dib0090_get_frequency()
2553 	struct dib0090_state *state = fe->tuner_priv;  in dib0090_set_params()  local
2556 	state->tune_state = CT_TUNER_START;  in dib0090_set_params()
2573 	} while (state->tune_state != CT_TUNER_STOP);  in dib0090_set_params()