Lines Matching refs:state
63 static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, in mt312_read() argument
70 msg[0].addr = state->config->demod_address; in mt312_read()
74 msg[1].addr = state->config->demod_address; in mt312_read()
79 ret = i2c_transfer(state->i2c, msg, 2); in mt312_read()
97 static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, in mt312_write() argument
121 msg.addr = state->config->demod_address; in mt312_write()
126 ret = i2c_transfer(state->i2c, &msg, 1); in mt312_write()
136 static inline int mt312_readreg(struct mt312_state *state, in mt312_readreg() argument
139 return mt312_read(state, reg, val, 1); in mt312_readreg()
142 static inline int mt312_writereg(struct mt312_state *state, in mt312_writereg() argument
145 return mt312_write(state, reg, &val, 1); in mt312_writereg()
153 static int mt312_reset(struct mt312_state *state, const u8 full) in mt312_reset() argument
155 return mt312_writereg(state, RESET, full ? 0x80 : 0x40); in mt312_reset()
158 static int mt312_get_inversion(struct mt312_state *state, in mt312_get_inversion() argument
164 ret = mt312_readreg(state, VIT_MODE, &vit_mode); in mt312_get_inversion()
174 static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr) in mt312_get_symbol_rate() argument
183 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h); in mt312_get_symbol_rate()
189 ret = mt312_writereg(state, MON_CTRL, 0x03); in mt312_get_symbol_rate()
193 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
202 ret = mt312_writereg(state, MON_CTRL, 0x05); in mt312_get_symbol_rate()
206 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
212 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf)); in mt312_get_symbol_rate()
221 (((state->xtal * 8192) / (sym_rat_op + 8192)) * in mt312_get_symbol_rate()
228 static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr) in mt312_get_code_rate() argument
237 ret = mt312_readreg(state, FEC_STATUS, &fec_status); in mt312_get_code_rate()
248 struct mt312_state *state = fe->demodulator_priv; in mt312_initfe() local
253 ret = mt312_writereg(state, CONFIG, in mt312_initfe()
254 (state->freq_mult == 6 ? 0x88 : 0x8c)); in mt312_initfe()
262 ret = mt312_reset(state, 1); in mt312_initfe()
272 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def)); in mt312_initfe()
277 switch (state->id) { in mt312_initfe()
280 ret = mt312_writereg(state, GPP_CTRL, 0x80); in mt312_initfe()
287 ret = mt312_write(state, HW_CTRL, buf, 2); in mt312_initfe()
292 ret = mt312_writereg(state, HW_CTRL, 0x00); in mt312_initfe()
296 ret = mt312_writereg(state, MPEG_CTRL, 0x00); in mt312_initfe()
304 buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000); in mt312_initfe()
307 buf[1] = mt312_div(state->xtal, 22000 * 4); in mt312_initfe()
309 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf)); in mt312_initfe()
313 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32); in mt312_initfe()
318 switch (state->id) { in mt312_initfe()
327 ret = mt312_writereg(state, OP_CTRL, buf[0]); in mt312_initfe()
335 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf)); in mt312_initfe()
339 ret = mt312_writereg(state, CS_SW_LIM, 0x69); in mt312_initfe()
349 struct mt312_state *state = fe->demodulator_priv; in mt312_send_master_cmd() local
356 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_master_cmd()
360 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len); in mt312_send_master_cmd()
364 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_master_cmd()
375 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40)); in mt312_send_master_cmd()
385 struct mt312_state *state = fe->demodulator_priv; in mt312_send_burst() local
394 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_send_burst()
398 ret = mt312_writereg(state, DISEQC_MODE, in mt312_send_burst()
408 struct mt312_state *state = fe->demodulator_priv; in mt312_set_tone() local
417 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode); in mt312_set_tone()
421 ret = mt312_writereg(state, DISEQC_MODE, in mt312_set_tone()
431 struct mt312_state *state = fe->demodulator_priv; in mt312_set_voltage() local
439 if (state->config->voltage_inverted) in mt312_set_voltage()
442 return mt312_writereg(state, DISEQC_MODE, val); in mt312_set_voltage()
447 struct mt312_state *state = fe->demodulator_priv; in mt312_read_status() local
453 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status)); in mt312_read_status()
476 struct mt312_state *state = fe->demodulator_priv; in mt312_read_ber() local
480 ret = mt312_read(state, RS_BERCNT_H, buf, 3); in mt312_read_ber()
492 struct mt312_state *state = fe->demodulator_priv; in mt312_read_signal_strength() local
498 ret = mt312_read(state, AGC_H, buf, sizeof(buf)); in mt312_read_signal_strength()
514 struct mt312_state *state = fe->demodulator_priv; in mt312_read_snr() local
518 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf)); in mt312_read_snr()
529 struct mt312_state *state = fe->demodulator_priv; in mt312_read_ucblocks() local
533 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf)); in mt312_read_ucblocks()
545 struct mt312_state *state = fe->demodulator_priv; in mt312_set_frontend() local
576 switch (state->id) { in mt312_set_frontend()
582 ret = mt312_readreg(state, CONFIG, &config_val); in mt312_set_frontend()
587 if (state->freq_mult == 6) { in mt312_set_frontend()
589 state->freq_mult = 9; in mt312_set_frontend()
595 if (state->freq_mult == 9) { in mt312_set_frontend()
597 state->freq_mult = 6; in mt312_set_frontend()
638 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf)); in mt312_set_frontend()
642 mt312_reset(state, 0); in mt312_set_frontend()
650 struct mt312_state *state = fe->demodulator_priv; in mt312_get_frontend() local
653 ret = mt312_get_inversion(state, &p->inversion); in mt312_get_frontend()
657 ret = mt312_get_symbol_rate(state, &p->symbol_rate); in mt312_get_frontend()
661 ret = mt312_get_code_rate(state, &p->fec_inner); in mt312_get_frontend()
670 struct mt312_state *state = fe->demodulator_priv; in mt312_i2c_gate_ctrl() local
675 switch (state->id) { in mt312_i2c_gate_ctrl()
677 ret = mt312_readreg(state, GPP_CTRL, &val); in mt312_i2c_gate_ctrl()
691 ret = mt312_writereg(state, GPP_CTRL, val); in mt312_i2c_gate_ctrl()
699 struct mt312_state *state = fe->demodulator_priv; in mt312_sleep() local
704 ret = mt312_reset(state, 1); in mt312_sleep()
708 if (state->id == ID_ZL10313) { in mt312_sleep()
710 ret = mt312_writereg(state, GPP_CTRL, 0x00); in mt312_sleep()
715 ret = mt312_writereg(state, HW_CTRL, 0x0d); in mt312_sleep()
720 ret = mt312_readreg(state, CONFIG, &config); in mt312_sleep()
725 ret = mt312_writereg(state, CONFIG, config & 0x7f); in mt312_sleep()
743 struct mt312_state *state = fe->demodulator_priv; in mt312_release() local
744 kfree(state); in mt312_release()
790 struct mt312_state *state = NULL; in mt312_attach() local
793 state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL); in mt312_attach()
794 if (state == NULL) in mt312_attach()
798 state->config = config; in mt312_attach()
799 state->i2c = i2c; in mt312_attach()
802 if (mt312_readreg(state, ID, &state->id) < 0) in mt312_attach()
806 memcpy(&state->frontend.ops, &mt312_ops, in mt312_attach()
808 state->frontend.demodulator_priv = state; in mt312_attach()
810 switch (state->id) { in mt312_attach()
812 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S"); in mt312_attach()
813 state->xtal = MT312_PLL_CLK; in mt312_attach()
814 state->freq_mult = 9; in mt312_attach()
817 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S"); in mt312_attach()
818 state->xtal = MT312_PLL_CLK; in mt312_attach()
819 state->freq_mult = 6; in mt312_attach()
822 strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S"); in mt312_attach()
823 state->xtal = MT312_PLL_CLK_10_111; in mt312_attach()
824 state->freq_mult = 9; in mt312_attach()
832 return &state->frontend; in mt312_attach()
835 kfree(state); in mt312_attach()