1/* 2 * Support for LGDT3306A - 8VSB/QAM-B 3 * 4 * Copyright (C) 2013 Fred Richter <frichter@hauppauge.com> 5 * - driver structure based on lgdt3305.[ch] by Michael Krufky 6 * - code based on LG3306_V0.35 API by LG Electronics Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21#include <asm/div64.h> 22#include <linux/dvb/frontend.h> 23#include "dvb_math.h" 24#include "lgdt3306a.h" 25 26 27static int debug; 28module_param(debug, int, 0644); 29MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))"); 30 31#define DBG_INFO 1 32#define DBG_REG 2 33#define DBG_DUMP 4 /* FGR - comment out to remove dump code */ 34 35#define lg_debug(fmt, arg...) \ 36 printk(KERN_DEBUG pr_fmt(fmt), ## arg) 37 38#define dbg_info(fmt, arg...) \ 39 do { \ 40 if (debug & DBG_INFO) \ 41 lg_debug(fmt, ## arg); \ 42 } while (0) 43 44#define dbg_reg(fmt, arg...) \ 45 do { \ 46 if (debug & DBG_REG) \ 47 lg_debug(fmt, ## arg); \ 48 } while (0) 49 50#define lg_chkerr(ret) \ 51({ \ 52 int __ret; \ 53 __ret = (ret < 0); \ 54 if (__ret) \ 55 pr_err("error %d on line %d\n", ret, __LINE__); \ 56 __ret; \ 57}) 58 59struct lgdt3306a_state { 60 struct i2c_adapter *i2c_adap; 61 const struct lgdt3306a_config *cfg; 62 63 struct dvb_frontend frontend; 64 65 fe_modulation_t current_modulation; 66 u32 current_frequency; 67 u32 snr; 68}; 69 70/* 71 * LG3306A Register Usage 72 * (LG does not really name the registers, so this code does not either) 73 * 74 * 0000 -> 00FF Common control and status 75 * 1000 -> 10FF Synchronizer control and status 76 * 1F00 -> 1FFF Smart Antenna control and status 77 * 2100 -> 21FF VSB Equalizer control and status 78 * 2800 -> 28FF QAM Equalizer control and status 79 * 3000 -> 30FF FEC control and status 80 */ 81 82enum lgdt3306a_lock_status { 83 LG3306_UNLOCK = 0x00, 84 LG3306_LOCK = 0x01, 85 LG3306_UNKNOWN_LOCK = 0xff 86}; 87 88enum lgdt3306a_neverlock_status { 89 LG3306_NL_INIT = 0x00, 90 LG3306_NL_PROCESS = 0x01, 91 LG3306_NL_LOCK = 0x02, 92 LG3306_NL_FAIL = 0x03, 93 LG3306_NL_UNKNOWN = 0xff 94}; 95 96enum lgdt3306a_modulation { 97 LG3306_VSB = 0x00, 98 LG3306_QAM64 = 0x01, 99 LG3306_QAM256 = 0x02, 100 LG3306_UNKNOWN_MODE = 0xff 101}; 102 103enum lgdt3306a_lock_check { 104 LG3306_SYNC_LOCK, 105 LG3306_FEC_LOCK, 106 LG3306_TR_LOCK, 107 LG3306_AGC_LOCK, 108}; 109 110 111#ifdef DBG_DUMP 112static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state); 113static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state); 114#endif 115 116 117static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) 118{ 119 int ret; 120 u8 buf[] = { reg >> 8, reg & 0xff, val }; 121 struct i2c_msg msg = { 122 .addr = state->cfg->i2c_addr, .flags = 0, 123 .buf = buf, .len = 3, 124 }; 125 126 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); 127 128 ret = i2c_transfer(state->i2c_adap, &msg, 1); 129 130 if (ret != 1) { 131 pr_err("error (addr %02x %02x <- %02x, err = %i)\n", 132 msg.buf[0], msg.buf[1], msg.buf[2], ret); 133 if (ret < 0) 134 return ret; 135 else 136 return -EREMOTEIO; 137 } 138 return 0; 139} 140 141static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) 142{ 143 int ret; 144 u8 reg_buf[] = { reg >> 8, reg & 0xff }; 145 struct i2c_msg msg[] = { 146 { .addr = state->cfg->i2c_addr, 147 .flags = 0, .buf = reg_buf, .len = 2 }, 148 { .addr = state->cfg->i2c_addr, 149 .flags = I2C_M_RD, .buf = val, .len = 1 }, 150 }; 151 152 ret = i2c_transfer(state->i2c_adap, msg, 2); 153 154 if (ret != 2) { 155 pr_err("error (addr %02x reg %04x error (ret == %i)\n", 156 state->cfg->i2c_addr, reg, ret); 157 if (ret < 0) 158 return ret; 159 else 160 return -EREMOTEIO; 161 } 162 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); 163 164 return 0; 165} 166 167#define read_reg(state, reg) \ 168({ \ 169 u8 __val; \ 170 int ret = lgdt3306a_read_reg(state, reg, &__val); \ 171 if (lg_chkerr(ret)) \ 172 __val = 0; \ 173 __val; \ 174}) 175 176static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state, 177 u16 reg, int bit, int onoff) 178{ 179 u8 val; 180 int ret; 181 182 dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); 183 184 ret = lgdt3306a_read_reg(state, reg, &val); 185 if (lg_chkerr(ret)) 186 goto fail; 187 188 val &= ~(1 << bit); 189 val |= (onoff & 1) << bit; 190 191 ret = lgdt3306a_write_reg(state, reg, val); 192 lg_chkerr(ret); 193fail: 194 return ret; 195} 196 197/* ------------------------------------------------------------------------ */ 198 199static int lgdt3306a_soft_reset(struct lgdt3306a_state *state) 200{ 201 int ret; 202 203 dbg_info("\n"); 204 205 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); 206 if (lg_chkerr(ret)) 207 goto fail; 208 209 msleep(20); 210 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); 211 lg_chkerr(ret); 212 213fail: 214 return ret; 215} 216 217static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state, 218 enum lgdt3306a_mpeg_mode mode) 219{ 220 u8 val; 221 int ret; 222 223 dbg_info("(%d)\n", mode); 224 /* transport packet format - TPSENB=0x80 */ 225 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, 226 mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0); 227 if (lg_chkerr(ret)) 228 goto fail; 229 230 /* 231 * start of packet signal duration 232 * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration 233 */ 234 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); 235 if (lg_chkerr(ret)) 236 goto fail; 237 238 ret = lgdt3306a_read_reg(state, 0x0070, &val); 239 if (lg_chkerr(ret)) 240 goto fail; 241 242 val |= 0x10; /* TPCLKSUPB=0x10 */ 243 244 if (mode == LGDT3306A_MPEG_PARALLEL) 245 val &= ~0x10; 246 247 ret = lgdt3306a_write_reg(state, 0x0070, val); 248 lg_chkerr(ret); 249 250fail: 251 return ret; 252} 253 254static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state, 255 enum lgdt3306a_tp_clock_edge edge, 256 enum lgdt3306a_tp_valid_polarity valid) 257{ 258 u8 val; 259 int ret; 260 261 dbg_info("edge=%d, valid=%d\n", edge, valid); 262 263 ret = lgdt3306a_read_reg(state, 0x0070, &val); 264 if (lg_chkerr(ret)) 265 goto fail; 266 267 val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */ 268 269 if (edge == LGDT3306A_TPCLK_RISING_EDGE) 270 val |= 0x04; 271 if (valid == LGDT3306A_TP_VALID_HIGH) 272 val |= 0x02; 273 274 ret = lgdt3306a_write_reg(state, 0x0070, val); 275 lg_chkerr(ret); 276 277fail: 278 return ret; 279} 280 281static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state, 282 int mode) 283{ 284 u8 val; 285 int ret; 286 287 dbg_info("(%d)\n", mode); 288 289 if (mode) { 290 ret = lgdt3306a_read_reg(state, 0x0070, &val); 291 if (lg_chkerr(ret)) 292 goto fail; 293 /* 294 * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, 295 * TPDATAOUTEN=0x08 296 */ 297 val &= ~0xa8; 298 ret = lgdt3306a_write_reg(state, 0x0070, val); 299 if (lg_chkerr(ret)) 300 goto fail; 301 302 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */ 303 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); 304 if (lg_chkerr(ret)) 305 goto fail; 306 307 } else { 308 /* enable IFAGC pin */ 309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); 310 if (lg_chkerr(ret)) 311 goto fail; 312 313 ret = lgdt3306a_read_reg(state, 0x0070, &val); 314 if (lg_chkerr(ret)) 315 goto fail; 316 317 val |= 0xa8; /* enable bus */ 318 ret = lgdt3306a_write_reg(state, 0x0070, val); 319 if (lg_chkerr(ret)) 320 goto fail; 321 } 322 323fail: 324 return ret; 325} 326 327static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire) 328{ 329 struct lgdt3306a_state *state = fe->demodulator_priv; 330 331 dbg_info("acquire=%d\n", acquire); 332 333 return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1); 334 335} 336 337static int lgdt3306a_power(struct lgdt3306a_state *state, 338 int mode) 339{ 340 int ret; 341 342 dbg_info("(%d)\n", mode); 343 344 if (mode == 0) { 345 /* into reset */ 346 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); 347 if (lg_chkerr(ret)) 348 goto fail; 349 350 /* power down */ 351 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); 352 if (lg_chkerr(ret)) 353 goto fail; 354 355 } else { 356 /* out of reset */ 357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); 358 if (lg_chkerr(ret)) 359 goto fail; 360 361 /* power up */ 362 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); 363 if (lg_chkerr(ret)) 364 goto fail; 365 } 366 367#ifdef DBG_DUMP 368 lgdt3306a_DumpAllRegs(state); 369#endif 370fail: 371 return ret; 372} 373 374 375static int lgdt3306a_set_vsb(struct lgdt3306a_state *state) 376{ 377 u8 val; 378 int ret; 379 380 dbg_info("\n"); 381 382 /* 0. Spectrum inversion detection manual; spectrum inverted */ 383 ret = lgdt3306a_read_reg(state, 0x0002, &val); 384 val &= 0xf7; /* SPECINVAUTO Off */ 385 val |= 0x04; /* SPECINV On */ 386 ret = lgdt3306a_write_reg(state, 0x0002, val); 387 if (lg_chkerr(ret)) 388 goto fail; 389 390 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */ 391 ret = lgdt3306a_write_reg(state, 0x0008, 0x80); 392 if (lg_chkerr(ret)) 393 goto fail; 394 395 /* 2. Bandwidth mode for VSB(6MHz) */ 396 ret = lgdt3306a_read_reg(state, 0x0009, &val); 397 val &= 0xe3; 398 val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */ 399 ret = lgdt3306a_write_reg(state, 0x0009, val); 400 if (lg_chkerr(ret)) 401 goto fail; 402 403 /* 3. QAM mode detection mode(None) */ 404 ret = lgdt3306a_read_reg(state, 0x0009, &val); 405 val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */ 406 ret = lgdt3306a_write_reg(state, 0x0009, val); 407 if (lg_chkerr(ret)) 408 goto fail; 409 410 /* 4. ADC sampling frequency rate(2x sampling) */ 411 ret = lgdt3306a_read_reg(state, 0x000d, &val); 412 val &= 0xbf; /* SAMPLING4XFEN=0 */ 413 ret = lgdt3306a_write_reg(state, 0x000d, val); 414 if (lg_chkerr(ret)) 415 goto fail; 416 417#if 0 418 /* FGR - disable any AICC filtering, testing only */ 419 420 ret = lgdt3306a_write_reg(state, 0x0024, 0x00); 421 if (lg_chkerr(ret)) 422 goto fail; 423 424 /* AICCFIXFREQ0 NT N-1(Video rejection) */ 425 ret = lgdt3306a_write_reg(state, 0x002e, 0x00); 426 ret = lgdt3306a_write_reg(state, 0x002f, 0x00); 427 ret = lgdt3306a_write_reg(state, 0x0030, 0x00); 428 429 /* AICCFIXFREQ1 NT N-1(Audio rejection) */ 430 ret = lgdt3306a_write_reg(state, 0x002b, 0x00); 431 ret = lgdt3306a_write_reg(state, 0x002c, 0x00); 432 ret = lgdt3306a_write_reg(state, 0x002d, 0x00); 433 434 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */ 435 ret = lgdt3306a_write_reg(state, 0x0028, 0x00); 436 ret = lgdt3306a_write_reg(state, 0x0029, 0x00); 437 ret = lgdt3306a_write_reg(state, 0x002a, 0x00); 438 439 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */ 440 ret = lgdt3306a_write_reg(state, 0x0025, 0x00); 441 ret = lgdt3306a_write_reg(state, 0x0026, 0x00); 442 ret = lgdt3306a_write_reg(state, 0x0027, 0x00); 443 444#else 445 /* FGR - this works well for HVR-1955,1975 */ 446 447 /* 5. AICCOPMODE NT N-1 Adj. */ 448 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A); 449 if (lg_chkerr(ret)) 450 goto fail; 451 452 /* AICCFIXFREQ0 NT N-1(Video rejection) */ 453 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A); 454 ret = lgdt3306a_write_reg(state, 0x002f, 0x00); 455 ret = lgdt3306a_write_reg(state, 0x0030, 0x00); 456 457 /* AICCFIXFREQ1 NT N-1(Audio rejection) */ 458 ret = lgdt3306a_write_reg(state, 0x002b, 0x36); 459 ret = lgdt3306a_write_reg(state, 0x002c, 0x00); 460 ret = lgdt3306a_write_reg(state, 0x002d, 0x00); 461 462 /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */ 463 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A); 464 ret = lgdt3306a_write_reg(state, 0x0029, 0x00); 465 ret = lgdt3306a_write_reg(state, 0x002a, 0x00); 466 467 /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */ 468 ret = lgdt3306a_write_reg(state, 0x0025, 0x06); 469 ret = lgdt3306a_write_reg(state, 0x0026, 0x00); 470 ret = lgdt3306a_write_reg(state, 0x0027, 0x00); 471#endif 472 473 ret = lgdt3306a_read_reg(state, 0x001e, &val); 474 val &= 0x0f; 475 val |= 0xa0; 476 ret = lgdt3306a_write_reg(state, 0x001e, val); 477 478 ret = lgdt3306a_write_reg(state, 0x0022, 0x08); 479 480 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF); 481 482 ret = lgdt3306a_read_reg(state, 0x211f, &val); 483 val &= 0xef; 484 ret = lgdt3306a_write_reg(state, 0x211f, val); 485 486 ret = lgdt3306a_write_reg(state, 0x2173, 0x01); 487 488 ret = lgdt3306a_read_reg(state, 0x1061, &val); 489 val &= 0xf8; 490 val |= 0x04; 491 ret = lgdt3306a_write_reg(state, 0x1061, val); 492 493 ret = lgdt3306a_read_reg(state, 0x103d, &val); 494 val &= 0xcf; 495 ret = lgdt3306a_write_reg(state, 0x103d, val); 496 497 ret = lgdt3306a_write_reg(state, 0x2122, 0x40); 498 499 ret = lgdt3306a_read_reg(state, 0x2141, &val); 500 val &= 0x3f; 501 ret = lgdt3306a_write_reg(state, 0x2141, val); 502 503 ret = lgdt3306a_read_reg(state, 0x2135, &val); 504 val &= 0x0f; 505 val |= 0x70; 506 ret = lgdt3306a_write_reg(state, 0x2135, val); 507 508 ret = lgdt3306a_read_reg(state, 0x0003, &val); 509 val &= 0xf7; 510 ret = lgdt3306a_write_reg(state, 0x0003, val); 511 512 ret = lgdt3306a_read_reg(state, 0x001c, &val); 513 val &= 0x7f; 514 ret = lgdt3306a_write_reg(state, 0x001c, val); 515 516 /* 6. EQ step size */ 517 ret = lgdt3306a_read_reg(state, 0x2179, &val); 518 val &= 0xf8; 519 ret = lgdt3306a_write_reg(state, 0x2179, val); 520 521 ret = lgdt3306a_read_reg(state, 0x217a, &val); 522 val &= 0xf8; 523 ret = lgdt3306a_write_reg(state, 0x217a, val); 524 525 /* 7. Reset */ 526 ret = lgdt3306a_soft_reset(state); 527 if (lg_chkerr(ret)) 528 goto fail; 529 530 dbg_info("complete\n"); 531fail: 532 return ret; 533} 534 535static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation) 536{ 537 u8 val; 538 int ret; 539 540 dbg_info("modulation=%d\n", modulation); 541 542 /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */ 543 ret = lgdt3306a_write_reg(state, 0x0008, 0x08); 544 if (lg_chkerr(ret)) 545 goto fail; 546 547 /* 1a. Spectrum inversion detection to Auto */ 548 ret = lgdt3306a_read_reg(state, 0x0002, &val); 549 val &= 0xfb; /* SPECINV Off */ 550 val |= 0x08; /* SPECINVAUTO On */ 551 ret = lgdt3306a_write_reg(state, 0x0002, val); 552 if (lg_chkerr(ret)) 553 goto fail; 554 555 /* 2. Bandwidth mode for QAM */ 556 ret = lgdt3306a_read_reg(state, 0x0009, &val); 557 val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */ 558 ret = lgdt3306a_write_reg(state, 0x0009, val); 559 if (lg_chkerr(ret)) 560 goto fail; 561 562 /* 3. : 64QAM/256QAM detection(manual, auto) */ 563 ret = lgdt3306a_read_reg(state, 0x0009, &val); 564 val &= 0xfc; 565 val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */ 566 ret = lgdt3306a_write_reg(state, 0x0009, val); 567 if (lg_chkerr(ret)) 568 goto fail; 569 570 /* 3a. : 64QAM/256QAM selection for manual */ 571 ret = lgdt3306a_read_reg(state, 0x101a, &val); 572 val &= 0xf8; 573 if (modulation == QAM_64) 574 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */ 575 else 576 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */ 577 578 ret = lgdt3306a_write_reg(state, 0x101a, val); 579 if (lg_chkerr(ret)) 580 goto fail; 581 582 /* 4. ADC sampling frequency rate(4x sampling) */ 583 ret = lgdt3306a_read_reg(state, 0x000d, &val); 584 val &= 0xbf; 585 val |= 0x40; /* SAMPLING4XFEN=1 */ 586 ret = lgdt3306a_write_reg(state, 0x000d, val); 587 if (lg_chkerr(ret)) 588 goto fail; 589 590 /* 5. No AICC operation in QAM mode */ 591 ret = lgdt3306a_read_reg(state, 0x0024, &val); 592 val &= 0x00; 593 ret = lgdt3306a_write_reg(state, 0x0024, val); 594 if (lg_chkerr(ret)) 595 goto fail; 596 597 /* 6. Reset */ 598 ret = lgdt3306a_soft_reset(state); 599 if (lg_chkerr(ret)) 600 goto fail; 601 602 dbg_info("complete\n"); 603fail: 604 return ret; 605} 606 607static int lgdt3306a_set_modulation(struct lgdt3306a_state *state, 608 struct dtv_frontend_properties *p) 609{ 610 int ret; 611 612 dbg_info("\n"); 613 614 switch (p->modulation) { 615 case VSB_8: 616 ret = lgdt3306a_set_vsb(state); 617 break; 618 case QAM_64: 619 ret = lgdt3306a_set_qam(state, QAM_64); 620 break; 621 case QAM_256: 622 ret = lgdt3306a_set_qam(state, QAM_256); 623 break; 624 default: 625 return -EINVAL; 626 } 627 if (lg_chkerr(ret)) 628 goto fail; 629 630 state->current_modulation = p->modulation; 631 632fail: 633 return ret; 634} 635 636/* ------------------------------------------------------------------------ */ 637 638static int lgdt3306a_agc_setup(struct lgdt3306a_state *state, 639 struct dtv_frontend_properties *p) 640{ 641 /* TODO: anything we want to do here??? */ 642 dbg_info("\n"); 643 644 switch (p->modulation) { 645 case VSB_8: 646 break; 647 case QAM_64: 648 case QAM_256: 649 break; 650 default: 651 return -EINVAL; 652 } 653 return 0; 654} 655 656/* ------------------------------------------------------------------------ */ 657 658static int lgdt3306a_set_inversion(struct lgdt3306a_state *state, 659 int inversion) 660{ 661 int ret; 662 663 dbg_info("(%d)\n", inversion); 664 665 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0); 666 return ret; 667} 668 669static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state, 670 int enabled) 671{ 672 int ret; 673 674 dbg_info("(%d)\n", enabled); 675 676 /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */ 677 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled); 678 return ret; 679} 680 681static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state, 682 struct dtv_frontend_properties *p, 683 int inversion) 684{ 685 int ret = 0; 686 687 dbg_info("(%d)\n", inversion); 688#if 0 689 /* 690 * FGR - spectral_inversion defaults already set for VSB and QAM; 691 * can enable later if desired 692 */ 693 694 ret = lgdt3306a_set_inversion(state, inversion); 695 696 switch (p->modulation) { 697 case VSB_8: 698 /* Manual only for VSB */ 699 ret = lgdt3306a_set_inversion_auto(state, 0); 700 break; 701 case QAM_64: 702 case QAM_256: 703 /* Auto ok for QAM */ 704 ret = lgdt3306a_set_inversion_auto(state, 1); 705 break; 706 default: 707 ret = -EINVAL; 708 } 709#endif 710 return ret; 711} 712 713static int lgdt3306a_set_if(struct lgdt3306a_state *state, 714 struct dtv_frontend_properties *p) 715{ 716 int ret; 717 u16 if_freq_khz; 718 u8 nco1, nco2; 719 720 switch (p->modulation) { 721 case VSB_8: 722 if_freq_khz = state->cfg->vsb_if_khz; 723 break; 724 case QAM_64: 725 case QAM_256: 726 if_freq_khz = state->cfg->qam_if_khz; 727 break; 728 default: 729 return -EINVAL; 730 } 731 732 switch (if_freq_khz) { 733 default: 734 pr_warn("IF=%d KHz is not supportted, 3250 assumed\n", 735 if_freq_khz); 736 /* fallthrough */ 737 case 3250: /* 3.25Mhz */ 738 nco1 = 0x34; 739 nco2 = 0x00; 740 break; 741 case 3500: /* 3.50Mhz */ 742 nco1 = 0x38; 743 nco2 = 0x00; 744 break; 745 case 4000: /* 4.00Mhz */ 746 nco1 = 0x40; 747 nco2 = 0x00; 748 break; 749 case 5000: /* 5.00Mhz */ 750 nco1 = 0x50; 751 nco2 = 0x00; 752 break; 753 case 5380: /* 5.38Mhz */ 754 nco1 = 0x56; 755 nco2 = 0x14; 756 break; 757 } 758 ret = lgdt3306a_write_reg(state, 0x0010, nco1); 759 if (ret) 760 return ret; 761 ret = lgdt3306a_write_reg(state, 0x0011, nco2); 762 if (ret) 763 return ret; 764 765 dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2); 766 767 return 0; 768} 769 770/* ------------------------------------------------------------------------ */ 771 772static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 773{ 774 struct lgdt3306a_state *state = fe->demodulator_priv; 775 776 if (state->cfg->deny_i2c_rptr) { 777 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr); 778 return 0; 779 } 780 dbg_info("(%d)\n", enable); 781 782 /* NI2CRPTEN=0x80 */ 783 return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); 784} 785 786static int lgdt3306a_sleep(struct lgdt3306a_state *state) 787{ 788 int ret; 789 790 dbg_info("\n"); 791 state->current_frequency = -1; /* force re-tune, when we wake */ 792 793 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */ 794 if (lg_chkerr(ret)) 795 goto fail; 796 797 ret = lgdt3306a_power(state, 0); /* power down */ 798 lg_chkerr(ret); 799 800fail: 801 return 0; 802} 803 804static int lgdt3306a_fe_sleep(struct dvb_frontend *fe) 805{ 806 struct lgdt3306a_state *state = fe->demodulator_priv; 807 808 return lgdt3306a_sleep(state); 809} 810 811static int lgdt3306a_init(struct dvb_frontend *fe) 812{ 813 struct lgdt3306a_state *state = fe->demodulator_priv; 814 u8 val; 815 int ret; 816 817 dbg_info("\n"); 818 819 /* 1. Normal operation mode */ 820 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */ 821 if (lg_chkerr(ret)) 822 goto fail; 823 824 /* 2. Spectrum inversion auto detection (Not valid for VSB) */ 825 ret = lgdt3306a_set_inversion_auto(state, 0); 826 if (lg_chkerr(ret)) 827 goto fail; 828 829 /* 3. Spectrum inversion(According to the tuner configuration) */ 830 ret = lgdt3306a_set_inversion(state, 1); 831 if (lg_chkerr(ret)) 832 goto fail; 833 834 /* 4. Peak-to-peak voltage of ADC input signal */ 835 836 /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */ 837 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); 838 if (lg_chkerr(ret)) 839 goto fail; 840 841 /* 5. ADC output data capture clock phase */ 842 843 /* 0=same phase as ADC clock */ 844 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); 845 if (lg_chkerr(ret)) 846 goto fail; 847 848 /* 5a. ADC sampling clock source */ 849 850 /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */ 851 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); 852 if (lg_chkerr(ret)) 853 goto fail; 854 855 /* 6. Automatic PLL set */ 856 857 /* PLLSETAUTO=0x40; 0=off */ 858 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); 859 if (lg_chkerr(ret)) 860 goto fail; 861 862 if (state->cfg->xtalMHz == 24) { /* 24MHz */ 863 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */ 864 ret = lgdt3306a_read_reg(state, 0x0005, &val); 865 if (lg_chkerr(ret)) 866 goto fail; 867 val &= 0xc0; 868 val |= 0x25; 869 ret = lgdt3306a_write_reg(state, 0x0005, val); 870 if (lg_chkerr(ret)) 871 goto fail; 872 ret = lgdt3306a_write_reg(state, 0x0006, 0x64); 873 if (lg_chkerr(ret)) 874 goto fail; 875 876 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */ 877 ret = lgdt3306a_read_reg(state, 0x000d, &val); 878 if (lg_chkerr(ret)) 879 goto fail; 880 val &= 0xc0; 881 val |= 0x18; 882 ret = lgdt3306a_write_reg(state, 0x000d, val); 883 if (lg_chkerr(ret)) 884 goto fail; 885 886 } else if (state->cfg->xtalMHz == 25) { /* 25MHz */ 887 /* 7. Frequency for PLL output */ 888 ret = lgdt3306a_read_reg(state, 0x0005, &val); 889 if (lg_chkerr(ret)) 890 goto fail; 891 val &= 0xc0; 892 val |= 0x25; 893 ret = lgdt3306a_write_reg(state, 0x0005, val); 894 if (lg_chkerr(ret)) 895 goto fail; 896 ret = lgdt3306a_write_reg(state, 0x0006, 0x64); 897 if (lg_chkerr(ret)) 898 goto fail; 899 900 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */ 901 ret = lgdt3306a_read_reg(state, 0x000d, &val); 902 if (lg_chkerr(ret)) 903 goto fail; 904 val &= 0xc0; 905 val |= 0x19; 906 ret = lgdt3306a_write_reg(state, 0x000d, val); 907 if (lg_chkerr(ret)) 908 goto fail; 909 } else { 910 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz); 911 } 912#if 0 913 ret = lgdt3306a_write_reg(state, 0x000e, 0x00); 914 ret = lgdt3306a_write_reg(state, 0x000f, 0x00); 915#endif 916 917 /* 9. Center frequency of input signal of ADC */ 918 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */ 919 ret = lgdt3306a_write_reg(state, 0x0011, 0x00); 920 921 /* 10. Fixed gain error value */ 922 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */ 923 924 /* 10a. VSB TR BW gear shift initial step */ 925 ret = lgdt3306a_read_reg(state, 0x103c, &val); 926 val &= 0x0f; 927 val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */ 928 ret = lgdt3306a_write_reg(state, 0x103c, val); 929 930 /* 10b. Timing offset calibration in low temperature for VSB */ 931 ret = lgdt3306a_read_reg(state, 0x103d, &val); 932 val &= 0xfc; 933 val |= 0x03; 934 ret = lgdt3306a_write_reg(state, 0x103d, val); 935 936 /* 10c. Timing offset calibration in low temperature for QAM */ 937 ret = lgdt3306a_read_reg(state, 0x1036, &val); 938 val &= 0xf0; 939 val |= 0x0c; 940 ret = lgdt3306a_write_reg(state, 0x1036, val); 941 942 /* 11. Using the imaginary part of CIR in CIR loading */ 943 ret = lgdt3306a_read_reg(state, 0x211f, &val); 944 val &= 0xef; /* do not use imaginary of CIR */ 945 ret = lgdt3306a_write_reg(state, 0x211f, val); 946 947 /* 12. Control of no signal detector function */ 948 ret = lgdt3306a_read_reg(state, 0x2849, &val); 949 val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */ 950 ret = lgdt3306a_write_reg(state, 0x2849, val); 951 952 /* FGR - put demod in some known mode */ 953 ret = lgdt3306a_set_vsb(state); 954 955 /* 13. TP stream format */ 956 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode); 957 958 /* 14. disable output buses */ 959 ret = lgdt3306a_mpeg_tristate(state, 1); 960 961 /* 15. Sleep (in reset) */ 962 ret = lgdt3306a_sleep(state); 963 lg_chkerr(ret); 964 965fail: 966 return ret; 967} 968 969static int lgdt3306a_set_parameters(struct dvb_frontend *fe) 970{ 971 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 972 struct lgdt3306a_state *state = fe->demodulator_priv; 973 int ret; 974 975 dbg_info("(%d, %d)\n", p->frequency, p->modulation); 976 977 if (state->current_frequency == p->frequency && 978 state->current_modulation == p->modulation) { 979 dbg_info(" (already set, skipping ...)\n"); 980 return 0; 981 } 982 state->current_frequency = -1; 983 state->current_modulation = -1; 984 985 ret = lgdt3306a_power(state, 1); /* power up */ 986 if (lg_chkerr(ret)) 987 goto fail; 988 989 if (fe->ops.tuner_ops.set_params) { 990 ret = fe->ops.tuner_ops.set_params(fe); 991 if (fe->ops.i2c_gate_ctrl) 992 fe->ops.i2c_gate_ctrl(fe, 0); 993#if 0 994 if (lg_chkerr(ret)) 995 goto fail; 996 state->current_frequency = p->frequency; 997#endif 998 } 999 1000 ret = lgdt3306a_set_modulation(state, p); 1001 if (lg_chkerr(ret)) 1002 goto fail; 1003 1004 ret = lgdt3306a_agc_setup(state, p); 1005 if (lg_chkerr(ret)) 1006 goto fail; 1007 1008 ret = lgdt3306a_set_if(state, p); 1009 if (lg_chkerr(ret)) 1010 goto fail; 1011 1012 ret = lgdt3306a_spectral_inversion(state, p, 1013 state->cfg->spectral_inversion ? 1 : 0); 1014 if (lg_chkerr(ret)) 1015 goto fail; 1016 1017 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode); 1018 if (lg_chkerr(ret)) 1019 goto fail; 1020 1021 ret = lgdt3306a_mpeg_mode_polarity(state, 1022 state->cfg->tpclk_edge, 1023 state->cfg->tpvalid_polarity); 1024 if (lg_chkerr(ret)) 1025 goto fail; 1026 1027 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */ 1028 if (lg_chkerr(ret)) 1029 goto fail; 1030 1031 ret = lgdt3306a_soft_reset(state); 1032 if (lg_chkerr(ret)) 1033 goto fail; 1034 1035#ifdef DBG_DUMP 1036 lgdt3306a_DumpAllRegs(state); 1037#endif 1038 state->current_frequency = p->frequency; 1039fail: 1040 return ret; 1041} 1042 1043static int lgdt3306a_get_frontend(struct dvb_frontend *fe) 1044{ 1045 struct lgdt3306a_state *state = fe->demodulator_priv; 1046 struct dtv_frontend_properties *p = &fe->dtv_property_cache; 1047 1048 dbg_info("(%u, %d)\n", 1049 state->current_frequency, state->current_modulation); 1050 1051 p->modulation = state->current_modulation; 1052 p->frequency = state->current_frequency; 1053 return 0; 1054} 1055 1056static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe) 1057{ 1058#if 1 1059 return DVBFE_ALGO_CUSTOM; 1060#else 1061 return DVBFE_ALGO_HW; 1062#endif 1063} 1064 1065/* ------------------------------------------------------------------------ */ 1066static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state) 1067{ 1068 u8 val; 1069 int ret; 1070 u8 snrRef, maxPowerMan, nCombDet; 1071 u16 fbDlyCir; 1072 1073 ret = lgdt3306a_read_reg(state, 0x21a1, &val); 1074 if (ret) 1075 return ret; 1076 snrRef = val & 0x3f; 1077 1078 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan); 1079 if (ret) 1080 return ret; 1081 1082 ret = lgdt3306a_read_reg(state, 0x2191, &val); 1083 if (ret) 1084 return ret; 1085 nCombDet = (val & 0x80) >> 7; 1086 1087 ret = lgdt3306a_read_reg(state, 0x2180, &val); 1088 if (ret) 1089 return ret; 1090 fbDlyCir = (val & 0x03) << 8; 1091 1092 ret = lgdt3306a_read_reg(state, 0x2181, &val); 1093 if (ret) 1094 return ret; 1095 fbDlyCir |= val; 1096 1097 dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n", 1098 snrRef, maxPowerMan, nCombDet, fbDlyCir); 1099 1100 /* Carrier offset sub loop bandwidth */ 1101 ret = lgdt3306a_read_reg(state, 0x1061, &val); 1102 if (ret) 1103 return ret; 1104 val &= 0xf8; 1105 if ((snrRef > 18) && (maxPowerMan > 0x68) 1106 && (nCombDet == 0x01) 1107 && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) { 1108 /* SNR is over 18dB and no ghosting */ 1109 val |= 0x00; /* final bandwidth = 0 */ 1110 } else { 1111 val |= 0x04; /* final bandwidth = 4 */ 1112 } 1113 ret = lgdt3306a_write_reg(state, 0x1061, val); 1114 if (ret) 1115 return ret; 1116 1117 /* Adjust Notch Filter */ 1118 ret = lgdt3306a_read_reg(state, 0x0024, &val); 1119 if (ret) 1120 return ret; 1121 val &= 0x0f; 1122 if (nCombDet == 0) { /* Turn on the Notch Filter */ 1123 val |= 0x50; 1124 } 1125 ret = lgdt3306a_write_reg(state, 0x0024, val); 1126 if (ret) 1127 return ret; 1128 1129 /* VSB Timing Recovery output normalization */ 1130 ret = lgdt3306a_read_reg(state, 0x103d, &val); 1131 if (ret) 1132 return ret; 1133 val &= 0xcf; 1134 val |= 0x20; 1135 ret = lgdt3306a_write_reg(state, 0x103d, val); 1136 1137 return ret; 1138} 1139 1140static enum lgdt3306a_modulation 1141lgdt3306a_check_oper_mode(struct lgdt3306a_state *state) 1142{ 1143 u8 val = 0; 1144 int ret; 1145 1146 ret = lgdt3306a_read_reg(state, 0x0081, &val); 1147 if (ret) 1148 goto err; 1149 1150 if (val & 0x80) { 1151 dbg_info("VSB\n"); 1152 return LG3306_VSB; 1153 } 1154 if (val & 0x08) { 1155 ret = lgdt3306a_read_reg(state, 0x00a6, &val); 1156 if (ret) 1157 goto err; 1158 val = val >> 2; 1159 if (val & 0x01) { 1160 dbg_info("QAM256\n"); 1161 return LG3306_QAM256; 1162 } 1163 dbg_info("QAM64\n"); 1164 return LG3306_QAM64; 1165 } 1166err: 1167 pr_warn("UNKNOWN\n"); 1168 return LG3306_UNKNOWN_MODE; 1169} 1170 1171static enum lgdt3306a_lock_status 1172lgdt3306a_check_lock_status(struct lgdt3306a_state *state, 1173 enum lgdt3306a_lock_check whatLock) 1174{ 1175 u8 val = 0; 1176 int ret; 1177 enum lgdt3306a_modulation modeOper; 1178 enum lgdt3306a_lock_status lockStatus; 1179 1180 modeOper = LG3306_UNKNOWN_MODE; 1181 1182 switch (whatLock) { 1183 case LG3306_SYNC_LOCK: 1184 { 1185 ret = lgdt3306a_read_reg(state, 0x00a6, &val); 1186 if (ret) 1187 return ret; 1188 1189 if ((val & 0x80) == 0x80) 1190 lockStatus = LG3306_LOCK; 1191 else 1192 lockStatus = LG3306_UNLOCK; 1193 1194 dbg_info("SYNC_LOCK=%x\n", lockStatus); 1195 break; 1196 } 1197 case LG3306_AGC_LOCK: 1198 { 1199 ret = lgdt3306a_read_reg(state, 0x0080, &val); 1200 if (ret) 1201 return ret; 1202 1203 if ((val & 0x40) == 0x40) 1204 lockStatus = LG3306_LOCK; 1205 else 1206 lockStatus = LG3306_UNLOCK; 1207 1208 dbg_info("AGC_LOCK=%x\n", lockStatus); 1209 break; 1210 } 1211 case LG3306_TR_LOCK: 1212 { 1213 modeOper = lgdt3306a_check_oper_mode(state); 1214 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) { 1215 ret = lgdt3306a_read_reg(state, 0x1094, &val); 1216 if (ret) 1217 return ret; 1218 1219 if ((val & 0x80) == 0x80) 1220 lockStatus = LG3306_LOCK; 1221 else 1222 lockStatus = LG3306_UNLOCK; 1223 } else 1224 lockStatus = LG3306_UNKNOWN_LOCK; 1225 1226 dbg_info("TR_LOCK=%x\n", lockStatus); 1227 break; 1228 } 1229 case LG3306_FEC_LOCK: 1230 { 1231 modeOper = lgdt3306a_check_oper_mode(state); 1232 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) { 1233 ret = lgdt3306a_read_reg(state, 0x0080, &val); 1234 if (ret) 1235 return ret; 1236 1237 if ((val & 0x10) == 0x10) 1238 lockStatus = LG3306_LOCK; 1239 else 1240 lockStatus = LG3306_UNLOCK; 1241 } else 1242 lockStatus = LG3306_UNKNOWN_LOCK; 1243 1244 dbg_info("FEC_LOCK=%x\n", lockStatus); 1245 break; 1246 } 1247 1248 default: 1249 lockStatus = LG3306_UNKNOWN_LOCK; 1250 pr_warn("UNKNOWN whatLock=%d\n", whatLock); 1251 break; 1252 } 1253 1254 return lockStatus; 1255} 1256 1257static enum lgdt3306a_neverlock_status 1258lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state) 1259{ 1260 u8 val = 0; 1261 int ret; 1262 enum lgdt3306a_neverlock_status lockStatus; 1263 1264 ret = lgdt3306a_read_reg(state, 0x0080, &val); 1265 if (ret) 1266 return ret; 1267 lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03); 1268 1269 dbg_info("NeverLock=%d", lockStatus); 1270 1271 return lockStatus; 1272} 1273 1274static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state) 1275{ 1276 u8 val = 0; 1277 int ret; 1278 u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus; 1279 1280 /* Channel variation */ 1281 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ); 1282 if (ret) 1283 return ret; 1284 1285 /* SNR of Frame sync */ 1286 ret = lgdt3306a_read_reg(state, 0x21a1, &val); 1287 if (ret) 1288 return ret; 1289 snrRef = val & 0x3f; 1290 1291 /* Strong Main CIR */ 1292 ret = lgdt3306a_read_reg(state, 0x2199, &val); 1293 if (ret) 1294 return ret; 1295 mainStrong = (val & 0x40) >> 6; 1296 1297 ret = lgdt3306a_read_reg(state, 0x0090, &val); 1298 if (ret) 1299 return ret; 1300 aiccrejStatus = (val & 0xf0) >> 4; 1301 1302 dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n", 1303 snrRef, mainStrong, aiccrejStatus, currChDiffACQ); 1304 1305#if 0 1306 /* Dynamic ghost exists */ 1307 if ((mainStrong == 0) && (currChDiffACQ > 0x70)) 1308#endif 1309 if (mainStrong == 0) { 1310 ret = lgdt3306a_read_reg(state, 0x2135, &val); 1311 if (ret) 1312 return ret; 1313 val &= 0x0f; 1314 val |= 0xa0; 1315 ret = lgdt3306a_write_reg(state, 0x2135, val); 1316 if (ret) 1317 return ret; 1318 1319 ret = lgdt3306a_read_reg(state, 0x2141, &val); 1320 if (ret) 1321 return ret; 1322 val &= 0x3f; 1323 val |= 0x80; 1324 ret = lgdt3306a_write_reg(state, 0x2141, val); 1325 if (ret) 1326 return ret; 1327 1328 ret = lgdt3306a_write_reg(state, 0x2122, 0x70); 1329 if (ret) 1330 return ret; 1331 } else { /* Weak ghost or static channel */ 1332 ret = lgdt3306a_read_reg(state, 0x2135, &val); 1333 if (ret) 1334 return ret; 1335 val &= 0x0f; 1336 val |= 0x70; 1337 ret = lgdt3306a_write_reg(state, 0x2135, val); 1338 if (ret) 1339 return ret; 1340 1341 ret = lgdt3306a_read_reg(state, 0x2141, &val); 1342 if (ret) 1343 return ret; 1344 val &= 0x3f; 1345 val |= 0x40; 1346 ret = lgdt3306a_write_reg(state, 0x2141, val); 1347 if (ret) 1348 return ret; 1349 1350 ret = lgdt3306a_write_reg(state, 0x2122, 0x40); 1351 if (ret) 1352 return ret; 1353 } 1354 return 0; 1355} 1356 1357static enum lgdt3306a_lock_status 1358lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state) 1359{ 1360 enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK; 1361 int i; 1362 1363 for (i = 0; i < 2; i++) { 1364 msleep(30); 1365 1366 syncLockStatus = lgdt3306a_check_lock_status(state, 1367 LG3306_SYNC_LOCK); 1368 1369 if (syncLockStatus == LG3306_LOCK) { 1370 dbg_info("locked(%d)\n", i); 1371 return LG3306_LOCK; 1372 } 1373 } 1374 dbg_info("not locked\n"); 1375 return LG3306_UNLOCK; 1376} 1377 1378static enum lgdt3306a_lock_status 1379lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state) 1380{ 1381 enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK; 1382 int i; 1383 1384 for (i = 0; i < 2; i++) { 1385 msleep(30); 1386 1387 FECLockStatus = lgdt3306a_check_lock_status(state, 1388 LG3306_FEC_LOCK); 1389 1390 if (FECLockStatus == LG3306_LOCK) { 1391 dbg_info("locked(%d)\n", i); 1392 return FECLockStatus; 1393 } 1394 } 1395 dbg_info("not locked\n"); 1396 return FECLockStatus; 1397} 1398 1399static enum lgdt3306a_neverlock_status 1400lgdt3306a_neverlock_poll(struct lgdt3306a_state *state) 1401{ 1402 enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL; 1403 int i; 1404 1405 for (i = 0; i < 5; i++) { 1406 msleep(30); 1407 1408 NLLockStatus = lgdt3306a_check_neverlock_status(state); 1409 1410 if (NLLockStatus == LG3306_NL_LOCK) { 1411 dbg_info("NL_LOCK(%d)\n", i); 1412 return NLLockStatus; 1413 } 1414 } 1415 dbg_info("NLLockStatus=%d\n", NLLockStatus); 1416 return NLLockStatus; 1417} 1418 1419static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state) 1420{ 1421 u8 val; 1422 int ret; 1423 1424 ret = lgdt3306a_read_reg(state, 0x00fa, &val); 1425 if (ret) 1426 return ret; 1427 1428 return val; 1429} 1430 1431static const u32 valx_x10[] = { 1432 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100 1433}; 1434static const u32 log10x_x1000[] = { 1435 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 1436}; 1437 1438static u32 log10_x1000(u32 x) 1439{ 1440 u32 diff_val, step_val, step_log10; 1441 u32 log_val = 0; 1442 u32 i; 1443 1444 if (x <= 0) 1445 return -1000000; /* signal error */ 1446 1447 if (x == 10) 1448 return 0; /* log(1)=0 */ 1449 1450 if (x < 10) { 1451 while (x < 10) { 1452 x = x * 10; 1453 log_val--; 1454 } 1455 } else { /* x > 10 */ 1456 while (x >= 100) { 1457 x = x / 10; 1458 log_val++; 1459 } 1460 } 1461 log_val *= 1000; 1462 1463 if (x == 10) /* was our input an exact multiple of 10 */ 1464 return log_val; /* don't need to interpolate */ 1465 1466 /* find our place on the log curve */ 1467 for (i = 1; i < ARRAY_SIZE(valx_x10); i++) { 1468 if (valx_x10[i] >= x) 1469 break; 1470 } 1471 if (i == ARRAY_SIZE(valx_x10)) 1472 return log_val + log10x_x1000[i - 1]; 1473 1474 diff_val = x - valx_x10[i-1]; 1475 step_val = valx_x10[i] - valx_x10[i - 1]; 1476 step_log10 = log10x_x1000[i] - log10x_x1000[i - 1]; 1477 1478 /* do a linear interpolation to get in-between values */ 1479 return log_val + log10x_x1000[i - 1] + 1480 ((diff_val*step_log10) / step_val); 1481} 1482 1483static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state) 1484{ 1485 u32 mse; /* Mean-Square Error */ 1486 u32 pwr; /* Constelation power */ 1487 u32 snr_x100; 1488 1489 mse = (read_reg(state, 0x00ec) << 8) | 1490 (read_reg(state, 0x00ed)); 1491 pwr = (read_reg(state, 0x00e8) << 8) | 1492 (read_reg(state, 0x00e9)); 1493 1494 if (mse == 0) /* no signal */ 1495 return 0; 1496 1497 snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000; 1498 dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100); 1499 1500 return snr_x100; 1501} 1502 1503static enum lgdt3306a_lock_status 1504lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state) 1505{ 1506 int ret; 1507 u8 cnt = 0; 1508 u8 packet_error; 1509 u32 snr; 1510 1511 for (cnt = 0; cnt < 10; cnt++) { 1512 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) { 1513 dbg_info("no sync lock!\n"); 1514 return LG3306_UNLOCK; 1515 } 1516 1517 msleep(20); 1518 ret = lgdt3306a_pre_monitoring(state); 1519 if (ret) 1520 break; 1521 1522 packet_error = lgdt3306a_get_packet_error(state); 1523 snr = lgdt3306a_calculate_snr_x100(state); 1524 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr); 1525 1526 if ((snr >= 1500) && (packet_error < 0xff)) 1527 return LG3306_LOCK; 1528 } 1529 1530 dbg_info("not locked!\n"); 1531 return LG3306_UNLOCK; 1532} 1533 1534static enum lgdt3306a_lock_status 1535lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state) 1536{ 1537 u8 cnt; 1538 u8 packet_error; 1539 u32 snr; 1540 1541 for (cnt = 0; cnt < 10; cnt++) { 1542 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) { 1543 dbg_info("no fec lock!\n"); 1544 return LG3306_UNLOCK; 1545 } 1546 1547 msleep(20); 1548 1549 packet_error = lgdt3306a_get_packet_error(state); 1550 snr = lgdt3306a_calculate_snr_x100(state); 1551 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr); 1552 1553 if ((snr >= 1500) && (packet_error < 0xff)) 1554 return LG3306_LOCK; 1555 } 1556 1557 dbg_info("not locked!\n"); 1558 return LG3306_UNLOCK; 1559} 1560 1561static int lgdt3306a_read_status(struct dvb_frontend *fe, fe_status_t *status) 1562{ 1563 struct lgdt3306a_state *state = fe->demodulator_priv; 1564 u16 strength = 0; 1565 int ret = 0; 1566 1567 if (fe->ops.tuner_ops.get_rf_strength) { 1568 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength); 1569 if (ret == 0) 1570 dbg_info("strength=%d\n", strength); 1571 else 1572 dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n"); 1573 } 1574 1575 *status = 0; 1576 if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) { 1577 *status |= FE_HAS_SIGNAL; 1578 *status |= FE_HAS_CARRIER; 1579 1580 switch (state->current_modulation) { 1581 case QAM_256: 1582 case QAM_64: 1583 if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) { 1584 *status |= FE_HAS_VITERBI; 1585 *status |= FE_HAS_SYNC; 1586 1587 *status |= FE_HAS_LOCK; 1588 } 1589 break; 1590 case VSB_8: 1591 if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) { 1592 *status |= FE_HAS_VITERBI; 1593 *status |= FE_HAS_SYNC; 1594 1595 *status |= FE_HAS_LOCK; 1596 1597 ret = lgdt3306a_monitor_vsb(state); 1598 } 1599 break; 1600 default: 1601 ret = -EINVAL; 1602 } 1603 } 1604 return ret; 1605} 1606 1607 1608static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr) 1609{ 1610 struct lgdt3306a_state *state = fe->demodulator_priv; 1611 1612 state->snr = lgdt3306a_calculate_snr_x100(state); 1613 /* report SNR in dB * 10 */ 1614 *snr = state->snr/10; 1615 1616 return 0; 1617} 1618 1619static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe, 1620 u16 *strength) 1621{ 1622 /* 1623 * Calculate some sort of "strength" from SNR 1624 */ 1625 struct lgdt3306a_state *state = fe->demodulator_priv; 1626 u16 snr; /* snr_x10 */ 1627 int ret; 1628 u32 ref_snr; /* snr*100 */ 1629 u32 str; 1630 1631 *strength = 0; 1632 1633 switch (state->current_modulation) { 1634 case VSB_8: 1635 ref_snr = 1600; /* 16dB */ 1636 break; 1637 case QAM_64: 1638 ref_snr = 2200; /* 22dB */ 1639 break; 1640 case QAM_256: 1641 ref_snr = 2800; /* 28dB */ 1642 break; 1643 default: 1644 return -EINVAL; 1645 } 1646 1647 ret = fe->ops.read_snr(fe, &snr); 1648 if (lg_chkerr(ret)) 1649 goto fail; 1650 1651 if (state->snr <= (ref_snr - 100)) 1652 str = 0; 1653 else if (state->snr <= ref_snr) 1654 str = (0xffff * 65) / 100; /* 65% */ 1655 else { 1656 str = state->snr - ref_snr; 1657 str /= 50; 1658 str += 78; /* 78%-100% */ 1659 if (str > 100) 1660 str = 100; 1661 str = (0xffff * str) / 100; 1662 } 1663 *strength = (u16)str; 1664 dbg_info("strength=%u\n", *strength); 1665 1666fail: 1667 return ret; 1668} 1669 1670/* ------------------------------------------------------------------------ */ 1671 1672static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber) 1673{ 1674 struct lgdt3306a_state *state = fe->demodulator_priv; 1675 u32 tmp; 1676 1677 *ber = 0; 1678#if 1 1679 /* FGR - FIXME - I don't know what value is expected by dvb_core 1680 * what is the scale of the value?? */ 1681 tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */ 1682 tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */ 1683 tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */ 1684 tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */ 1685 *ber = tmp; 1686 dbg_info("ber=%u\n", tmp); 1687#endif 1688 return 0; 1689} 1690 1691static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 1692{ 1693 struct lgdt3306a_state *state = fe->demodulator_priv; 1694 1695 *ucblocks = 0; 1696#if 1 1697 /* FGR - FIXME - I don't know what value is expected by dvb_core 1698 * what happens when value wraps? */ 1699 *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */ 1700 dbg_info("ucblocks=%u\n", *ucblocks); 1701#endif 1702 1703 return 0; 1704} 1705 1706static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, 1707 unsigned int mode_flags, unsigned int *delay, 1708 fe_status_t *status) 1709{ 1710 int ret = 0; 1711 struct lgdt3306a_state *state = fe->demodulator_priv; 1712 1713 dbg_info("re_tune=%u\n", re_tune); 1714 1715 if (re_tune) { 1716 state->current_frequency = -1; /* force re-tune */ 1717 ret = lgdt3306a_set_parameters(fe); 1718 if (ret != 0) 1719 return ret; 1720 } 1721 *delay = 125; 1722 ret = lgdt3306a_read_status(fe, status); 1723 1724 return ret; 1725} 1726 1727static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe, 1728 struct dvb_frontend_tune_settings 1729 *fe_tune_settings) 1730{ 1731 fe_tune_settings->min_delay_ms = 100; 1732 dbg_info("\n"); 1733 return 0; 1734} 1735 1736static int lgdt3306a_search(struct dvb_frontend *fe) 1737{ 1738 fe_status_t status = 0; 1739 int i, ret; 1740 1741 /* set frontend */ 1742 ret = lgdt3306a_set_parameters(fe); 1743 if (ret) 1744 goto error; 1745 1746 /* wait frontend lock */ 1747 for (i = 20; i > 0; i--) { 1748 dbg_info(": loop=%d\n", i); 1749 msleep(50); 1750 ret = lgdt3306a_read_status(fe, &status); 1751 if (ret) 1752 goto error; 1753 1754 if (status & FE_HAS_LOCK) 1755 break; 1756 } 1757 1758 /* check if we have a valid signal */ 1759 if (status & FE_HAS_LOCK) 1760 return DVBFE_ALGO_SEARCH_SUCCESS; 1761 else 1762 return DVBFE_ALGO_SEARCH_AGAIN; 1763 1764error: 1765 dbg_info("failed (%d)\n", ret); 1766 return DVBFE_ALGO_SEARCH_ERROR; 1767} 1768 1769static void lgdt3306a_release(struct dvb_frontend *fe) 1770{ 1771 struct lgdt3306a_state *state = fe->demodulator_priv; 1772 1773 dbg_info("\n"); 1774 kfree(state); 1775} 1776 1777static struct dvb_frontend_ops lgdt3306a_ops; 1778 1779struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, 1780 struct i2c_adapter *i2c_adap) 1781{ 1782 struct lgdt3306a_state *state = NULL; 1783 int ret; 1784 u8 val; 1785 1786 dbg_info("(%d-%04x)\n", 1787 i2c_adap ? i2c_adapter_id(i2c_adap) : 0, 1788 config ? config->i2c_addr : 0); 1789 1790 state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL); 1791 if (state == NULL) 1792 goto fail; 1793 1794 state->cfg = config; 1795 state->i2c_adap = i2c_adap; 1796 1797 memcpy(&state->frontend.ops, &lgdt3306a_ops, 1798 sizeof(struct dvb_frontend_ops)); 1799 state->frontend.demodulator_priv = state; 1800 1801 /* verify that we're talking to a lg3306a */ 1802 /* FGR - NOTE - there is no obvious ChipId to check; we check 1803 * some "known" bits after reset, but it's still just a guess */ 1804 ret = lgdt3306a_read_reg(state, 0x0000, &val); 1805 if (lg_chkerr(ret)) 1806 goto fail; 1807 if ((val & 0x74) != 0x74) { 1808 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74)); 1809#if 0 1810 /* FIXME - re-enable when we know this is right */ 1811 goto fail; 1812#endif 1813 } 1814 ret = lgdt3306a_read_reg(state, 0x0001, &val); 1815 if (lg_chkerr(ret)) 1816 goto fail; 1817 if ((val & 0xf6) != 0xc6) { 1818 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6)); 1819#if 0 1820 /* FIXME - re-enable when we know this is right */ 1821 goto fail; 1822#endif 1823 } 1824 ret = lgdt3306a_read_reg(state, 0x0002, &val); 1825 if (lg_chkerr(ret)) 1826 goto fail; 1827 if ((val & 0x73) != 0x03) { 1828 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73)); 1829#if 0 1830 /* FIXME - re-enable when we know this is right */ 1831 goto fail; 1832#endif 1833 } 1834 1835 state->current_frequency = -1; 1836 state->current_modulation = -1; 1837 1838 lgdt3306a_sleep(state); 1839 1840 return &state->frontend; 1841 1842fail: 1843 pr_warn("unable to detect LGDT3306A hardware\n"); 1844 kfree(state); 1845 return NULL; 1846} 1847EXPORT_SYMBOL(lgdt3306a_attach); 1848 1849#ifdef DBG_DUMP 1850 1851static const short regtab[] = { 1852 0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */ 1853 0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */ 1854 0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */ 1855 0x0003, /* AGCRFOUT */ 1856 0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */ 1857 0x0005, /* PLLINDIVSE */ 1858 0x0006, /* PLLCTRL[7:0] 11100001 */ 1859 0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */ 1860 0x0008, /* STDOPMODE[7:0] 10000000 */ 1861 0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */ 1862 0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */ 1863 0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */ 1864 0x000d, /* x SAMPLING4 */ 1865 0x000e, /* SAMFREQ[15:8] 00000000 */ 1866 0x000f, /* SAMFREQ[7:0] 00000000 */ 1867 0x0010, /* IFFREQ[15:8] 01100000 */ 1868 0x0011, /* IFFREQ[7:0] 00000000 */ 1869 0x0012, /* AGCEN AGCREFMO */ 1870 0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */ 1871 0x0014, /* AGCFIXVALUE[7:0] 01111111 */ 1872 0x0015, /* AGCREF[15:8] 00001010 */ 1873 0x0016, /* AGCREF[7:0] 11100100 */ 1874 0x0017, /* AGCDELAY[7:0] 00100000 */ 1875 0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */ 1876 0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */ 1877 0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */ 1878 0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */ 1879 0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */ 1880 0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */ 1881 0x0020, /* AICCDETTH[15:8] 01111100 */ 1882 0x0021, /* AICCDETTH[7:0] 00000000 */ 1883 0x0022, /* AICCOFFTH[15:8] 00000101 */ 1884 0x0023, /* AICCOFFTH[7:0] 11100000 */ 1885 0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */ 1886 0x0025, /* AICCFIXFREQ3[23:16] 00000000 */ 1887 0x0026, /* AICCFIXFREQ3[15:8] 00000000 */ 1888 0x0027, /* AICCFIXFREQ3[7:0] 00000000 */ 1889 0x0028, /* AICCFIXFREQ2[23:16] 00000000 */ 1890 0x0029, /* AICCFIXFREQ2[15:8] 00000000 */ 1891 0x002a, /* AICCFIXFREQ2[7:0] 00000000 */ 1892 0x002b, /* AICCFIXFREQ1[23:16] 00000000 */ 1893 0x002c, /* AICCFIXFREQ1[15:8] 00000000 */ 1894 0x002d, /* AICCFIXFREQ1[7:0] 00000000 */ 1895 0x002e, /* AICCFIXFREQ0[23:16] 00000000 */ 1896 0x002f, /* AICCFIXFREQ0[15:8] 00000000 */ 1897 0x0030, /* AICCFIXFREQ0[7:0] 00000000 */ 1898 0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */ 1899 0x0032, /* DAGC1STEN DAGC1STER */ 1900 0x0033, /* DAGC1STREF[15:8] 00001010 */ 1901 0x0034, /* DAGC1STREF[7:0] 11100100 */ 1902 0x0035, /* DAGC2NDE */ 1903 0x0036, /* DAGC2NDREF[15:8] 00001010 */ 1904 0x0037, /* DAGC2NDREF[7:0] 10000000 */ 1905 0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */ 1906 0x003d, /* 1'b1 SAMGEARS */ 1907 0x0040, /* SAMLFGMA */ 1908 0x0041, /* SAMLFBWM */ 1909 0x0044, /* 1'b1 CRGEARSHE */ 1910 0x0045, /* CRLFGMAN */ 1911 0x0046, /* CFLFBWMA */ 1912 0x0047, /* CRLFGMAN */ 1913 0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */ 1914 0x0049, /* CRLFBWMA */ 1915 0x004a, /* CRLFBWMA */ 1916 0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */ 1917 0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */ 1918 0x0071, /* TPSENB TPSSOPBITE */ 1919 0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */ 1920 0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */ 1921 0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */ 1922 0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */ 1923 0x0078, /* NBERPOLY[31:24] 00000000 */ 1924 0x0079, /* NBERPOLY[23:16] 00000000 */ 1925 0x007a, /* NBERPOLY[15:8] 00000000 */ 1926 0x007b, /* NBERPOLY[7:0] 00000000 */ 1927 0x007c, /* NBERPED[31:24] 00000000 */ 1928 0x007d, /* NBERPED[23:16] 00000000 */ 1929 0x007e, /* NBERPED[15:8] 00000000 */ 1930 0x007f, /* NBERPED[7:0] 00000000 */ 1931 0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */ 1932 0x0085, /* SPECINVST */ 1933 0x0088, /* SYSLOCKTIME[15:8] */ 1934 0x0089, /* SYSLOCKTIME[7:0] */ 1935 0x008c, /* FECLOCKTIME[15:8] */ 1936 0x008d, /* FECLOCKTIME[7:0] */ 1937 0x008e, /* AGCACCOUT[15:8] */ 1938 0x008f, /* AGCACCOUT[7:0] */ 1939 0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */ 1940 0x0091, /* AICCVSYNC */ 1941 0x009c, /* CARRFREQOFFSET[15:8] */ 1942 0x009d, /* CARRFREQOFFSET[7:0] */ 1943 0x00a1, /* SAMFREQOFFSET[23:16] */ 1944 0x00a2, /* SAMFREQOFFSET[15:8] */ 1945 0x00a3, /* SAMFREQOFFSET[7:0] */ 1946 0x00a6, /* SYNCLOCK SYNCLOCKH */ 1947#if 0 /* covered elsewhere */ 1948 0x00e8, /* CONSTPWR[15:8] */ 1949 0x00e9, /* CONSTPWR[7:0] */ 1950 0x00ea, /* BMSE[15:8] */ 1951 0x00eb, /* BMSE[7:0] */ 1952 0x00ec, /* MSE[15:8] */ 1953 0x00ed, /* MSE[7:0] */ 1954 0x00ee, /* CONSTI[7:0] */ 1955 0x00ef, /* CONSTQ[7:0] */ 1956#endif 1957 0x00f4, /* TPIFTPERRCNT[7:0] */ 1958 0x00f5, /* TPCORREC */ 1959 0x00f6, /* VBBER[15:8] */ 1960 0x00f7, /* VBBER[7:0] */ 1961 0x00f8, /* VABER[15:8] */ 1962 0x00f9, /* VABER[7:0] */ 1963 0x00fa, /* TPERRCNT[7:0] */ 1964 0x00fb, /* NBERLOCK x x x x x x x */ 1965 0x00fc, /* NBERVALUE[31:24] */ 1966 0x00fd, /* NBERVALUE[23:16] */ 1967 0x00fe, /* NBERVALUE[15:8] */ 1968 0x00ff, /* NBERVALUE[7:0] */ 1969 0x1000, /* 1'b0 WODAGCOU */ 1970 0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */ 1971 0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */ 1972 0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */ 1973 0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */ 1974 0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */ 1975 0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */ 1976 0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */ 1977 0x103f, /* SAMZTEDSE */ 1978 0x105d, /* EQSTATUSE */ 1979 0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */ 1980 0x1060, /* 1'b1 EQSTATUSE */ 1981 0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */ 1982 0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */ 1983 0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */ 1984 0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */ 1985 0x106e, /* x x x x x CREPHNEN_ */ 1986 0x106f, /* CREPHNTH_V[7:0] 00010101 */ 1987 0x1072, /* CRSWEEPN */ 1988 0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */ 1989 0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */ 1990 0x1080, /* DAFTSTATUS[1:0] x x x x x x */ 1991 0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */ 1992 0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */ 1993 0x10b7, /* EQSTATUS_V[1:0] x x x x x x */ 1994#if 0 /* SMART_ANT */ 1995 0x1f00, /* MODEDETE */ 1996 0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */ 1997 0x1f03, /* NUMOFANT[7:0] 10000000 */ 1998 0x1f04, /* x SELMASK[6:0] x0000000 */ 1999 0x1f05, /* x SETMASK[6:0] x0000000 */ 2000 0x1f06, /* x TXDATA[6:0] x0000000 */ 2001 0x1f07, /* x CHNUMBER[6:0] x0000000 */ 2002 0x1f09, /* AGCTIME[23:16] 10011000 */ 2003 0x1f0a, /* AGCTIME[15:8] 10010110 */ 2004 0x1f0b, /* AGCTIME[7:0] 10000000 */ 2005 0x1f0c, /* ANTTIME[31:24] 00000000 */ 2006 0x1f0d, /* ANTTIME[23:16] 00000011 */ 2007 0x1f0e, /* ANTTIME[15:8] 10010000 */ 2008 0x1f0f, /* ANTTIME[7:0] 10010000 */ 2009 0x1f11, /* SYNCTIME[23:16] 10011000 */ 2010 0x1f12, /* SYNCTIME[15:8] 10010110 */ 2011 0x1f13, /* SYNCTIME[7:0] 10000000 */ 2012 0x1f14, /* SNRTIME[31:24] 00000001 */ 2013 0x1f15, /* SNRTIME[23:16] 01111101 */ 2014 0x1f16, /* SNRTIME[15:8] 01111000 */ 2015 0x1f17, /* SNRTIME[7:0] 01000000 */ 2016 0x1f19, /* FECTIME[23:16] 00000000 */ 2017 0x1f1a, /* FECTIME[15:8] 01110010 */ 2018 0x1f1b, /* FECTIME[7:0] 01110000 */ 2019 0x1f1d, /* FECTHD[7:0] 00000011 */ 2020 0x1f1f, /* SNRTHD[23:16] 00001000 */ 2021 0x1f20, /* SNRTHD[15:8] 01111111 */ 2022 0x1f21, /* SNRTHD[7:0] 10000101 */ 2023 0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */ 2024 0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */ 2025 0x1f82, /* x x x SCANOPCD[4:0] */ 2026 0x1f83, /* x x x x MAINOPCD[3:0] */ 2027 0x1f84, /* x x RXDATA[13:8] */ 2028 0x1f85, /* RXDATA[7:0] */ 2029 0x1f86, /* x x SDTDATA[13:8] */ 2030 0x1f87, /* SDTDATA[7:0] */ 2031 0x1f89, /* ANTSNR[23:16] */ 2032 0x1f8a, /* ANTSNR[15:8] */ 2033 0x1f8b, /* ANTSNR[7:0] */ 2034 0x1f8c, /* x x x x ANTFEC[13:8] */ 2035 0x1f8d, /* ANTFEC[7:0] */ 2036 0x1f8e, /* MAXCNT[7:0] */ 2037 0x1f8f, /* SCANCNT[7:0] */ 2038 0x1f91, /* MAXPW[23:16] */ 2039 0x1f92, /* MAXPW[15:8] */ 2040 0x1f93, /* MAXPW[7:0] */ 2041 0x1f95, /* CURPWMSE[23:16] */ 2042 0x1f96, /* CURPWMSE[15:8] */ 2043 0x1f97, /* CURPWMSE[7:0] */ 2044#endif /* SMART_ANT */ 2045 0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */ 2046 0x212a, /* EQAUTOST */ 2047 0x2122, /* CHFAST[7:0] 01100000 */ 2048 0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */ 2049 0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */ 2050 0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */ 2051 0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */ 2052 0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */ 2053 0x2162, /* AICCCTRLE */ 2054 0x2173, /* PHNCNFCNT[7:0] 00000100 */ 2055 0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */ 2056 0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */ 2057 0x217e, /* CNFCNTTPIF[7:0] 00001000 */ 2058 0x217f, /* TPERRCNTTPIF[7:0] 00000001 */ 2059 0x2180, /* x x x x x x FBDLYCIR[9:8] */ 2060 0x2181, /* FBDLYCIR[7:0] */ 2061 0x2185, /* MAXPWRMAIN[7:0] */ 2062 0x2191, /* NCOMBDET x x x x x x x */ 2063 0x2199, /* x MAINSTRON */ 2064 0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */ 2065 0x21a1, /* x x SNRREF[5:0] */ 2066 0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */ 2067 0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */ 2068 0x2847, /* ENNOSIGDE */ 2069 0x2849, /* 1'b1 1'b1 NOUSENOSI */ 2070 0x284a, /* EQINITWAITTIME[7:0] 01100100 */ 2071 0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */ 2072 0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */ 2073 0x3031, /* FRAMELOC */ 2074 0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */ 2075 0x30a9, /* VDLOCK_Q FRAMELOCK */ 2076 0x30aa, /* MPEGLOCK */ 2077}; 2078 2079#define numDumpRegs (sizeof(regtab)/sizeof(regtab[0])) 2080static u8 regval1[numDumpRegs] = {0, }; 2081static u8 regval2[numDumpRegs] = {0, }; 2082 2083static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state) 2084{ 2085 memset(regval2, 0xff, sizeof(regval2)); 2086 lgdt3306a_DumpRegs(state); 2087} 2088 2089static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state) 2090{ 2091 int i; 2092 int sav_debug = debug; 2093 2094 if ((debug & DBG_DUMP) == 0) 2095 return; 2096 debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */ 2097 2098 lg_debug("\n"); 2099 2100 for (i = 0; i < numDumpRegs; i++) { 2101 lgdt3306a_read_reg(state, regtab[i], ®val1[i]); 2102 if (regval1[i] != regval2[i]) { 2103 lg_debug(" %04X = %02X\n", regtab[i], regval1[i]); 2104 regval2[i] = regval1[i]; 2105 } 2106 } 2107 debug = sav_debug; 2108} 2109#endif /* DBG_DUMP */ 2110 2111 2112 2113static struct dvb_frontend_ops lgdt3306a_ops = { 2114 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, 2115 .info = { 2116 .name = "LG Electronics LGDT3306A VSB/QAM Frontend", 2117 .frequency_min = 54000000, 2118 .frequency_max = 858000000, 2119 .frequency_stepsize = 62500, 2120 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB 2121 }, 2122 .i2c_gate_ctrl = lgdt3306a_i2c_gate_ctrl, 2123 .init = lgdt3306a_init, 2124 .sleep = lgdt3306a_fe_sleep, 2125 /* if this is set, it overrides the default swzigzag */ 2126 .tune = lgdt3306a_tune, 2127 .set_frontend = lgdt3306a_set_parameters, 2128 .get_frontend = lgdt3306a_get_frontend, 2129 .get_frontend_algo = lgdt3306a_get_frontend_algo, 2130 .get_tune_settings = lgdt3306a_get_tune_settings, 2131 .read_status = lgdt3306a_read_status, 2132 .read_ber = lgdt3306a_read_ber, 2133 .read_signal_strength = lgdt3306a_read_signal_strength, 2134 .read_snr = lgdt3306a_read_snr, 2135 .read_ucblocks = lgdt3306a_read_ucblocks, 2136 .release = lgdt3306a_release, 2137 .ts_bus_ctrl = lgdt3306a_ts_bus_ctrl, 2138 .search = lgdt3306a_search, 2139}; 2140 2141MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver"); 2142MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>"); 2143MODULE_LICENSE("GPL"); 2144MODULE_VERSION("0.2"); 2145