63 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)  in reg_write()  argument
68 	ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf));  in reg_write()
74 static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val)  in reg_read()  argument
78 			.addr = state->i2c->addr,  in reg_read()
84 			.addr = state->i2c->addr,  in reg_read()
92 	ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs));  in reg_read()
99 static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast)  in qm1d1c0042_set_srch_mode()  argument
102 		state->regs[0x03] |= 0x01; /* set fast search mode */  in qm1d1c0042_set_srch_mode()
104 		state->regs[0x03] &= ~0x01 & 0xff;  in qm1d1c0042_set_srch_mode()
106 	return reg_write(state, 0x03, state->regs[0x03]);  in qm1d1c0042_set_srch_mode()
109 static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state)  in qm1d1c0042_wakeup()  argument
113 	state->regs[0x01] |= 1 << 3;             /* BB_Reg_enable */  in qm1d1c0042_wakeup()
114 	state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */  in qm1d1c0042_wakeup()
115 	state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */  in qm1d1c0042_wakeup()
116 	ret = reg_write(state, 0x01, state->regs[0x01]);  in qm1d1c0042_wakeup()
118 		ret = reg_write(state, 0x05, state->regs[0x05]);  in qm1d1c0042_wakeup()
121 		dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",  in qm1d1c0042_wakeup()
122 			__func__, state->cfg.fe->dvb->num, state->cfg.fe->id);  in qm1d1c0042_wakeup()
130 	struct qm1d1c0042_state *state;  in qm1d1c0042_set_config()  local
133 	state = fe->tuner_priv;  in qm1d1c0042_set_config()
137 		state->cfg.fe = cfg->fe;  in qm1d1c0042_set_config()
140 		dev_warn(&state->i2c->dev,  in qm1d1c0042_set_config()
142 	state->cfg.xtal_freq = default_cfg.xtal_freq;  in qm1d1c0042_set_config()
144 	state->cfg.lpf = cfg->lpf;  in qm1d1c0042_set_config()
145 	state->cfg.fast_srch = cfg->fast_srch;  in qm1d1c0042_set_config()
148 		state->cfg.lpf_wait = cfg->lpf_wait;  in qm1d1c0042_set_config()
150 		state->cfg.lpf_wait = default_cfg.lpf_wait;  in qm1d1c0042_set_config()
153 		state->cfg.fast_srch_wait = cfg->fast_srch_wait;  in qm1d1c0042_set_config()
155 		state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;  in qm1d1c0042_set_config()
158 		state->cfg.normal_srch_wait = cfg->normal_srch_wait;  in qm1d1c0042_set_config()
160 		state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;  in qm1d1c0042_set_config()
180 	struct qm1d1c0042_state *state;  in qm1d1c0042_set_params()  local
187 	state = fe->tuner_priv;  in qm1d1c0042_set_params()
190 	state->regs[0x08] &= 0xf0;  in qm1d1c0042_set_params()
191 	state->regs[0x08] |= 0x09;  in qm1d1c0042_set_params()
193 	state->regs[0x13] &= 0x9f;  in qm1d1c0042_set_params()
194 	state->regs[0x13] |= 0x20;  in qm1d1c0042_set_params()
197 	val = state->regs[0x02] & 0x0f;  in qm1d1c0042_set_params()
204 	ret = reg_write(state, 0x02, val);  in qm1d1c0042_set_params()
208 	a = (freq + state->cfg.xtal_freq / 2) / state->cfg.xtal_freq;  in qm1d1c0042_set_params()
210 	state->regs[0x06] &= 0x40;  in qm1d1c0042_set_params()
211 	state->regs[0x06] |= (a - 12) / 4;  in qm1d1c0042_set_params()
212 	ret = reg_write(state, 0x06, state->regs[0x06]);  in qm1d1c0042_set_params()
216 	state->regs[0x07] &= 0xf0;  in qm1d1c0042_set_params()
217 	state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f;  in qm1d1c0042_set_params()
218 	ret = reg_write(state, 0x07, state->regs[0x07]);  in qm1d1c0042_set_params()
223 	val = state->regs[0x08];  in qm1d1c0042_set_params()
224 	if (state->cfg.lpf) {  in qm1d1c0042_set_params()
229 	ret = reg_write(state, 0x08, val);  in qm1d1c0042_set_params()
238 	b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)  in qm1d1c0042_set_params()
246 	state->regs[0x09] &= 0xc0;  in qm1d1c0042_set_params()
247 	state->regs[0x09] |= (sd >> 16) & 0x3f;  in qm1d1c0042_set_params()
248 	state->regs[0x0a] = (sd >> 8) & 0xff;  in qm1d1c0042_set_params()
249 	state->regs[0x0b] = sd & 0xff;  in qm1d1c0042_set_params()
250 	ret = reg_write(state, 0x09, state->regs[0x09]);  in qm1d1c0042_set_params()
252 		ret = reg_write(state, 0x0a, state->regs[0x0a]);  in qm1d1c0042_set_params()
254 		ret = reg_write(state, 0x0b, state->regs[0x0b]);  in qm1d1c0042_set_params()
258 	if (!state->cfg.lpf) {  in qm1d1c0042_set_params()
260 		ret = reg_write(state, 0x13, state->regs[0x13]);  in qm1d1c0042_set_params()
266 	mask = state->cfg.lpf ? 0x3f : 0x7f;  in qm1d1c0042_set_params()
267 	val = state->regs[0x0c] & mask;  in qm1d1c0042_set_params()
268 	ret = reg_write(state, 0x0c, val);  in qm1d1c0042_set_params()
272 	val = state->regs[0x0c] | ~mask;  in qm1d1c0042_set_params()
273 	ret = reg_write(state, 0x0c, val);  in qm1d1c0042_set_params()
277 	if (state->cfg.lpf)  in qm1d1c0042_set_params()
278 		msleep(state->cfg.lpf_wait);  in qm1d1c0042_set_params()
279 	else if (state->regs[0x03] & 0x01)  in qm1d1c0042_set_params()
280 		msleep(state->cfg.fast_srch_wait);  in qm1d1c0042_set_params()
282 		msleep(state->cfg.normal_srch_wait);  in qm1d1c0042_set_params()
284 	if (state->cfg.lpf) {  in qm1d1c0042_set_params()
286 		ret = reg_write(state, 0x08, 0x09);  in qm1d1c0042_set_params()
291 		ret = reg_write(state, 0x13, state->regs[0x13]);  in qm1d1c0042_set_params()
300 	struct qm1d1c0042_state *state;  in qm1d1c0042_sleep()  local
303 	state = fe->tuner_priv;  in qm1d1c0042_sleep()
304 	state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */  in qm1d1c0042_sleep()
305 	state->regs[0x01] |= 1 << 0;             /* STDBY */  in qm1d1c0042_sleep()
306 	state->regs[0x05] |= 1 << 3;             /* pfd_rst STANDBY */  in qm1d1c0042_sleep()
307 	ret = reg_write(state, 0x05, state->regs[0x05]);  in qm1d1c0042_sleep()
309 		ret = reg_write(state, 0x01, state->regs[0x01]);  in qm1d1c0042_sleep()
311 		dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",  in qm1d1c0042_sleep()
318 	struct qm1d1c0042_state *state;  in qm1d1c0042_init()  local
322 	state = fe->tuner_priv;  in qm1d1c0042_init()
323 	memcpy(state->regs, reg_initval, sizeof(reg_initval));  in qm1d1c0042_init()
325 	reg_write(state, 0x01, 0x0c);  in qm1d1c0042_init()
326 	reg_write(state, 0x01, 0x0c);  in qm1d1c0042_init()
328 	ret = reg_write(state, 0x01, 0x0c); /* soft reset on */  in qm1d1c0042_init()
333 	val = state->regs[0x01] | 0x10;  in qm1d1c0042_init()
334 	ret = reg_write(state, 0x01, val); /* soft reset off */  in qm1d1c0042_init()
339 	ret = reg_read(state, 0x00, &val);  in qm1d1c0042_init()
344 	state->regs[0x0c] |= 0x40;  in qm1d1c0042_init()
345 	ret = reg_write(state, 0x0c, state->regs[0x0c]);  in qm1d1c0042_init()
348 	msleep(state->cfg.lpf_wait);  in qm1d1c0042_init()
352 		ret = reg_write(state, i, state->regs[i]);  in qm1d1c0042_init()
357 		ret = reg_write(state, i, state->regs[i]);  in qm1d1c0042_init()
362 	ret = qm1d1c0042_wakeup(state);  in qm1d1c0042_init()
366 	ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);  in qm1d1c0042_init()
373 	dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",  in qm1d1c0042_init()
398 	struct qm1d1c0042_state *state;  in qm1d1c0042_probe()  local
402 	state = kzalloc(sizeof(*state), GFP_KERNEL);  in qm1d1c0042_probe()
403 	if (!state)  in qm1d1c0042_probe()
405 	state->i2c = client;  in qm1d1c0042_probe()
409 	fe->tuner_priv = state;  in qm1d1c0042_probe()
413 	i2c_set_clientdata(client, &state->cfg);  in qm1d1c0042_probe()
420 	struct qm1d1c0042_state *state;  in qm1d1c0042_remove()  local
422 	state = cfg_to_state(i2c_get_clientdata(client));  in qm1d1c0042_remove()
423 	state->cfg.fe->tuner_priv = NULL;  in qm1d1c0042_remove()
424 	kfree(state);  in qm1d1c0042_remove()