Lines Matching refs:state
248 static int mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len) in mt2063_write() argument
250 struct dvb_frontend *fe = state->frontend; in mt2063_write()
254 .addr = state->config->tuner_address, in mt2063_write()
267 ret = i2c_transfer(state->i2c, &msg, 1); in mt2063_write()
280 static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val) in mt2063_setreg() argument
289 status = mt2063_write(state, reg, &val, 1); in mt2063_setreg()
293 state->reg[reg] = val; in mt2063_setreg()
301 static int mt2063_read(struct mt2063_state *state, in mt2063_read() argument
305 struct dvb_frontend *fe = state->frontend; in mt2063_read()
317 .addr = state->config->tuner_address, in mt2063_read()
322 .addr = state->config->tuner_address, in mt2063_read()
329 status = i2c_transfer(state->i2c, msg, 2); in mt2063_read()
938 static int mt2063_lockStatus(struct mt2063_state *state) in mt2063_lockStatus() argument
951 if (state->tuner_id == MT2063_B0) in mt2063_lockStatus()
955 status = mt2063_read(state, MT2063_REG_LO_STATUS, in mt2063_lockStatus()
956 &state->reg[MT2063_REG_LO_STATUS], 1); in mt2063_lockStatus()
961 if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) == in mt2063_lockStatus()
1047 static u32 mt2063_get_dnc_output_enable(struct mt2063_state *state, in mt2063_get_dnc_output_enable() argument
1052 if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */ in mt2063_get_dnc_output_enable()
1053 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ in mt2063_get_dnc_output_enable()
1058 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ in mt2063_get_dnc_output_enable()
1069 static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state, in mt2063_set_dnc_output_enable() argument
1080 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ in mt2063_set_dnc_output_enable()
1081 if (state->reg[MT2063_REG_DNC_GAIN] != in mt2063_set_dnc_output_enable()
1084 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1088 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ in mt2063_set_dnc_output_enable()
1089 if (state->reg[MT2063_REG_VGA_GAIN] != in mt2063_set_dnc_output_enable()
1092 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1096 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ in mt2063_set_dnc_output_enable()
1097 if (state->reg[MT2063_REG_RSVD_20] != in mt2063_set_dnc_output_enable()
1100 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1106 …val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=… in mt2063_set_dnc_output_enable()
1107 if (state->reg[MT2063_REG_DNC_GAIN] != in mt2063_set_dnc_output_enable()
1110 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1114 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ in mt2063_set_dnc_output_enable()
1115 if (state->reg[MT2063_REG_VGA_GAIN] != in mt2063_set_dnc_output_enable()
1118 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1122 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ in mt2063_set_dnc_output_enable()
1123 if (state->reg[MT2063_REG_RSVD_20] != in mt2063_set_dnc_output_enable()
1126 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1132 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ in mt2063_set_dnc_output_enable()
1133 if (state->reg[MT2063_REG_DNC_GAIN] != in mt2063_set_dnc_output_enable()
1136 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1140 …val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=… in mt2063_set_dnc_output_enable()
1141 if (state->reg[MT2063_REG_VGA_GAIN] != in mt2063_set_dnc_output_enable()
1144 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1148 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ in mt2063_set_dnc_output_enable()
1149 if (state->reg[MT2063_REG_RSVD_20] != in mt2063_set_dnc_output_enable()
1152 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1158 …val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=… in mt2063_set_dnc_output_enable()
1159 if (state->reg[MT2063_REG_DNC_GAIN] != in mt2063_set_dnc_output_enable()
1162 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1166 …val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=… in mt2063_set_dnc_output_enable()
1167 if (state->reg[MT2063_REG_VGA_GAIN] != in mt2063_set_dnc_output_enable()
1170 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1174 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ in mt2063_set_dnc_output_enable()
1175 if (state->reg[MT2063_REG_RSVD_20] != in mt2063_set_dnc_output_enable()
1178 mt2063_setreg(state, in mt2063_set_dnc_output_enable()
1203 static u32 MT2063_SetReceiverMode(struct mt2063_state *state, in MT2063_SetReceiverMode() argument
1218 (state-> in MT2063_SetReceiverMode()
1222 if (state->reg[MT2063_REG_PD1_TGT] != val) in MT2063_SetReceiverMode()
1223 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); in MT2063_SetReceiverMode()
1228 u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) | in MT2063_SetReceiverMode()
1230 if (state->reg[MT2063_REG_CTRL_2C] != val) in MT2063_SetReceiverMode()
1231 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val); in MT2063_SetReceiverMode()
1237 (state-> in MT2063_SetReceiverMode()
1240 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) { in MT2063_SetReceiverMode()
1242 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val); in MT2063_SetReceiverMode()
1245 (state->reg[MT2063_REG_FIFF_CTRL] | 0x01); in MT2063_SetReceiverMode()
1247 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); in MT2063_SetReceiverMode()
1249 (state-> in MT2063_SetReceiverMode()
1252 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); in MT2063_SetReceiverMode()
1257 status |= mt2063_get_dnc_output_enable(state, &longval); in MT2063_SetReceiverMode()
1258 status |= mt2063_set_dnc_output_enable(state, longval); in MT2063_SetReceiverMode()
1262 u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) | in MT2063_SetReceiverMode()
1264 if (state->reg[MT2063_REG_LNA_OV] != val) in MT2063_SetReceiverMode()
1265 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val); in MT2063_SetReceiverMode()
1270 u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) | in MT2063_SetReceiverMode()
1272 if (state->reg[MT2063_REG_LNA_TGT] != val) in MT2063_SetReceiverMode()
1273 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); in MT2063_SetReceiverMode()
1278 u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) | in MT2063_SetReceiverMode()
1280 if (state->reg[MT2063_REG_RF_OV] != val) in MT2063_SetReceiverMode()
1281 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val); in MT2063_SetReceiverMode()
1286 u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) | in MT2063_SetReceiverMode()
1288 if (state->reg[MT2063_REG_PD1_TGT] != val) in MT2063_SetReceiverMode()
1289 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); in MT2063_SetReceiverMode()
1295 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5) in MT2063_SetReceiverMode()
1297 val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) | in MT2063_SetReceiverMode()
1299 if (state->reg[MT2063_REG_FIF_OV] != val) in MT2063_SetReceiverMode()
1300 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val); in MT2063_SetReceiverMode()
1305 u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) | in MT2063_SetReceiverMode()
1307 if (state->reg[MT2063_REG_PD2_TGT] != val) in MT2063_SetReceiverMode()
1308 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val); in MT2063_SetReceiverMode()
1313 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) | in MT2063_SetReceiverMode()
1315 if (state->reg[MT2063_REG_LNA_TGT] != val) in MT2063_SetReceiverMode()
1316 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); in MT2063_SetReceiverMode()
1321 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) | in MT2063_SetReceiverMode()
1323 if (state->reg[MT2063_REG_PD1_TGT] != val) in MT2063_SetReceiverMode()
1324 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); in MT2063_SetReceiverMode()
1328 state->rcvr_mode = Mode; in MT2063_SetReceiverMode()
1330 mt2063_mode_name[state->rcvr_mode]); in MT2063_SetReceiverMode()
1345 static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state, in MT2063_ClearPowerMaskBits() argument
1353 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); in MT2063_ClearPowerMaskBits()
1355 mt2063_write(state, in MT2063_ClearPowerMaskBits()
1357 &state->reg[MT2063_REG_PWR_2], 1); in MT2063_ClearPowerMaskBits()
1360 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); in MT2063_ClearPowerMaskBits()
1362 mt2063_write(state, in MT2063_ClearPowerMaskBits()
1364 &state->reg[MT2063_REG_PWR_1], 1); in MT2063_ClearPowerMaskBits()
1375 static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown) in MT2063_SoftwareShutdown() argument
1381 state->reg[MT2063_REG_PWR_1] |= 0x04; in MT2063_SoftwareShutdown()
1383 state->reg[MT2063_REG_PWR_1] &= ~0x04; in MT2063_SoftwareShutdown()
1385 status = mt2063_write(state, in MT2063_SoftwareShutdown()
1387 &state->reg[MT2063_REG_PWR_1], 1); in MT2063_SoftwareShutdown()
1390 state->reg[MT2063_REG_BYP_CTRL] = in MT2063_SoftwareShutdown()
1391 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; in MT2063_SoftwareShutdown()
1393 mt2063_write(state, in MT2063_SoftwareShutdown()
1395 &state->reg[MT2063_REG_BYP_CTRL], in MT2063_SoftwareShutdown()
1397 state->reg[MT2063_REG_BYP_CTRL] = in MT2063_SoftwareShutdown()
1398 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F); in MT2063_SoftwareShutdown()
1400 mt2063_write(state, in MT2063_SoftwareShutdown()
1402 &state->reg[MT2063_REG_BYP_CTRL], in MT2063_SoftwareShutdown()
1519 static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in) in FindClearTuneFilter() argument
1529 if (state->CTFiltMax[idx] >= f_in) { in FindClearTuneFilter()
1540 static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in) in MT2063_Tune() argument
1562 if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ) in MT2063_Tune()
1563 || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ)) in MT2063_Tune()
1569 ofLO1 = state->AS_Data.f_LO1; in MT2063_Tune()
1570 ofLO2 = state->AS_Data.f_LO2; in MT2063_Tune()
1575 if (state->ctfilt_sw == 1) { in MT2063_Tune()
1576 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08); in MT2063_Tune()
1577 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) { in MT2063_Tune()
1579 mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val); in MT2063_Tune()
1581 val = state->reg[MT2063_REG_CTUNE_OV]; in MT2063_Tune()
1582 RFBand = FindClearTuneFilter(state, f_in); in MT2063_Tune()
1583 state->reg[MT2063_REG_CTUNE_OV] = in MT2063_Tune()
1584 (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F) in MT2063_Tune()
1586 if (state->reg[MT2063_REG_CTUNE_OV] != val) { in MT2063_Tune()
1588 mt2063_setreg(state, MT2063_REG_CTUNE_OV, val); in MT2063_Tune()
1597 mt2063_read(state, in MT2063_Tune()
1599 &state->reg[MT2063_REG_FIFFC], 1); in MT2063_Tune()
1600 fiffc = state->reg[MT2063_REG_FIFFC]; in MT2063_Tune()
1605 state->AS_Data.f_in = f_in; in MT2063_Tune()
1607 state->AS_Data.f_if1_Request = in MT2063_Tune()
1608 MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in, in MT2063_Tune()
1609 state->AS_Data.f_LO1_Step, in MT2063_Tune()
1610 state->AS_Data.f_ref) - f_in; in MT2063_Tune()
1616 MT2063_ResetExclZones(&state->AS_Data); in MT2063_Tune()
1618 f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data); in MT2063_Tune()
1620 state->AS_Data.f_LO1 = in MT2063_Tune()
1621 MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step, in MT2063_Tune()
1622 state->AS_Data.f_ref); in MT2063_Tune()
1624 state->AS_Data.f_LO2 = in MT2063_Tune()
1625 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in, in MT2063_Tune()
1626 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref); in MT2063_Tune()
1632 status |= MT2063_AvoidSpurs(&state->AS_Data); in MT2063_Tune()
1638 state->AS_Data.f_LO1 = in MT2063_Tune()
1639 MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1, in MT2063_Tune()
1640 state->AS_Data.f_LO1_Step, state->AS_Data.f_ref); in MT2063_Tune()
1641 state->AS_Data.f_LO2 = in MT2063_Tune()
1642 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in, in MT2063_Tune()
1643 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref); in MT2063_Tune()
1644 state->AS_Data.f_LO2 = in MT2063_Tune()
1645 MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2, in MT2063_Tune()
1646 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref); in MT2063_Tune()
1651 if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ) in MT2063_Tune()
1652 || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ)) in MT2063_Tune()
1654 if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ) in MT2063_Tune()
1655 || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ)) in MT2063_Tune()
1658 if (state->tuner_id == MT2063_B0) in MT2063_Tune()
1665 if ((ofLO1 != state->AS_Data.f_LO1) in MT2063_Tune()
1666 || (ofLO2 != state->AS_Data.f_LO2) in MT2063_Tune()
1667 || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) != in MT2063_Tune()
1677 (state->AS_Data.f_LO1 - in MT2063_Tune()
1678 f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc - in MT2063_Tune()
1688 state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */ in MT2063_Tune()
1689 state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */ in MT2063_Tune()
1690 state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */ in MT2063_Tune()
1692 state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */ in MT2063_Tune()
1693 state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */ in MT2063_Tune()
1700 …status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0… in MT2063_Tune()
1701 if (state->tuner_id == MT2063_B0) { in MT2063_Tune()
1703 … status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ in MT2063_Tune()
1706 if (state->reg[MT2063_REG_FIFF_OFFSET] != in MT2063_Tune()
1708 state->reg[MT2063_REG_FIFF_OFFSET] = in MT2063_Tune()
1711 mt2063_write(state, in MT2063_Tune()
1713 &state-> in MT2063_Tune()
1726 status = mt2063_lockStatus(state); in MT2063_Tune()
1735 state->f_IF1_actual = state->AS_Data.f_LO1 - f_in; in MT2063_Tune()
1807 struct mt2063_state *state = fe->tuner_priv; in mt2063_init() local
1818 state->rcvr_mode = MT2063_CABLE_QAM; in mt2063_init()
1821 status = mt2063_read(state, MT2063_REG_PART_REV, in mt2063_init()
1822 &state->reg[MT2063_REG_PART_REV], 1); in mt2063_init()
1829 switch (state->reg[MT2063_REG_PART_REV]) { in mt2063_init()
1844 state->reg[MT2063_REG_PART_REV]); in mt2063_init()
1849 status = mt2063_read(state, MT2063_REG_RSVD_3B, in mt2063_init()
1850 &state->reg[MT2063_REG_RSVD_3B], 1); in mt2063_init()
1853 if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) { in mt2063_init()
1855 state->reg[MT2063_REG_PART_REV], in mt2063_init()
1856 state->reg[MT2063_REG_RSVD_3B]); in mt2063_init()
1863 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1); in mt2063_init()
1869 switch (state->reg[MT2063_REG_PART_REV]) { in mt2063_init()
1890 status = mt2063_write(state, reg, &val, 1); in mt2063_init()
1900 status = mt2063_read(state, in mt2063_init()
1902 &state-> in mt2063_init()
1904 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6; in mt2063_init()
1910 status = mt2063_read(state, in mt2063_init()
1912 &state->reg[MT2063_REG_FIFFC], 1); in mt2063_init()
1917 status = mt2063_read(state, in mt2063_init()
1919 state->reg, MT2063_REG_END_REGS); in mt2063_init()
1924 state->tuner_id = state->reg[MT2063_REG_PART_REV]; in mt2063_init()
1925 state->AS_Data.f_ref = MT2063_REF_FREQ; in mt2063_init()
1926 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) * in mt2063_init()
1927 ((u32) state->reg[MT2063_REG_FIFFC] + 640); in mt2063_init()
1928 state->AS_Data.f_if1_bw = MT2063_IF1_BW; in mt2063_init()
1929 state->AS_Data.f_out = 43750000UL; in mt2063_init()
1930 state->AS_Data.f_out_bw = 6750000UL; in mt2063_init()
1931 state->AS_Data.f_zif_bw = MT2063_ZIF_BW; in mt2063_init()
1932 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64; in mt2063_init()
1933 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE; in mt2063_init()
1934 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1; in mt2063_init()
1935 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2; in mt2063_init()
1936 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP; in mt2063_init()
1937 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center; in mt2063_init()
1938 state->AS_Data.f_LO1 = 2181000000UL; in mt2063_init()
1939 state->AS_Data.f_LO2 = 1486249786UL; in mt2063_init()
1940 state->f_IF1_actual = state->AS_Data.f_if1_Center; in mt2063_init()
1941 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual; in mt2063_init()
1942 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID; in mt2063_init()
1943 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID; in mt2063_init()
1944 state->num_regs = MT2063_REG_END_REGS; in mt2063_init()
1945 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH; in mt2063_init()
1946 state->ctfilt_sw = 0; in mt2063_init()
1948 state->CTFiltMax[0] = 69230000; in mt2063_init()
1949 state->CTFiltMax[1] = 105770000; in mt2063_init()
1950 state->CTFiltMax[2] = 140350000; in mt2063_init()
1951 state->CTFiltMax[3] = 177110000; in mt2063_init()
1952 state->CTFiltMax[4] = 212860000; in mt2063_init()
1953 state->CTFiltMax[5] = 241130000; in mt2063_init()
1954 state->CTFiltMax[6] = 274370000; in mt2063_init()
1955 state->CTFiltMax[7] = 309820000; in mt2063_init()
1956 state->CTFiltMax[8] = 342450000; in mt2063_init()
1957 state->CTFiltMax[9] = 378870000; in mt2063_init()
1958 state->CTFiltMax[10] = 416210000; in mt2063_init()
1959 state->CTFiltMax[11] = 456500000; in mt2063_init()
1960 state->CTFiltMax[12] = 495790000; in mt2063_init()
1961 state->CTFiltMax[13] = 534530000; in mt2063_init()
1962 state->CTFiltMax[14] = 572610000; in mt2063_init()
1963 state->CTFiltMax[15] = 598970000; in mt2063_init()
1964 state->CTFiltMax[16] = 635910000; in mt2063_init()
1965 state->CTFiltMax[17] = 672130000; in mt2063_init()
1966 state->CTFiltMax[18] = 714840000; in mt2063_init()
1967 state->CTFiltMax[19] = 739660000; in mt2063_init()
1968 state->CTFiltMax[20] = 770410000; in mt2063_init()
1969 state->CTFiltMax[21] = 814660000; in mt2063_init()
1970 state->CTFiltMax[22] = 846950000; in mt2063_init()
1971 state->CTFiltMax[23] = 867820000; in mt2063_init()
1972 state->CTFiltMax[24] = 915980000; in mt2063_init()
1973 state->CTFiltMax[25] = 947450000; in mt2063_init()
1974 state->CTFiltMax[26] = 983110000; in mt2063_init()
1975 state->CTFiltMax[27] = 1021630000; in mt2063_init()
1976 state->CTFiltMax[28] = 1061870000; in mt2063_init()
1977 state->CTFiltMax[29] = 1098330000; in mt2063_init()
1978 state->CTFiltMax[30] = 1138990000; in mt2063_init()
1985 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; in mt2063_init()
1986 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL, in mt2063_init()
1987 &state->reg[MT2063_REG_CTUNE_CTRL], 1); in mt2063_init()
1992 status = mt2063_read(state, MT2063_REG_FIFFC, in mt2063_init()
1993 &state->reg[MT2063_REG_FIFFC], 1); in mt2063_init()
1997 fcu_osc = state->reg[MT2063_REG_FIFFC]; in mt2063_init()
1999 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00; in mt2063_init()
2000 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL, in mt2063_init()
2001 &state->reg[MT2063_REG_CTUNE_CTRL], 1); in mt2063_init()
2007 state->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640); in mt2063_init()
2009 status = MT2063_SoftwareShutdown(state, 1); in mt2063_init()
2012 status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD); in mt2063_init()
2016 state->init = true; in mt2063_init()
2023 struct mt2063_state *state = fe->tuner_priv; in mt2063_get_status() local
2028 if (!state->init) in mt2063_get_status()
2032 status = mt2063_lockStatus(state); in mt2063_get_status()
2045 struct mt2063_state *state = fe->tuner_priv; in mt2063_release() local
2050 kfree(state); in mt2063_release()
2058 struct mt2063_state *state = fe->tuner_priv; in mt2063_set_analog_params() local
2068 if (!state->init) { in mt2063_set_analog_params()
2102 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */ in mt2063_set_analog_params()
2103 state->AS_Data.f_out = if_mid; in mt2063_set_analog_params()
2104 state->AS_Data.f_out_bw = ch_bw + 750000; in mt2063_set_analog_params()
2105 status = MT2063_SetReceiverMode(state, rcvr_mode); in mt2063_set_analog_params()
2112 status = MT2063_Tune(state, (params->frequency + (pict2chanb_vsb + (ch_bw / 2)))); in mt2063_set_analog_params()
2116 state->frequency = params->frequency; in mt2063_set_analog_params()
2132 struct mt2063_state *state = fe->tuner_priv; in mt2063_set_params() local
2140 if (!state->init) { in mt2063_set_params()
2174 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */ in mt2063_set_params()
2175 state->AS_Data.f_out = if_mid; in mt2063_set_params()
2176 state->AS_Data.f_out_bw = ch_bw + 750000; in mt2063_set_params()
2177 status = MT2063_SetReceiverMode(state, rcvr_mode); in mt2063_set_params()
2184 status = MT2063_Tune(state, (c->frequency + (pict2chanb_vsb + (ch_bw / 2)))); in mt2063_set_params()
2189 state->frequency = c->frequency; in mt2063_set_params()
2195 struct mt2063_state *state = fe->tuner_priv; in mt2063_get_if_frequency() local
2199 if (!state->init) in mt2063_get_if_frequency()
2202 *freq = state->AS_Data.f_out; in mt2063_get_if_frequency()
2211 struct mt2063_state *state = fe->tuner_priv; in mt2063_get_bandwidth() local
2215 if (!state->init) in mt2063_get_bandwidth()
2218 *bw = state->AS_Data.f_out_bw - 750000; in mt2063_get_bandwidth()
2247 struct mt2063_state *state = NULL; in mt2063_attach() local
2251 state = kzalloc(sizeof(struct mt2063_state), GFP_KERNEL); in mt2063_attach()
2252 if (!state) in mt2063_attach()
2255 state->config = config; in mt2063_attach()
2256 state->i2c = i2c; in mt2063_attach()
2257 state->frontend = fe; in mt2063_attach()
2258 state->reference = config->refclock / 1000; /* kHz */ in mt2063_attach()
2259 fe->tuner_priv = state; in mt2063_attach()
2274 struct mt2063_state *state = fe->tuner_priv;
2279 err = MT2063_SoftwareShutdown(state, 1);
2288 struct mt2063_state *state = fe->tuner_priv;
2293 err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);