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Searched refs:reg_base (Results 1 – 178 of 178) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_dp_reg.c32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap()
70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param()
73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param()
76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param()
[all …]
Dexynos_drm_dsi.c278 void __iomem *reg_base; member
365 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG); in exynos_dsi_reset()
452 writel(500, dsi->reg_base + driver_data->plltmr_reg); in exynos_dsi_set_pll()
474 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); in exynos_dsi_set_pll()
482 reg = readl(dsi->reg_base + DSIM_STATUS_REG); in exynos_dsi_set_pll()
512 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); in exynos_dsi_enable_clock()
522 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); in exynos_dsi_enable_clock()
537 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG); in exynos_dsi_set_phy_ctrl()
545 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG); in exynos_dsi_set_phy_ctrl()
564 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG); in exynos_dsi_set_phy_ctrl()
[all …]
Dexynos_dp_core.h159 void __iomem *reg_base; member
Dexynos_dp_core.c1262 dp->reg_base = devm_ioremap_resource(&pdev->dev, res); in exynos_dp_bind()
1263 if (IS_ERR(dp->reg_base)) in exynos_dp_bind()
1264 return PTR_ERR(dp->reg_base); in exynos_dp_bind()
/linux-4.1.27/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_lowlevel.c36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & in exynos_mipi_dsi_get_sw_reset_release()
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_read_interrupt_mask()
90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_set_interrupt_mask()
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
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Dexynos_mipi_dsi.c389 dsim->reg_base = devm_ioremap_resource(&pdev->dev, res); in exynos_mipi_dsi_probe()
390 if (IS_ERR(dsim->reg_base)) { in exynos_mipi_dsi_probe()
391 ret = PTR_ERR(dsim->reg_base); in exynos_mipi_dsi_probe()
/linux-4.1.27/drivers/gpio/
Dgpio-bcm-kona.c65 void __iomem *reg_base; member
86 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
89 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
90 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
102 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
104 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
118 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
120 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
128 void __iomem *reg_base; in bcm_kona_gpio_set() local
135 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set()
[all …]
Dgpio-sta2x11.c53 void __iomem *reg_base; member
329 chip->reg_base, handle_simple_irq); in gsta_alloc_irq_chip()
377 chip->reg_base = devm_ioremap_resource(&dev->dev, res); in gsta_probe()
378 if (IS_ERR(chip->reg_base)) in gsta_probe()
379 return PTR_ERR(chip->reg_base); in gsta_probe()
382 chip->regs[i] = chip->reg_base + i * 4096; in gsta_probe()
Dgpio-lynxpoint.c65 unsigned long reg_base; member
110 return lg->reg_base + reg + reg_offset; in lp_gpio_reg()
348 lg->reg_base = io_rc->start; in lp_gpio_probe()
351 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) { in lp_gpio_probe()
353 (unsigned int)lg->reg_base); in lp_gpio_probe()
Dgpio-intel-mid.c76 void __iomem *reg_base; member
93 return priv->reg_base + reg_type * nreg * 4 + reg * 4; in gpio_reg()
103 return priv->reg_base + reg_type * nreg * 4 + reg * 4; in gpio_reg_2bit()
393 priv->reg_base = pcim_iomap_table(pdev)[0]; in intel_gpio_probe()
Dgpio-dwapb.c95 void __iomem *reg_base = gpio->regs; in dwapb_read() local
97 return bgc->read_reg(reg_base + offset); in dwapb_read()
104 void __iomem *reg_base = gpio->regs; in dwapb_write() local
106 bgc->write_reg(reg_base + offset, val); in dwapb_write()
328 irq_gc->reg_base = gpio->regs; in dwapb_configure_irqs()
Dgpio-tb10x.c265 gc->reg_base = tb10x_gpio->base; in tb10x_gpio_probe()
Dgpio-tz1090.c484 gc->reg_base = bank->reg; in tz1090_gpio_bank_probe()
/linux-4.1.27/arch/sh/drivers/pci/
Dpci-sh7780.c103 addr = __raw_readl(hose->reg_base + SH4_PCIALR); in sh7780_pci_err_irq()
108 status = __raw_readw(hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
116 __raw_writew(cmd, hose->reg_base + PCI_STATUS); in sh7780_pci_err_irq()
122 status = __raw_readl(hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
130 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
135 status = __raw_readl(hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
143 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
157 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
172 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
180 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS); in sh7780_pci_setup_irqs()
[all …]
Dpci-sh4.h180 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
186 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
Dpcie-sh7786.h571 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
577 return __raw_readl(chan->reg_base + reg); in pci_read_reg()
Dpci-sh7751.c86 chan->reg_base = 0xfe200000; in sh7751_pci_init()
Dpcie-sh7786.c120 .reg_base = start, \
239 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()
/linux-4.1.27/drivers/video/fbdev/mmp/hw/
Dmmp_spi.c47 void *reg_base = in lcd_spi_write() local
51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
71 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
Dmmp_ctrl.c48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); in ctrl_handle_irq()
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); in ctrl_handle_irq()
335 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL); in ctrl_set_default()
337 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL); in ctrl_set_default()
343 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); in ctrl_set_default()
346 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA); in ctrl_set_default()
503 ctrl->reg_base = devm_ioremap_nocache(ctrl->dev, in mmphw_probe()
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Dmmp_ctrl.h1410 void *reg_base; member
1448 return path_to_ctrl(path)->reg_base; in ctrl_regs()
/linux-4.1.27/arch/powerpc/boot/
Duartlite.c29 static void * reg_base; variable
34 out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX); in uartlite_open()
42 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_putc()
43 out_be32(reg_base + ULITE_TX, c); in uartlite_putc()
50 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_getc()
51 return in_be32(reg_base + ULITE_RX); in uartlite_getc()
56 u32 reg = in_be32(reg_base + ULITE_STATUS); in uartlite_tstc()
65 n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base)); in uartlite_console_init()
66 if (n != sizeof(reg_base)) { in uartlite_console_init()
70 reg_base = (void *)reg_phys; in uartlite_console_init()
Dns16550.c29 static unsigned char *reg_base; variable
34 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
40 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
41 out_8(reg_base, c); in ns16550_putc()
46 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
47 return in_8(reg_base); in ns16550_getc()
52 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
60 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) in ns16550_console_init()
65 reg_base += reg_offset; in ns16550_console_init()
Dvirtex.c30 unsigned char *reg_base; in virtex_ns16550_console_init() local
35 if (dt_get_virtual_reg(devp, (void **)&reg_base, 1) < 1) in virtex_ns16550_console_init()
40 reg_base += reg_offset; in virtex_ns16550_console_init()
58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
61 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); in virtex_ns16550_console_init()
62 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
68 out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); in virtex_ns16550_console_init()
71 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
/linux-4.1.27/drivers/ide/
Dopti621.c29 static int reg_base; variable
40 inw(reg_base + 1); in write_reg()
41 inw(reg_base + 1); in write_reg()
42 outb(3, reg_base + 2); in write_reg()
43 outb(value, reg_base + reg); in write_reg()
44 outb(0x83, reg_base + 2); in write_reg()
56 inw(reg_base + 1); in read_reg()
57 inw(reg_base + 1); in read_reg()
58 outb(3, reg_base + 2); in read_reg()
59 ret = inb(reg_base + reg); in read_reg()
[all …]
/linux-4.1.27/drivers/spi/
Dspi-fsl-espi.c92 struct fsl_espi_reg *reg_base = mspi->reg_base; in fsl_espi_change_mode() local
93 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select]; in fsl_espi_change_mode()
94 __be32 __iomem *espi_mode = &reg_base->mode; in fsl_espi_change_mode()
203 struct fsl_espi_reg *reg_base = mspi->reg_base; in fsl_espi_cpu_bufs() local
208 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_espi_cpu_bufs()
212 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_espi_cpu_bufs()
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; in fsl_espi_bufs() local
238 mpc8xxx_spi_write_reg(&reg_base->command, in fsl_espi_bufs()
248 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_espi_bufs()
469 struct fsl_espi_reg *reg_base; in fsl_espi_setup() local
[all …]
Dspi-fsl-spi.c90 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
91 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
292 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
297 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
301 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
310 struct fsl_spi_reg *reg_base; in fsl_spi_bufs() local
315 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
348 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
425 struct fsl_spi_reg *reg_base; in fsl_spi_setup() local
441 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
Dspi-fsl-cpm.c81 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpm_bufs_start() local
101 mpc8xxx_spi_write_reg(&reg_base->command, SPCOM_STR); in fsl_spi_cpm_bufs_start()
108 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpm_bufs() local
153 mpc8xxx_spi_write_reg(&reg_base->mask, SPIE_RXB); in fsl_spi_cpm_bufs()
186 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpm_irq() local
198 mpc8xxx_spi_write_reg(&reg_base->event, events); in fsl_spi_cpm_irq()
Dspi-fsl-lib.h26 void *reg_base; member
/linux-4.1.27/drivers/clk/samsung/
Dclk-s5pv210-audss.c28 static void __iomem *reg_base; variable
47 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
57 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
77 reg_base = devm_ioremap_resource(&pdev->dev, res); in s5pv210_audss_clk_probe()
78 if (IS_ERR(reg_base)) { in s5pv210_audss_clk_probe()
80 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
122 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
133 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
137 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
139 "mout_i2s_audss", 0, reg_base + ASS_CLK_DIV, in s5pv210_audss_clk_probe()
[all …]
Dclk-exynos-audss.c30 static void __iomem *reg_base; variable
56 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
66 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
123 reg_base = devm_ioremap_resource(&pdev->dev, res); in exynos_audss_clk_probe()
124 if (IS_ERR(reg_base)) { in exynos_audss_clk_probe()
126 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
164 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
175 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
178 "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, in exynos_audss_clk_probe()
183 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
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Dclk-exynos5440.c28 static void __iomem *reg_base; variable
101 status = readl_relaxed(reg_base + 0xbc); in exynos5440_clk_restart_notify()
102 val = readl_relaxed(reg_base + 0xcc); in exynos5440_clk_restart_notify()
104 writel_relaxed(val, reg_base + 0xcc); in exynos5440_clk_restart_notify()
122 reg_base = of_iomap(np, 0); in exynos5440_clk_init()
123 if (!reg_base) { in exynos5440_clk_init()
129 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); in exynos5440_clk_init()
136 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); in exynos5440_clk_init()
137 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); in exynos5440_clk_init()
Dclk.c73 ctx->reg_base = base; in samsung_clk_init()
193 ctx->reg_base + list->offset, in samsung_clk_register_mux()
226 ctx->reg_base + list->offset, in samsung_clk_register_div()
232 ctx->reg_base + list->offset, list->shift, in samsung_clk_register_div()
263 list->flags, ctx->reg_base + list->offset, in samsung_clk_register_gate()
325 samsung_clk_save(reg_cache->reg_base, reg_cache->rdump, in samsung_clk_suspend()
335 samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump, in samsung_clk_resume()
344 static void samsung_clk_sleep_init(void __iomem *reg_base, in samsung_clk_sleep_init() argument
362 reg_cache->reg_base = reg_base; in samsung_clk_sleep_init()
368 static void samsung_clk_sleep_init(void __iomem *reg_base, in samsung_clk_sleep_init() argument
[all …]
Dclk-s3c2412.c37 static void __iomem *reg_base; variable
57 samsung_clk_save(reg_base, s3c2412_save, in s3c2412_clk_suspend()
65 samsung_clk_restore(reg_base, s3c2412_save, in s3c2412_clk_resume()
221 __raw_writel(0x00, reg_base + CLKSRC); in s3c2412_restart()
222 __raw_writel(0x533C2412, reg_base + SWRST); in s3c2412_restart()
261 reg_base = base; in s3c2412_common_clk_init()
264 reg_base = of_iomap(np, 0); in s3c2412_common_clk_init()
265 if (!reg_base) in s3c2412_common_clk_init()
269 ctx = samsung_clk_init(np, reg_base, NR_CLKS); in s3c2412_common_clk_init()
279 reg_base); in s3c2412_common_clk_init()
Dclk-s3c2410.c43 static void __iomem *reg_base; variable
64 samsung_clk_save(reg_base, s3c2410_save, in s3c2410_clk_suspend()
72 samsung_clk_restore(reg_base, s3c2410_save, in s3c2410_clk_resume()
370 reg_base = base; in s3c2410_common_clk_init()
373 reg_base = of_iomap(np, 0); in s3c2410_common_clk_init()
374 if (!reg_base) in s3c2410_common_clk_init()
378 ctx = samsung_clk_init(np, reg_base, NR_CLKS); in s3c2410_common_clk_init()
394 ARRAY_SIZE(s3c2410_plls), reg_base); in s3c2410_common_clk_init()
410 ARRAY_SIZE(s3c244x_common_plls), reg_base); in s3c2410_common_clk_init()
Dclk-exynos5410.c189 void __iomem *reg_base; in exynos5410_clk_init() local
191 reg_base = of_iomap(np, 0); in exynos5410_clk_init()
192 if (!reg_base) in exynos5410_clk_init()
195 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); in exynos5410_clk_init()
198 ARRAY_SIZE(exynos5410_plls), reg_base); in exynos5410_clk_init()
Dclk-s3c2443.c51 static void __iomem *reg_base; variable
77 samsung_clk_save(reg_base, s3c2443_save, in s3c2443_clk_suspend()
85 samsung_clk_restore(reg_base, s3c2443_save, in s3c2443_clk_resume()
362 __raw_writel(0x533c2443, reg_base + SWRST); in s3c2443_restart()
396 reg_base = base; in s3c2443_common_clk_init()
399 reg_base = of_iomap(np, 0); in s3c2443_common_clk_init()
400 if (!reg_base) in s3c2443_common_clk_init()
404 ctx = samsung_clk_init(np, reg_base, NR_CLKS); in s3c2443_common_clk_init()
415 ARRAY_SIZE(s3c2416_pll_clks), reg_base); in s3c2443_common_clk_init()
418 ARRAY_SIZE(s3c2443_pll_clks), reg_base); in s3c2443_common_clk_init()
Dclk-s3c64xx.c65 static void __iomem *reg_base; variable
100 samsung_clk_save(reg_base, s3c64xx_save_common, in s3c64xx_clk_suspend()
104 samsung_clk_save(reg_base, s3c64xx_save_soc, in s3c64xx_clk_suspend()
112 samsung_clk_restore(reg_base, s3c64xx_save_common, in s3c64xx_clk_resume()
116 samsung_clk_restore(reg_base, s3c64xx_save_soc, in s3c64xx_clk_resume()
465 reg_base = base; in s3c64xx_clk_init()
469 reg_base = of_iomap(np, 0); in s3c64xx_clk_init()
470 if (!reg_base) in s3c64xx_clk_init()
474 ctx = samsung_clk_init(np, reg_base, NR_CLKS); in s3c64xx_clk_init()
484 ARRAY_SIZE(s3c64xx_pll_clks), reg_base); in s3c64xx_clk_init()
Dclk-exynos4.c156 static void __iomem *reg_base; variable
300 pll_con = readl(reg_base + reg); in exynos4_clk_wait_for_pll()
306 pll_con = readl(reg_base + reg); in exynos4_clk_wait_for_pll()
312 samsung_clk_save(reg_base, exynos4_save_common, in exynos4_clk_suspend()
314 samsung_clk_save(reg_base, exynos4_save_pll, in exynos4_clk_suspend()
318 samsung_clk_save(reg_base, exynos4_save_soc, in exynos4_clk_suspend()
320 samsung_clk_restore(reg_base, src_mask_suspend_e4210, in exynos4_clk_suspend()
323 samsung_clk_save(reg_base, exynos4_save_soc, in exynos4_clk_suspend()
327 samsung_clk_restore(reg_base, src_mask_suspend, in exynos4_clk_suspend()
335 samsung_clk_restore(reg_base, exynos4_save_pll, in exynos4_clk_resume()
[all …]
Dclk-s5pv210.c86 static void __iomem *reg_base; variable
139 samsung_clk_save(reg_base, s5pv210_clk_dump, in s5pv210_clk_suspend()
146 samsung_clk_restore(reg_base, s5pv210_clk_dump, in s5pv210_clk_resume()
788 ctx = samsung_clk_init(np, reg_base, NR_CLKS); in __s5pv210_clk_init()
799 ARRAY_SIZE(s5p6442_pll_clks), reg_base); in __s5pv210_clk_init()
810 ARRAY_SIZE(s5pv210_pll_clks), reg_base); in __s5pv210_clk_init()
842 reg_base = of_iomap(np, 0); in s5pv210_clk_dt_init()
843 if (!reg_base) in s5pv210_clk_dt_init()
852 reg_base = of_iomap(np, 0); in s5p6442_clk_dt_init()
853 if (!reg_base) in s5p6442_clk_dt_init()
Dclk-exynos5250.c112 static void __iomem *reg_base; variable
177 samsung_clk_save(reg_base, exynos5250_save, in exynos5250_clk_suspend()
185 samsung_clk_restore(reg_base, exynos5250_save, in exynos5250_clk_resume()
763 reg_base = of_iomap(np, 0); in exynos5250_clk_init()
764 if (!reg_base) in exynos5250_clk_init()
770 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); in exynos5250_clk_init()
789 reg_base); in exynos5250_clk_init()
809 __raw_writel(tmp, reg_base + PWR_CTRL1); in exynos5250_clk_init()
819 __raw_writel(tmp, reg_base + PWR_CTRL2); in exynos5250_clk_init()
Dclk-exynos5420.c152 static void __iomem *reg_base; variable
281 samsung_clk_save(reg_base, exynos5x_save, in exynos5420_clk_suspend()
285 samsung_clk_save(reg_base, exynos5800_save, in exynos5420_clk_suspend()
288 samsung_clk_restore(reg_base, exynos5420_set_clksrc, in exynos5420_clk_suspend()
296 samsung_clk_restore(reg_base, exynos5x_save, in exynos5420_clk_resume()
300 samsung_clk_restore(reg_base, exynos5800_save, in exynos5420_clk_resume()
1262 reg_base = of_iomap(np, 0); in exynos5x_clk_init()
1263 if (!reg_base) in exynos5x_clk_init()
1271 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); in exynos5x_clk_init()
1285 reg_base); in exynos5x_clk_init()
Dclk-pll.h105 const char *pname, const void __iomem *reg_base,
Dclk.h27 void __iomem *reg_base; member
325 void __iomem *reg_base; member
Dclk-exynos3250.c738 static void __init exynos3_core_down_clock(void __iomem *reg_base) in exynos3_core_down_clock() argument
750 __raw_writel(tmp, reg_base + PWR_CTRL1); in exynos3_core_down_clock()
756 __raw_writel(0x0, reg_base + PWR_CTRL2); in exynos3_core_down_clock()
783 exynos3_core_down_clock(ctx->reg_base); in exynos3250_cmu_init()
Dclk-pll.c893 const void __iomem *reg_base; member
906 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3); in samsung_pll2550x_recalc_rate()
925 const char *pname, const void __iomem *reg_base, in samsung_clk_register_pll2550x() argument
945 pll->reg_base = reg_base; in samsung_clk_register_pll2550x()
/linux-4.1.27/arch/arm/mach-rockchip/
Drockchip.c39 void __iomem *reg_base; in rockchip_timer_init() local
46 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K); in rockchip_timer_init()
47 if (reg_base) { in rockchip_timer_init()
48 writel(0, reg_base + 0x30); in rockchip_timer_init()
49 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
50 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
51 writel(1, reg_base + 0x30); in rockchip_timer_init()
53 iounmap(reg_base); in rockchip_timer_init()
/linux-4.1.27/drivers/input/serio/
Dsun4i-ps2.c84 void __iomem *reg_base; member
106 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
107 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
117 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
124 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
129 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
153 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
160 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/linux-4.1.27/drivers/ata/
Dahci_sunxi.c94 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) in ahci_sunxi_phy_init() argument
100 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init()
103 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
107 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()
110 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()
111 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
112 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
114 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init()
118 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init()
[all …]
Dsata_dwc_460ex.c149 u8 __iomem *reg_base; member
1210 hsdev->reg_base = base; in sata_dwc_probe()
1300 iounmap(hsdev->reg_base); in sata_dwc_remove()
/linux-4.1.27/drivers/irqchip/
Dirq-digicolor.c58 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
64 gc->reg_base = reg_base; in digicolor_set_gc()
75 static void __iomem *reg_base; in digicolor_of_init() local
80 reg_base = of_iomap(node, 0); in digicolor_of_init()
81 if (!reg_base) { in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
88 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
114 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
Dirq-orion.c42 u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & in orion_handle_irq()
87 gc->reg_base = ioremap(r.start, resource_size(&r)); in orion_irq_init()
88 if (!gc->reg_base) in orion_irq_init()
96 writel(0, gc->reg_base + ORION_IRQ_MASK); in orion_irq_init()
115 u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & in orion_bridge_irq_handler()
184 gc->reg_base = ioremap(r.start, resource_size(&r)); in orion_bridge_irq_init()
185 if (!gc->reg_base) { in orion_bridge_irq_init()
198 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); in orion_bridge_irq_init()
199 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE); in orion_bridge_irq_init()
Dirq-tb10x.c114 void __iomem *reg_base; in of_tb10x_init_irq() local
128 reg_base = ioremap(mem.start, resource_size(&mem)); in of_tb10x_init_irq()
129 if (!reg_base) { in of_tb10x_init_irq()
155 gc->reg_base = reg_base; in of_tb10x_init_irq()
190 iounmap(reg_base); in of_tb10x_init_irq()
Dirq-atmel-aic-common.c222 void __iomem *reg_base; in aic_common_of_init() local
229 reg_base = of_iomap(node, 0); in aic_common_of_init()
230 if (!reg_base) in aic_common_of_init()
255 gc->reg_base = reg_base; in aic_common_of_init()
277 iounmap(reg_base); in aic_common_of_init()
Dirq-dw-apb-ictl.c40 stat = readl_relaxed(gc->reg_base + in dw_apb_ictl_handler()
60 writel_relaxed(~0, gc->reg_base + ct->regs.enable); in dw_apb_ictl_resume()
61 writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); in dw_apb_ictl_resume()
142 gc->reg_base = iobase; in dw_apb_ictl_init()
Dirq-nvic.c92 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
103 writel_relaxed(~0, gc->reg_base + NVIC_ICER); in nvic_of_init()
Dirq-zevio.c50 readl(gc->reg_base + regs->ack); in zevio_irq_ack()
111 gc->reg_base = zevio_irq_io; in zevio_of_init()
Dirq-sunxi-nmi.c154 gc->reg_base = of_iomap(node, 0); in sunxi_sc_nmi_irq_init()
155 if (!gc->reg_base) { in sunxi_sc_nmi_irq_init()
Dirq-s3c24xx.c1251 void __iomem *reg_base; in s3c_init_intc_of() local
1254 reg_base = of_iomap(np, 0); in s3c_init_intc_of()
1255 if (!reg_base) { in s3c_init_intc_of()
1285 intc->reg_pending = reg_base + ctrl->offset; in s3c_init_intc_of()
1286 intc->reg_mask = reg_base + ctrl->offset + 0x4; in s3c_init_intc_of()
1298 intc->reg_pending = reg_base + ctrl->offset; in s3c_init_intc_of()
1299 intc->reg_mask = reg_base + ctrl->offset + 0x08; in s3c_init_intc_of()
1300 intc->reg_intpnd = reg_base + ctrl->offset + 0x10; in s3c_init_intc_of()
Dirq-moxart.c100 gc->reg_base = intc.base; in moxart_of_intc_init()
Dirq-sirfsoc.c43 gc->reg_base = base; in sirfsoc_alloc_gc()
Dirq-imgpdc.c406 gc->reg_base = priv->pdc_base; in pdc_intc_probe()
420 gc->reg_base = priv->pdc_base; in pdc_intc_probe()
Dirq-brcmstb-l2.c179 gc->reg_base = data->base; in brcmstb_l2_intc_of_init()
Dirq-omap-intc.c208 gc->reg_base = base; in omap_alloc_gc_of()
Dirq-bcm7120-l2.c277 gc->reg_base = data->pair_base[idx]; in bcm7120_l2_intc_probe()
/linux-4.1.27/drivers/ntb/
Dntb_hw.c547 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6); in bwd_recover_link()
548 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4); in bwd_recover_link()
549 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4); in bwd_recover_link()
550 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6); in bwd_recover_link()
556 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET); in bwd_recover_link()
559 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET); in bwd_recover_link()
562 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET); in bwd_recover_link()
565 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET); in bwd_recover_link()
568 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET); in bwd_recover_link()
571 writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET); in bwd_recover_link()
[all …]
Dntb_hw.h119 void __iomem *reg_base; member
/linux-4.1.27/arch/sparc/kernel/
Dsbus.c211 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq() local
221 imap += reg_base; in sbus_build_irq()
236 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_build_irq()
239 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_build_irq()
242 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_build_irq()
246 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_build_irq()
273 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler() local
278 afsr_reg = reg_base + SYSIO_UE_AFSR; in sysio_ue_handler()
279 afar_reg = reg_base + SYSIO_UE_AFAR; in sysio_ue_handler()
347 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler() local
[all …]
Dprom_irqtrans.c651 unsigned long reg_base = (unsigned long) _data; in sbus_of_build_irq() local
672 imap += reg_base; in sbus_of_build_irq()
685 iclr = reg_base + SYSIO_ICLR_SLOT0; in sbus_of_build_irq()
688 iclr = reg_base + SYSIO_ICLR_SLOT1; in sbus_of_build_irq()
691 iclr = reg_base + SYSIO_ICLR_SLOT2; in sbus_of_build_irq()
695 iclr = reg_base + SYSIO_ICLR_SLOT3; in sbus_of_build_irq()
/linux-4.1.27/drivers/i2c/busses/
Di2c-mv64xxx.c126 void __iomem *reg_base; member
205 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); in mv64xxx_i2c_hw_init()
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); in mv64xxx_i2c_hw_init()
207 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init()
209 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init()
213 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); in mv64xxx_i2c_hw_init()
215 drv_data->reg_base + drv_data->reg_offsets.clock); in mv64xxx_i2c_hw_init()
216 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); in mv64xxx_i2c_hw_init()
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); in mv64xxx_i2c_hw_init()
219 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_hw_init()
[all …]
Di2c-pca-platform.c30 void __iomem *reg_base; member
45 return ioread8(i2c->reg_base + reg); in i2c_pca_pf_readbyte8()
51 return ioread8(i2c->reg_base + reg * 2); in i2c_pca_pf_readbyte16()
57 return ioread8(i2c->reg_base + reg * 4); in i2c_pca_pf_readbyte32()
63 iowrite8(val, i2c->reg_base + reg); in i2c_pca_pf_writebyte8()
69 iowrite8(val, i2c->reg_base + reg * 2); in i2c_pca_pf_writebyte16()
75 iowrite8(val, i2c->reg_base + reg * 4); in i2c_pca_pf_writebyte32()
164 i2c->reg_base = ioremap(res->start, resource_size(res)); in i2c_pca_pf_probe()
165 if (!i2c->reg_base) { in i2c_pca_pf_probe()
249 iounmap(i2c->reg_base); in i2c_pca_pf_probe()
[all …]
Di2c-pxa.c146 void __iomem *reg_base; member
1190 i2c->reg_base = ioremap(res->start, resource_size(res)); in i2c_pxa_probe()
1191 if (!i2c->reg_base) { in i2c_pxa_probe()
1196 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; in i2c_pxa_probe()
1197 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; in i2c_pxa_probe()
1198 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; in i2c_pxa_probe()
1199 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; in i2c_pxa_probe()
1201 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; in i2c_pxa_probe()
1271 iounmap(i2c->reg_base); in i2c_pxa_probe()
1292 iounmap(i2c->reg_base); in i2c_pxa_remove()
Di2c-sibyte.c29 void *reg_base; /* CSR base */ member
33 #define SMB_CSR(a,r) ((long)(a->reg_base + r))
/linux-4.1.27/drivers/clk/mvebu/
Dclk-cpu.c39 void __iomem *reg_base; member
55 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
84 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
87 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_off_set_rate()
91 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
93 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_off_set_rate()
96 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
98 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_off_set_rate()
103 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_off_set_rate()
125 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); in clk_cpu_on_set_rate()
[all …]
/linux-4.1.27/drivers/video/fbdev/
Dpxa168fb.c291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider()
301 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
338 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start()
373 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; in set_dumb_panel_control()
386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control()
399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions()
425 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
[all …]
Dgoldfishfb.c46 void __iomem *reg_base; member
63 status = readl(fb->reg_base + FB_INT_STATUS); in goldfish_fb_interrupt()
130 writel(fb->rotation, fb->reg_base + FB_SET_ROTATION); in goldfish_fb_set_par()
146 fb->reg_base + FB_SET_BASE); in goldfish_fb_pan_display()
160 writel(1, fb->reg_base + FB_SET_BLANK); in goldfish_fb_blank()
163 writel(0, fb->reg_base + FB_SET_BLANK); in goldfish_fb_blank()
205 fb->reg_base = ioremap(r->start, PAGE_SIZE); in goldfish_fb_probe()
206 if (fb->reg_base == NULL) { in goldfish_fb_probe()
217 width = readl(fb->reg_base + FB_GET_WIDTH); in goldfish_fb_probe()
218 height = readl(fb->reg_base + FB_GET_HEIGHT); in goldfish_fb_probe()
[all …]
Dmx3fb.c242 void __iomem *reg_base; member
348 return __raw_readl(mx3fb->reg_base + reg); in mx3fb_read_reg()
353 __raw_writel(value, mx3fb->reg_base + reg); in mx3fb_write_reg()
1580 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); in mx3fb_probe()
1581 if (!mx3fb->reg_base) { in mx3fb_probe()
1586 pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base); in mx3fb_probe()
1620 iounmap(mx3fb->reg_base); in mx3fb_probe()
1641 iounmap(mx3fb->reg_base); in mx3fb_remove()
Dsm501fb.c1480 static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base) in sm501_init_cursor() argument
1492 par->cursor_regs = info->regs + reg_base; in sm501_init_cursor()
/linux-4.1.27/drivers/clk/rockchip/
Dsoftrst.c24 void __iomem *reg_base; member
42 softrst->reg_base + (bank * 4)); in rockchip_softrst_assert()
49 reg = readl(softrst->reg_base + (bank * 4)); in rockchip_softrst_assert()
50 writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); in rockchip_softrst_assert()
68 writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); in rockchip_softrst_deassert()
75 reg = readl(softrst->reg_base + (bank * 4)); in rockchip_softrst_deassert()
76 writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); in rockchip_softrst_deassert()
102 softrst->reg_base = base; in rockchip_register_softrst()
Dclk-pll.c38 void __iomem *reg_base; member
137 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_recalc_rate()
144 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_recalc_rate()
147 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_recalc_rate()
199 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_rate()
206 pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_set_rate()
210 pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_set_rate()
213 pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_set_rate()
217 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_rate()
239 pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_enable()
[all …]
Dclk.c155 static void __iomem *reg_base; variable
163 reg_base = base; in rockchip_clk_init()
198 reg_base, list->con_offset, grf_lock_offset, in rockchip_clk_register_plls()
228 flags, reg_base + list->muxdiv_offset, in rockchip_clk_register_branches()
236 flags, reg_base + list->muxdiv_offset, in rockchip_clk_register_branches()
243 reg_base + list->muxdiv_offset, in rockchip_clk_register_branches()
250 reg_base, list->muxdiv_offset, list->div_flags, in rockchip_clk_register_branches()
259 reg_base + list->gate_offset, in rockchip_clk_register_branches()
265 reg_base, list->muxdiv_offset, list->mux_shift, in rockchip_clk_register_branches()
276 reg_base + list->muxdiv_offset, in rockchip_clk_register_branches()
[all …]
Dclk-cpu.c61 void __iomem *reg_base; member
93 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_recalc_rate()
118 writel(clksel->val , cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
161 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_pre_rate_change()
165 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_pre_rate_change()
201 cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_post_rate_change()
237 int nrates, void __iomem *reg_base, spinlock_t *lock) in rockchip_clk_register_cpuclk() argument
266 cpuclk->reg_base = reg_base; in rockchip_clk_register_cpuclk()
Dclk-rk3288.c842 static void rk3288_clk_sleep_init(void __iomem *reg_base) in rk3288_clk_sleep_init() argument
844 rk3288_cru_base = reg_base; in rk3288_clk_sleep_init()
849 static void rk3288_clk_sleep_init(void __iomem *reg_base) {} in rk3288_clk_sleep_init() argument
854 void __iomem *reg_base; in rk3288_clk_init() local
857 reg_base = of_iomap(np, 0); in rk3288_clk_init()
858 if (!reg_base) { in rk3288_clk_init()
863 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); in rk3288_clk_init()
904 rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0), in rk3288_clk_init()
908 rk3288_clk_sleep_init(reg_base); in rk3288_clk_init()
Dclk-rk3188.c718 void __iomem *reg_base; in rk3188_common_clk_init() local
721 reg_base = of_iomap(np, 0); in rk3188_common_clk_init()
722 if (!reg_base) { in rk3188_common_clk_init()
727 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); in rk3188_common_clk_init()
745 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), in rk3188_common_clk_init()
Dclk.h179 int nrates, void __iomem *reg_base, spinlock_t *lock);
/linux-4.1.27/drivers/dma/ioat/
Ddma.h40 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
76 void __iomem *reg_base; member
98 void __iomem *reg_base; member
228 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); in ioat_chansts_32()
229 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); in ioat_chansts_32()
245 status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); in ioat_chansts()
260 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); in ioat_start()
270 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat_chanerr()
277 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); in ioat_suspend()
284 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); in ioat_reset()
[all …]
Ddma.c63 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); in ioat_dma_do_interrupt()
69 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); in ioat_dma_do_interrupt()
73 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); in ioat_dma_do_interrupt()
80 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); in ioat_dma_do_interrupt()
107 chan->reg_base = device->reg_base + (0x80 * (idx + 1)); in ioat_init_channel()
133 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); in ioat1_enumerate_channels()
140 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); in ioat1_enumerate_channels()
172 void __iomem *reg_base = ioat->base.reg_base; in __ioat1_dma_memcpy_issue_pending() local
177 writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); in __ioat1_dma_memcpy_issue_pending()
198 void __iomem *reg_base = chan->reg_base; in ioat1_reset_channel() local
[all …]
Ddma_v2.c58 writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); in __ioat2_issue_pending()
194 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); in ioat2_cleanup_event()
312 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_timer_event()
357 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_reset_hw()
358 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_reset_hw()
376 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); in ioat2_enumerate_channels()
383 xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET); in ioat2_enumerate_channels()
528 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); in ioat2_alloc_chan_resources()
539 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); in ioat2_alloc_chan_resources()
541 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); in ioat2_alloc_chan_resources()
[all …]
Ddma_v2.h149 chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); in ioat2_set_chainaddr()
151 chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); in ioat2_set_chainaddr()
Ddma_v3.c444 chan->device->reg_base + IOAT_INTRDELAY_OFFSET); in __cleanup()
458 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_cleanup()
477 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); in ioat3_cleanup_event()
508 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_eh()
555 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_eh()
607 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_timer_event()
1542 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_reset_hw()
1543 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_reset_hw()
1594 errmask = readl(chan->reg_base + in ioat3_intr_quirk()
1598 writel(errmask, chan->reg_base + in ioat3_intr_quirk()
[all …]
Dpci.c147 d->reg_base = iobase; in alloc_ioatdma()
187 device->version = readb(device->reg_base + IOAT_VER_OFFSET); in ioat_pci_probe()
/linux-4.1.27/drivers/watchdog/
Ds3c2410_wdt.c126 void __iomem *reg_base; member
242 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); in s3c2410wdt_keepalive()
252 wtcon = readl(wdt->reg_base + S3C2410_WTCON); in __s3c2410wdt_stop()
254 writel(wtcon, wdt->reg_base + S3C2410_WTCON); in __s3c2410wdt_stop()
277 wtcon = readl(wdt->reg_base + S3C2410_WTCON); in s3c2410wdt_start()
291 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); in s3c2410wdt_start()
292 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); in s3c2410wdt_start()
293 writel(wtcon, wdt->reg_base + S3C2410_WTCON); in s3c2410wdt_start()
301 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; in s3c2410wdt_is_running()
342 wtcon = readl(wdt->reg_base + S3C2410_WTCON); in s3c2410wdt_set_heartbeat()
[all …]
/linux-4.1.27/drivers/input/keyboard/
Dnspire-keypad.c35 void __iomem *reg_base; member
64 int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask; in nspire_keypad_irq()
68 memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state)); in nspire_keypad_irq()
94 writel(0x3, keypad->reg_base + KEYPAD_INT); in nspire_keypad_irq()
118 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); in nspire_keypad_chip_init()
121 writel(val, keypad->reg_base + KEYPAD_CNTL); in nspire_keypad_chip_init()
125 writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_chip_init()
129 writel(0, keypad->reg_base + KEYPAD_UNKNOWN_INT); in nspire_keypad_chip_init()
131 writel(~0, keypad->reg_base + KEYPAD_UNKNOWN_INT_STS); in nspire_keypad_chip_init()
208 keypad->reg_base = devm_ioremap_resource(&pdev->dev, res); in nspire_keypad_probe()
[all …]
Dnomadik-ske-keypad.c65 void __iomem *reg_base; member
81 ret = readl(keypad->reg_base + addr); in ske_keypad_set_bits()
84 writel(ret, keypad->reg_base + addr); in ske_keypad_set_bits()
100 while ((readl(keypad->reg_base + SKE_RIS) != 0x00000000) && timeout--) in ske_keypad_chip_init()
112 value = readl(keypad->reg_base + SKE_DBCR); in ske_keypad_chip_init()
115 writel(value, keypad->reg_base + SKE_DBCR); in ske_keypad_chip_init()
156 ske_ris = readl(keypad->reg_base + SKE_RIS); in ske_keypad_report()
180 ske_asr = readl(keypad->reg_base + SKE_ASR0 + (4 * i)); in ske_keypad_read_data()
207 while ((readl(keypad->reg_base + SKE_CR) & SKE_KPASON) && --timeout) in ske_keypad_irq()
214 while ((readl(keypad->reg_base + SKE_RIS)) && --timeout) in ske_keypad_irq()
[all …]
/linux-4.1.27/drivers/clocksource/
Dexynos_mct.c80 static void __iomem *reg_base; variable
97 writel_relaxed(value, reg_base + offset); in exynos4_mct_write()
147 if (readl_relaxed(reg_base + stat_addr) & mask) { in exynos4_mct_write()
148 writel_relaxed(mask, reg_base + stat_addr); in exynos4_mct_write()
160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_frc_start()
178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_read_count_64()
182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_read_count_64()
183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_read_count_64()
199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_read_count_32()
253 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_stop()
[all …]
/linux-4.1.27/drivers/usb/musb/
Dam35x.c99 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); in am35x_musb_enable()
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
119 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); in am35x_musb_disable()
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
219 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); in am35x_musb_interrupt()
[all …]
Dda8xx.c149 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable() local
156 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); in da8xx_musb_enable()
159 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, in da8xx_musb_enable()
168 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_disable() local
170 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, in da8xx_musb_disable()
174 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_disable()
291 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt() local
305 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); in da8xx_musb_interrupt()
309 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); in da8xx_musb_interrupt()
325 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); in da8xx_musb_interrupt()
[all …]
Dmusb_dsps.c218 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
226 dsps_writel(reg_base, wrp->epintr_set, epmask); in dsps_musb_enable()
227 dsps_writel(reg_base, wrp->coreintr_set, coremask); in dsps_musb_enable()
245 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
247 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); in dsps_musb_disable()
248 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
307 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
318 epintr = dsps_readl(reg_base, wrp->epintr_status); in dsps_interrupt()
323 dsps_writel(reg_base, wrp->epintr_status, epintr); in dsps_interrupt()
326 usbintr = dsps_readl(reg_base, wrp->coreintr_status); in dsps_interrupt()
[all …]
/linux-4.1.27/drivers/dma/
Dmmp_tdma.c124 void __iomem *reg_base; member
145 writel(phys, tdmac->reg_base + TDNDPR); in mmp_tdma_chan_set_desc()
146 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, in mmp_tdma_chan_set_desc()
147 tdmac->reg_base + TDCR); in mmp_tdma_chan_set_desc()
153 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); in mmp_tdma_enable_irq()
155 writel(0, tdmac->reg_base + TDIMR); in mmp_tdma_enable_irq()
161 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, in mmp_tdma_enable_chan()
162 tdmac->reg_base + TDCR); in mmp_tdma_enable_chan()
171 tdcr = readl(tdmac->reg_base + TDCR); in mmp_tdma_disable_chan()
174 writel(tdcr, tdmac->reg_base + TDCR); in mmp_tdma_disable_chan()
[all …]
/linux-4.1.27/drivers/net/can/sja1000/
Dsja1000_isa.c82 return readb(priv->reg_base + reg); in sja1000_isa_mem_read_reg()
88 writeb(val, priv->reg_base + reg); in sja1000_isa_mem_write_reg()
93 return inb((unsigned long)priv->reg_base + reg); in sja1000_isa_port_read_reg()
99 outb(val, (unsigned long)priv->reg_base + reg); in sja1000_isa_port_write_reg()
105 unsigned long flags, base = (unsigned long)priv->reg_base; in sja1000_isa_port_read_reg_indirect()
119 unsigned long flags, base = (unsigned long)priv->reg_base; in sja1000_isa_port_write_reg_indirect()
169 priv->reg_base = base; in sja1000_isa_probe()
174 priv->reg_base = (void __iomem *)port[idx]; in sja1000_isa_probe()
220 DRV_NAME, priv->reg_base, dev->irq); in sja1000_isa_probe()
244 iounmap(priv->reg_base); in sja1000_isa_remove()
Dsja1000_platform.c45 return ioread8(priv->reg_base + reg); in sp_read_reg8()
50 iowrite8(val, priv->reg_base + reg); in sp_write_reg8()
55 return ioread8(priv->reg_base + reg * 2); in sp_read_reg16()
60 iowrite8(val, priv->reg_base + reg * 2); in sp_write_reg16()
65 return ioread8(priv->reg_base + reg * 4); in sp_read_reg32()
70 iowrite8(val, priv->reg_base + reg * 4); in sp_write_reg32()
209 priv->reg_base = addr; in sp_probe()
227 DRV_NAME, priv->reg_base, dev->irq); in sp_probe()
Dpeak_pci.c150 void __iomem *reg_base; /* first channel base address */ member
405 int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; in peak_pciec_write_reg()
460 card->reg_base = priv->reg_base; in peak_pciec_probe()
533 return readb(priv->reg_base + (port << 2)); in peak_pci_read_reg()
539 writeb(val, priv->reg_base + (port << 2)); in peak_pci_write_reg()
558 void __iomem *cfg_base, *reg_base; in peak_pci_probe() local
597 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); in peak_pci_probe()
598 if (!reg_base) { in peak_pci_probe()
627 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; in peak_pci_probe()
678 dev->name, priv->reg_base, chan->cfg_base, dev->irq); in peak_pci_probe()
[all …]
Dems_pci.c125 return readb(priv->reg_base + (port * 4)); in ems_pci_v1_read_reg()
131 writeb(val, priv->reg_base + (port * 4)); in ems_pci_v1_write_reg()
145 return readb(priv->reg_base + port); in ems_pci_v2_read_reg()
151 writeb(val, priv->reg_base + port); in ems_pci_v2_write_reg()
307 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET in ems_pci_add_card()
349 i + 1, priv->reg_base, dev->irq); in ems_pci_add_card()
Dtscan1.c81 return inb((unsigned long)priv->reg_base + reg); in tscan1_read()
87 outb(val, (unsigned long)priv->reg_base + reg); in tscan1_write()
153 priv->reg_base = (void __iomem *)sja1000_base; in tscan1_probe()
186 sja1000_base = (unsigned long)priv->reg_base; in tscan1_remove()
Dkvaser_pci.c120 return ioread8(priv->reg_base + port); in kvaser_pci_read_reg()
126 iowrite8(val, priv->reg_base + port); in kvaser_pci_write_reg()
201 pci_iounmap(board->pci_dev, priv->reg_base); in kvaser_pci_del_chan()
253 priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES; in kvaser_pci_add_chan()
267 priv->reg_base, board->conf_addr, dev->irq); in kvaser_pci_add_chan()
Dems_pcmcia.c81 return readb(priv->reg_base + port); in ems_pcmcia_read_reg()
87 writeb(val, priv->reg_base + port); in ems_pcmcia_write_reg()
218 priv->reg_base = card->base_addr + EMS_PCMCIA_CAN_BASE_OFFSET + in ems_pcmcia_add_card()
241 i, priv->reg_base, dev->irq); in ems_pcmcia_add_card()
Dplx_pci.c348 return ioread8(priv->reg_base + port); in plx_pci_read_reg()
353 iowrite8(val, priv->reg_base + port); in plx_pci_write_reg()
478 if (priv->reg_base) in plx_pci_del_card()
479 pci_iounmap(pdev, priv->reg_base); in plx_pci_del_card()
579 priv->reg_base = addr + cm->offset; in plx_pci_add_card()
603 "registered as %s\n", i + 1, priv->reg_base, in plx_pci_add_card()
Dpeak_pcmcia.c187 return ioread8(priv->reg_base + port); in pcan_read_canreg()
196 int c = (priv->reg_base - card->ioport_addr) / PCC_CHAN_SIZE; in pcan_write_canreg()
214 iowrite8(v, priv->reg_base + port); in pcan_write_canreg()
557 priv->reg_base = card->ioport_addr + PCC_CHAN_OFF(i); in pcan_add_channels()
593 netdev->name, i, priv->reg_base, pdev->irq); in pcan_add_channels()
Dsja1000.h166 void __iomem *reg_base; /* ioremap'ed address to registers */ member
Dsja1000.c108 if (priv->reg_base && sja1000_is_absent(priv)) { in sja1000_probe_chip()
/linux-4.1.27/drivers/net/can/cc770/
Dcc770_isa.c122 return readb(priv->reg_base + reg); in cc770_isa_mem_read_reg()
128 writeb(val, priv->reg_base + reg); in cc770_isa_mem_write_reg()
133 return inb((unsigned long)priv->reg_base + reg); in cc770_isa_port_read_reg()
139 outb(val, (unsigned long)priv->reg_base + reg); in cc770_isa_port_write_reg()
145 unsigned long base = (unsigned long)priv->reg_base; in cc770_isa_port_read_reg_indirect()
160 unsigned long base = (unsigned long)priv->reg_base; in cc770_isa_port_write_reg_indirect()
211 priv->reg_base = base; in cc770_isa_probe()
216 priv->reg_base = (void __iomem *)port[idx]; in cc770_isa_probe()
279 priv->reg_base, dev->irq); in cc770_isa_probe()
303 iounmap(priv->reg_base); in cc770_isa_remove()
Dcc770_platform.c69 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg()
75 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg()
202 priv->reg_base = base; in cc770_platform_probe()
216 priv->reg_base, dev->irq, priv->can.clock.freq, in cc770_platform_probe()
248 iounmap(priv->reg_base); in cc770_platform_remove()
Dcc770.h188 void __iomem *reg_base; /* ioremap'ed address to registers */ member
Dcc770.c312 priv->reg_base); in cc770_probe_chip()
324 priv->reg_base); in cc770_probe_chip()
/linux-4.1.27/drivers/staging/media/davinci_vpfe/
Ddm365_ipipe_hw.c75 u32 reg_base; in rsz_set_rsz_regs() local
85 reg_base = RSZ_EN_A; in rsz_set_rsz_regs()
89 reg_base = RSZ_EN_B; in rsz_set_rsz_regs()
94 regw_rsz(rsz_base, params->oper_mode, reg_base + RSZ_MODE); in rsz_set_rsz_regs()
97 regw_rsz(rsz_base, val, reg_base + RSZ_420); in rsz_set_rsz_regs()
100 reg_base + RSZ_I_VPS); in rsz_set_rsz_regs()
102 reg_base + RSZ_I_HPS); in rsz_set_rsz_regs()
104 reg_base + RSZ_O_VSZ); in rsz_set_rsz_regs()
106 reg_base + RSZ_O_HSZ); in rsz_set_rsz_regs()
108 reg_base + RSZ_V_PHS_Y); in rsz_set_rsz_regs()
[all …]
/linux-4.1.27/drivers/misc/eeprom/
Dsunxi_sid.c39 void __iomem *reg_base; member
56 sid_key = ioread32be(sid_data->reg_base + round_down(offset, 4)); in sunxi_sid_read_byte()
118 sid_data->reg_base = devm_ioremap_resource(&pdev->dev, res); in sunxi_sid_probe()
119 if (IS_ERR(sid_data->reg_base)) in sunxi_sid_probe()
120 return PTR_ERR(sid_data->reg_base); in sunxi_sid_probe()
/linux-4.1.27/drivers/staging/goldfish/
Dgoldfish_audio.c37 char __iomem *reg_base; member
63 #define AUDIO_READ(data, addr) (readl(data->reg_base + addr))
64 #define AUDIO_WRITE(data, addr, x) (writel(x, data->reg_base + addr))
66 (gf_write64((u64)(x), data->reg_base + addr, data->reg_base+addr2))
287 data->reg_base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); in goldfish_audio_probe()
288 if (data->reg_base == NULL) in goldfish_audio_probe()
/linux-4.1.27/drivers/net/can/mscan/
Dmscan.c64 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_set_mode()
140 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_start()
180 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_restart()
201 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_start_xmit()
306 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_get_rx_frame()
347 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_get_err_frame()
393 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_rx_poll()
440 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_isr()
520 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_do_set_bittiming()
541 struct mscan_regs __iomem *regs = priv->reg_base; in mscan_get_berr_counter()
[all …]
Dmpc5xxx_can.c323 priv->reg_base = base; in mpc5xxx_can_probe()
345 priv->reg_base, dev->irq, priv->can.clock.freq); in mpc5xxx_can_probe()
372 iounmap(priv->reg_base); in mpc5xxx_can_remove()
385 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; in mpc5xxx_can_suspend()
396 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; in mpc5xxx_can_resume()
Dmscan.h285 void __iomem *reg_base; /* ioremap'ed address to registers */ member
/linux-4.1.27/drivers/power/
Dgoldfish_battery.c29 void __iomem *reg_base; member
38 (readl(data->reg_base + addr))
40 (writel(x, data->reg_base + addr))
183 data->reg_base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); in goldfish_battery_probe()
184 if (data->reg_base == NULL) { in goldfish_battery_probe()
/linux-4.1.27/drivers/media/rc/img-ir/
Dimg-ir.h152 void __iomem *reg_base; member
164 iowrite32(data, priv->reg_base + reg_offs); in img_ir_write()
170 return ioread32(priv->reg_base + reg_offs); in img_ir_read()
Dimg-ir-core.c105 priv->reg_base = devm_ioremap_resource(&pdev->dev, res_regs); in img_ir_probe()
106 if (IS_ERR(priv->reg_base)) in img_ir_probe()
107 return PTR_ERR(priv->reg_base); in img_ir_probe()
/linux-4.1.27/arch/arm/mach-s3c24xx/
Dcommon.h117 void __iomem *reg_base);
121 unsigned long ext_f, void __iomem *reg_base);
126 void __iomem *reg_base);
/linux-4.1.27/drivers/pinctrl/samsung/
Dpinctrl-exynos5440.c115 void __iomem *reg_base; member
357 base = priv->reg_base; in exynos5440_pinmux_setup()
410 base = priv->reg_base; in exynos5440_pinconf_set()
478 base = priv->reg_base; in exynos5440_pinconf_get()
557 void __iomem *base = priv->reg_base; in exynos5440_gpio_set()
571 void __iomem *base = priv->reg_base; in exynos5440_gpio_get()
584 void __iomem *base = priv->reg_base; in exynos5440_gpio_direction_input()
604 void __iomem *base = priv->reg_base; in exynos5440_gpio_direction_output()
888 gpio_int = readl(d->reg_base + GPIO_INT); in exynos5440_gpio_irq_unmask()
890 writel(gpio_int, d->reg_base + GPIO_INT); in exynos5440_gpio_irq_unmask()
[all …]
Dpinctrl-samsung.c427 void __iomem *reg_base; in samsung_pinconf_rw() local
434 pin_to_reg_bank(drvdata, pin - drvdata->pin_base, &reg_base, in samsung_pinconf_rw()
448 data = readl(reg_base + cfg_reg); in samsung_pinconf_rw()
454 writel(data, reg_base + cfg_reg); in samsung_pinconf_rw()
/linux-4.1.27/drivers/phy/
Dphy-rockchip-usb.c41 struct regmap *reg_base; member
49 return regmap_write(phy->reg_base, phy->reg_offset, in rockchip_usb_phy_power()
120 rk_phy->reg_base = grf; in rockchip_usb_phy_probe()
/linux-4.1.27/drivers/mmc/host/
Dandroid-goldfish.c58 #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
59 #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
131 void __iomem *reg_base; member
479 host->reg_base = ioremap(res->start, resource_size(res)); in goldfish_mmc_probe()
480 if (host->reg_base == NULL) { in goldfish_mmc_probe()
538 iounmap(host->reg_base); in goldfish_mmc_probe()
554 iounmap(host->reg_base); in goldfish_mmc_remove()
Dsunxi-mmc.c75 readl((host)->reg_base + SDXC_##reg)
77 writel((value), (host)->reg_base + SDXC_##reg)
225 void __iomem *reg_base; member
905 host->reg_base = devm_ioremap_resource(&pdev->dev, in sunxi_mmc_resource_request()
907 if (IS_ERR(host->reg_base)) in sunxi_mmc_resource_request()
908 return PTR_ERR(host->reg_base); in sunxi_mmc_resource_request()
1044 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); in sunxi_mmc_probe()
/linux-4.1.27/drivers/iio/adc/
Dcc10001_adc.c60 void __iomem *reg_base; member
73 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
79 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
342 adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res); in cc10001_adc_probe()
343 if (IS_ERR(adc_dev->reg_base)) { in cc10001_adc_probe()
344 ret = PTR_ERR(adc_dev->reg_base); in cc10001_adc_probe()
Dat91_adc.c140 (readl_relaxed(st->reg_base + reg))
142 (writel_relaxed(val, st->reg_base + reg))
202 void __iomem *reg_base; member
1167 st->reg_base = devm_ioremap_resource(&pdev->dev, res); in at91_adc_probe()
1168 if (IS_ERR(st->reg_base)) { in at91_adc_probe()
1169 return PTR_ERR(st->reg_base); in at91_adc_probe()
Dtwl4030-madc.c277 u8 reg_base, unsigned in twl4030_madc_read_channels() argument
286 reg = reg_base + (2 * i); in twl4030_madc_read_channels()
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-rockchip.c107 void __iomem *reg_base; member
877 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
883 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
1313 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; in rockchip_gpio_set()
1337 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_gpio_get()
1407 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
1431 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
1435 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
1442 bank->reg_base + GPIO_INT_POLARITY); in rockchip_irq_demux()
1447 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
[all …]
/linux-4.1.27/drivers/clk/pistachio/
Dclk.h114 unsigned long reg_base; member
125 .reg_base = _reg, \
136 .reg_base = _reg, \
Dclk-pll.c395 0, p->base + pll[i].reg_base, in pistachio_clk_register_pll()
/linux-4.1.27/drivers/usb/host/
Dehci-pmcmsp.c49 struct ehci_regs *reg_base = ehci->regs; in usb_hcd_tdi_set_mode() local
52 base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE; in usb_hcd_tdi_set_mode()
53 statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS; in usb_hcd_tdi_set_mode()
54 fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO; in usb_hcd_tdi_set_mode()
/linux-4.1.27/drivers/rtc/
Drtc-x1205.c94 unsigned char reg_base) in x1205_get_datetime() argument
96 unsigned char dt_addr[2] = { 0, reg_base }; in x1205_get_datetime()
128 if (reg_base < X1205_CCR_BASE) in x1205_get_datetime()
178 u8 reg_base, unsigned char alm_enable) in x1205_set_datetime() argument
181 unsigned char rdata[10] = { 0, reg_base }; in x1205_set_datetime()
214 if (reg_base < X1205_CCR_BASE) in x1205_set_datetime()
241 if (reg_base < X1205_CCR_BASE) { in x1205_set_datetime()
/linux-4.1.27/drivers/pci/host/
Dpcie-xilinx.c112 void __iomem *reg_base; member
131 return readl(port->reg_base + reg); in pcie_read()
136 writel(val, port->reg_base + reg); in pcie_write()
212 return port->reg_base + relbus + where; in xilinx_pcie_map_bus()
773 port->reg_base = devm_ioremap_resource(dev, &regs); in xilinx_pcie_parse_dt()
774 if (IS_ERR(port->reg_base)) in xilinx_pcie_parse_dt()
775 return PTR_ERR(port->reg_base); in xilinx_pcie_parse_dt()
/linux-4.1.27/include/linux/
Dirq.h745 void __iomem *reg_base; member
817 void __iomem *reg_base, irq_flow_handler_t handler);
859 gc->reg_writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
861 writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
868 return gc->reg_readl(gc->reg_base + reg_offset); in irq_reg_readl()
870 return readl(gc->reg_base + reg_offset); in irq_reg_readl()
/linux-4.1.27/drivers/pinctrl/intel/
Dpinctrl-baytrail.c150 void __iomem *reg_base; member
168 return vg->reg_base + reg_offset + reg; in byt_gpio_reg()
376 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); in byt_gpio_dbg_show()
377 val = readl(vg->reg_base + offs + BYT_VAL_REG); in byt_gpio_dbg_show()
588 vg->reg_base = devm_ioremap_resource(dev, mem_rc); in byt_gpio_probe()
589 if (IS_ERR(vg->reg_base)) in byt_gpio_probe()
590 return PTR_ERR(vg->reg_base); in byt_gpio_probe()
/linux-4.1.27/arch/mips/jz4740/
Dirq.c61 writel(mask, gc->reg_base + regs->enable); in jz4740_irq_set_mask()
62 writel(~mask, gc->reg_base + regs->disable); in jz4740_irq_set_mask()
/linux-4.1.27/drivers/net/ethernet/sfc/
Dqt202x_phy.c463 int mmd, reg_base, rc, i; in qt202x_phy_get_module_eeprom() local
467 reg_base = 0xd000; in qt202x_phy_get_module_eeprom()
470 reg_base = 0x8007; in qt202x_phy_get_module_eeprom()
474 rc = efx_mdio_read(efx, mmd, reg_base + ee->offset + i); in qt202x_phy_get_module_eeprom()
/linux-4.1.27/kernel/irq/
Dgeneric-chip.c207 void __iomem *reg_base, irq_flow_handler_t handler) in irq_init_generic_chip() argument
212 gc->reg_base = reg_base; in irq_init_generic_chip()
230 void __iomem *reg_base, irq_flow_handler_t handler) in irq_alloc_generic_chip() argument
237 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base, in irq_alloc_generic_chip()
/linux-4.1.27/drivers/gpu/drm/msm/dsi/
Ddsi_phy.c38 void __iomem *reg_base; member
175 void __iomem *base = phy->reg_base; in dsi_28nm_phy_regulator_ctrl()
307 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG"); in msm_dsi_phy_init()
308 if (IS_ERR_OR_NULL(phy->reg_base)) { in msm_dsi_phy_init()
/linux-4.1.27/arch/x86/platform/intel-quark/
Dimr.c42 int reg_base; member
111 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; in imr_read()
149 u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; in imr_write()
633 idev->reg_base = QUARK_X1000_IMR_REGBASE; in imr_init()
/linux-4.1.27/drivers/media/pci/solo6x10/
Dsolo6x10.h197 u8 __iomem *reg_base; member
290 ret = readl(solo_dev->reg_base + reg); in solo_reg_read()
308 writel(data, solo_dev->reg_base + reg); in solo_reg_write()
Dsolo6x10-core.c154 if (solo_dev->reg_base) { in free_solo_dev()
167 pci_iounmap(pdev, solo_dev->reg_base); in free_solo_dev()
508 solo_dev->reg_base = pci_ioremap_bar(pdev, 0); in solo_pci_probe()
509 if (solo_dev->reg_base == NULL) { in solo_pci_probe()
/linux-4.1.27/drivers/fmc/
Dfmc-sdb.c29 unsigned long reg_base, int level) in __fmc_scan_sdb_tree() argument
77 subaddr += reg_base; in __fmc_scan_sdb_tree()
78 newbase += reg_base; in __fmc_scan_sdb_tree()
/linux-4.1.27/arch/arm/mach-s3c64xx/
Dcommon.h28 unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
/linux-4.1.27/drivers/net/can/
Dxilinx_can.c142 void __iomem *reg_base; member
172 iowrite32(val, priv->reg_base + reg); in xcan_write_reg_le()
185 return ioread32(priv->reg_base + reg); in xcan_read_reg_le()
199 iowrite32be(val, priv->reg_base + reg); in xcan_write_reg_be()
212 return ioread32be(priv->reg_base + reg); in xcan_read_reg_be()
1081 priv->reg_base = addr; in xcan_probe()
1151 priv->reg_base, ndev->irq, priv->can.clock.freq, in xcan_probe()
Dat91_can.c143 void __iomem *reg_base; member
294 return readl_relaxed(priv->reg_base + reg); in at91_read()
300 writel_relaxed(value, priv->reg_base + reg); in at91_write()
1352 priv->reg_base = addr; in at91_can_probe()
1375 priv->reg_base, dev->irq); in at91_can_probe()
1399 iounmap(priv->reg_base); in at91_can_remove()
/linux-4.1.27/drivers/macintosh/
Dwindfarm_fcu_controls.c171 int rc, reg_base, shift = pv->rpm_shift; in wf_fcu_fan_get_rpm() local
189 reg_base = 0x11; in wf_fcu_fan_get_rpm()
191 reg_base = 0x10; in wf_fcu_fan_get_rpm()
193 rc = wf_fcu_read_reg(pv, reg_base + (fan->id * 2), buf, 2); in wf_fcu_fan_get_rpm()
/linux-4.1.27/include/video/
Dpxa168fb.h70 void __iomem *reg_base; member
Dexynos_mipi_dsim.h226 void __iomem *reg_base; member
/linux-4.1.27/drivers/pcmcia/
Dm32r_cfc.c318 unsigned int reg_base; in add_pcc_socket() local
320 reg_base = (unsigned int)PLD_CFRSTCR; in add_pcc_socket()
321 reg_base |= pcc_sockets << 8; in add_pcc_socket()
322 request_region(reg_base, 0x20, "m32r_cfc"); in add_pcc_socket()
/linux-4.1.27/arch/sh/include/asm/
Dpci.h28 unsigned long reg_base; member
/linux-4.1.27/arch/powerpc/kvm/
Dmpic.c198 gpa_t reg_base; member
1390 ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val); in kvm_mpic_read()
1431 ret = kvm_mpic_write_internal(opp, addr - opp->reg_base, in kvm_mpic_write()
1451 opp->reg_base, OPENPIC_REG_SIZE, in map_mmio()
1473 if (base == opp->reg_base) in set_base_addr()
1479 opp->reg_base = base; in set_base_addr()
1569 attr64 = opp->reg_base; in mpic_get_attr()
/linux-4.1.27/drivers/pinctrl/bcm/
Dpinctrl-bcm281xx.c89 void __iomem *reg_base; member
1407 pdata->reg_base = devm_ioremap_resource(&pdev->dev, res); in bcm281xx_pinctrl_probe()
1408 if (IS_ERR(pdata->reg_base)) { in bcm281xx_pinctrl_probe()
1414 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base, in bcm281xx_pinctrl_probe()
/linux-4.1.27/drivers/input/mouse/
Dalps.c2002 int reg_base, bool enable) in alps_passthrough_mode_v3() argument
2009 reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x0008); in alps_passthrough_mode_v3()
2042 static int alps_probe_trackstick_v3(struct psmouse *psmouse, int reg_base) in alps_probe_trackstick_v3() argument
2049 reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08); in alps_probe_trackstick_v3()
2061 static int alps_setup_trackstick_v3(struct psmouse *psmouse, int reg_base) in alps_setup_trackstick_v3() argument
2067 if (alps_passthrough_mode_v3(psmouse, reg_base, true)) in alps_setup_trackstick_v3()
2109 reg_base + 0x08, 0x82) || in alps_setup_trackstick_v3()
2115 if (alps_passthrough_mode_v3(psmouse, reg_base, false)) in alps_setup_trackstick_v3()
/linux-4.1.27/drivers/mfd/
Djz4740-adc.c74 status = readb(gc->reg_base + JZ_REG_ADC_STATUS); in jz4740_adc_irq_demux()
/linux-4.1.27/drivers/net/ethernet/qlogic/qlge/
Dqlge.h2081 void __iomem *reg_base; member
2160 return readl(qdev->reg_base + reg); in ql_read32()
2168 writel(val, qdev->reg_base + reg); in ql_write32()
Dqlge_main.c4562 if (qdev->reg_base) in ql_release_all()
4563 iounmap(qdev->reg_base); in ql_release_all()
4618 qdev->reg_base = in ql_init_device()
4621 if (!qdev->reg_base) { in ql_init_device()
Dqlge_dbg.c1617 DUMP_QDEV_FIELD(qdev, "%p", reg_base); in ql_dump_qdev()
/linux-4.1.27/drivers/input/misc/
Dad714x.c916 unsigned short reg_base; in ad714x_hw_init() local
922 reg_base = AD714X_STAGECFG_REG + i * STAGE_CFGREG_NUM; in ad714x_hw_init()
924 ad714x->write(ad714x, reg_base + j, in ad714x_hw_init()
/linux-4.1.27/drivers/scsi/bnx2i/
Dbnx2i.h405 resource_size_t reg_base; member
Dbnx2i_hwi.c2736 resource_size_t reg_base; in bnx2i_map_ep_dbell_regs() local
2741 reg_base = pci_resource_start(ep->hba->pcidev, in bnx2i_map_ep_dbell_regs()
2744 ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4); in bnx2i_map_ep_dbell_regs()
2763 ep->qp.ctx_base = ioremap_nocache(ep->hba->reg_base + reg_off, in bnx2i_map_ep_dbell_regs()
Dbnx2i_iscsi.c817 hba->reg_base = pci_resource_start(hba->pcidev, 0); in bnx2i_alloc_hba()
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
Dhw.h417 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) argument
/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_device.c249 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; in radeon_scratch_init()
252 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in radeon_scratch_init()
Dradeon_fence.c830 rdev->scratch.reg_base; in radeon_fence_driver_start_ring()
Dr600.c2766 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2769 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
Dsi.c3361 rdev->scratch.reg_base = SCRATCH_REG0; in si_scratch_init()
3364 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in si_scratch_init()
Dradeon.h704 uint32_t reg_base; member
Dcik.c3824 rdev->scratch.reg_base = SCRATCH_REG0; in cik_scratch_init()
3827 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in cik_scratch_init()
/linux-4.1.27/drivers/scsi/bnx2fc/
Dbnx2fc_hwi.c1419 resource_size_t reg_base; in bnx2fc_map_doorbell() local
1423 reg_base = pci_resource_start(hba->pcidev, in bnx2fc_map_doorbell()
1426 tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4); in bnx2fc_map_doorbell()
/linux-4.1.27/drivers/net/ethernet/micrel/
Dksz884x.c6924 unsigned long reg_base; in pcidev_init() local
6945 reg_base = pci_resource_start(pdev, 0); in pcidev_init()
6950 if (!request_mem_region(reg_base, reg_len, DRV_NAME)) in pcidev_init()
6965 hw->io = ioremap(reg_base, reg_len); in pcidev_init()
7130 release_mem_region(reg_base, reg_len); in pcidev_init()
/linux-4.1.27/drivers/gpu/ipu-v3/
Dipu-common.c1112 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
/linux-4.1.27/drivers/gpu/drm/i915/
Di915_gem.c4631 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); in i915_gem_l3_remap() local
4649 intel_ring_emit(ring, reg_base + i); in i915_gem_l3_remap()