1/* 2 * Library implementing the most common irq chip callback functions 3 * 4 * Copyright (C) 2011, Thomas Gleixner 5 */ 6#include <linux/io.h> 7#include <linux/irq.h> 8#include <linux/slab.h> 9#include <linux/export.h> 10#include <linux/irqdomain.h> 11#include <linux/interrupt.h> 12#include <linux/kernel_stat.h> 13#include <linux/syscore_ops.h> 14 15#include "internals.h" 16 17static LIST_HEAD(gc_list); 18static DEFINE_RAW_SPINLOCK(gc_lock); 19 20/** 21 * irq_gc_noop - NOOP function 22 * @d: irq_data 23 */ 24void irq_gc_noop(struct irq_data *d) 25{ 26} 27 28/** 29 * irq_gc_mask_disable_reg - Mask chip via disable register 30 * @d: irq_data 31 * 32 * Chip has separate enable/disable registers instead of a single mask 33 * register. 34 */ 35void irq_gc_mask_disable_reg(struct irq_data *d) 36{ 37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 38 struct irq_chip_type *ct = irq_data_get_chip_type(d); 39 u32 mask = d->mask; 40 41 irq_gc_lock(gc); 42 irq_reg_writel(gc, mask, ct->regs.disable); 43 *ct->mask_cache &= ~mask; 44 irq_gc_unlock(gc); 45} 46 47/** 48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register 49 * @d: irq_data 50 * 51 * Chip has a single mask register. Values of this register are cached 52 * and protected by gc->lock 53 */ 54void irq_gc_mask_set_bit(struct irq_data *d) 55{ 56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 57 struct irq_chip_type *ct = irq_data_get_chip_type(d); 58 u32 mask = d->mask; 59 60 irq_gc_lock(gc); 61 *ct->mask_cache |= mask; 62 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); 63 irq_gc_unlock(gc); 64} 65EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); 66 67/** 68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register 69 * @d: irq_data 70 * 71 * Chip has a single mask register. Values of this register are cached 72 * and protected by gc->lock 73 */ 74void irq_gc_mask_clr_bit(struct irq_data *d) 75{ 76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 77 struct irq_chip_type *ct = irq_data_get_chip_type(d); 78 u32 mask = d->mask; 79 80 irq_gc_lock(gc); 81 *ct->mask_cache &= ~mask; 82 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); 83 irq_gc_unlock(gc); 84} 85EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit); 86 87/** 88 * irq_gc_unmask_enable_reg - Unmask chip via enable register 89 * @d: irq_data 90 * 91 * Chip has separate enable/disable registers instead of a single mask 92 * register. 93 */ 94void irq_gc_unmask_enable_reg(struct irq_data *d) 95{ 96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 97 struct irq_chip_type *ct = irq_data_get_chip_type(d); 98 u32 mask = d->mask; 99 100 irq_gc_lock(gc); 101 irq_reg_writel(gc, mask, ct->regs.enable); 102 *ct->mask_cache |= mask; 103 irq_gc_unlock(gc); 104} 105 106/** 107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit 108 * @d: irq_data 109 */ 110void irq_gc_ack_set_bit(struct irq_data *d) 111{ 112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 113 struct irq_chip_type *ct = irq_data_get_chip_type(d); 114 u32 mask = d->mask; 115 116 irq_gc_lock(gc); 117 irq_reg_writel(gc, mask, ct->regs.ack); 118 irq_gc_unlock(gc); 119} 120EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit); 121 122/** 123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit 124 * @d: irq_data 125 */ 126void irq_gc_ack_clr_bit(struct irq_data *d) 127{ 128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 129 struct irq_chip_type *ct = irq_data_get_chip_type(d); 130 u32 mask = ~d->mask; 131 132 irq_gc_lock(gc); 133 irq_reg_writel(gc, mask, ct->regs.ack); 134 irq_gc_unlock(gc); 135} 136 137/** 138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt 139 * @d: irq_data 140 */ 141void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) 142{ 143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 144 struct irq_chip_type *ct = irq_data_get_chip_type(d); 145 u32 mask = d->mask; 146 147 irq_gc_lock(gc); 148 irq_reg_writel(gc, mask, ct->regs.mask); 149 irq_reg_writel(gc, mask, ct->regs.ack); 150 irq_gc_unlock(gc); 151} 152 153/** 154 * irq_gc_eoi - EOI interrupt 155 * @d: irq_data 156 */ 157void irq_gc_eoi(struct irq_data *d) 158{ 159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 160 struct irq_chip_type *ct = irq_data_get_chip_type(d); 161 u32 mask = d->mask; 162 163 irq_gc_lock(gc); 164 irq_reg_writel(gc, mask, ct->regs.eoi); 165 irq_gc_unlock(gc); 166} 167 168/** 169 * irq_gc_set_wake - Set/clr wake bit for an interrupt 170 * @d: irq_data 171 * @on: Indicates whether the wake bit should be set or cleared 172 * 173 * For chips where the wake from suspend functionality is not 174 * configured in a separate register and the wakeup active state is 175 * just stored in a bitmask. 176 */ 177int irq_gc_set_wake(struct irq_data *d, unsigned int on) 178{ 179 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 180 u32 mask = d->mask; 181 182 if (!(mask & gc->wake_enabled)) 183 return -EINVAL; 184 185 irq_gc_lock(gc); 186 if (on) 187 gc->wake_active |= mask; 188 else 189 gc->wake_active &= ~mask; 190 irq_gc_unlock(gc); 191 return 0; 192} 193 194static u32 irq_readl_be(void __iomem *addr) 195{ 196 return ioread32be(addr); 197} 198 199static void irq_writel_be(u32 val, void __iomem *addr) 200{ 201 iowrite32be(val, addr); 202} 203 204static void 205irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, 206 int num_ct, unsigned int irq_base, 207 void __iomem *reg_base, irq_flow_handler_t handler) 208{ 209 raw_spin_lock_init(&gc->lock); 210 gc->num_ct = num_ct; 211 gc->irq_base = irq_base; 212 gc->reg_base = reg_base; 213 gc->chip_types->chip.name = name; 214 gc->chip_types->handler = handler; 215} 216 217/** 218 * irq_alloc_generic_chip - Allocate a generic chip and initialize it 219 * @name: Name of the irq chip 220 * @num_ct: Number of irq_chip_type instances associated with this 221 * @irq_base: Interrupt base nr for this chip 222 * @reg_base: Register base address (virtual) 223 * @handler: Default flow handler associated with this chip 224 * 225 * Returns an initialized irq_chip_generic structure. The chip defaults 226 * to the primary (index 0) irq_chip_type and @handler 227 */ 228struct irq_chip_generic * 229irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, 230 void __iomem *reg_base, irq_flow_handler_t handler) 231{ 232 struct irq_chip_generic *gc; 233 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); 234 235 gc = kzalloc(sz, GFP_KERNEL); 236 if (gc) { 237 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base, 238 handler); 239 } 240 return gc; 241} 242EXPORT_SYMBOL_GPL(irq_alloc_generic_chip); 243 244static void 245irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) 246{ 247 struct irq_chip_type *ct = gc->chip_types; 248 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; 249 int i; 250 251 for (i = 0; i < gc->num_ct; i++) { 252 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { 253 mskptr = &ct[i].mask_cache_priv; 254 mskreg = ct[i].regs.mask; 255 } 256 ct[i].mask_cache = mskptr; 257 if (flags & IRQ_GC_INIT_MASK_CACHE) 258 *mskptr = irq_reg_readl(gc, mskreg); 259 } 260} 261 262/** 263 * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain 264 * @d: irq domain for which to allocate chips 265 * @irqs_per_chip: Number of interrupts each chip handles 266 * @num_ct: Number of irq_chip_type instances associated with this 267 * @name: Name of the irq chip 268 * @handler: Default flow handler associated with these chips 269 * @clr: IRQ_* bits to clear in the mapping function 270 * @set: IRQ_* bits to set in the mapping function 271 * @gcflags: Generic chip specific setup flags 272 */ 273int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 274 int num_ct, const char *name, 275 irq_flow_handler_t handler, 276 unsigned int clr, unsigned int set, 277 enum irq_gc_flags gcflags) 278{ 279 struct irq_domain_chip_generic *dgc; 280 struct irq_chip_generic *gc; 281 int numchips, sz, i; 282 unsigned long flags; 283 void *tmp; 284 285 if (d->gc) 286 return -EBUSY; 287 288 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip); 289 if (!numchips) 290 return -EINVAL; 291 292 /* Allocate a pointer, generic chip and chiptypes for each chip */ 293 sz = sizeof(*dgc) + numchips * sizeof(gc); 294 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type)); 295 296 tmp = dgc = kzalloc(sz, GFP_KERNEL); 297 if (!dgc) 298 return -ENOMEM; 299 dgc->irqs_per_chip = irqs_per_chip; 300 dgc->num_chips = numchips; 301 dgc->irq_flags_to_set = set; 302 dgc->irq_flags_to_clear = clr; 303 dgc->gc_flags = gcflags; 304 d->gc = dgc; 305 306 /* Calc pointer to the first generic chip */ 307 tmp += sizeof(*dgc) + numchips * sizeof(gc); 308 for (i = 0; i < numchips; i++) { 309 /* Store the pointer to the generic chip */ 310 dgc->gc[i] = gc = tmp; 311 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip, 312 NULL, handler); 313 314 gc->domain = d; 315 if (gcflags & IRQ_GC_BE_IO) { 316 gc->reg_readl = &irq_readl_be; 317 gc->reg_writel = &irq_writel_be; 318 } 319 320 raw_spin_lock_irqsave(&gc_lock, flags); 321 list_add_tail(&gc->list, &gc_list); 322 raw_spin_unlock_irqrestore(&gc_lock, flags); 323 /* Calc pointer to the next generic chip */ 324 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); 325 } 326 d->name = name; 327 return 0; 328} 329EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips); 330 331/** 332 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq 333 * @d: irq domain pointer 334 * @hw_irq: Hardware interrupt number 335 */ 336struct irq_chip_generic * 337irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) 338{ 339 struct irq_domain_chip_generic *dgc = d->gc; 340 int idx; 341 342 if (!dgc) 343 return NULL; 344 idx = hw_irq / dgc->irqs_per_chip; 345 if (idx >= dgc->num_chips) 346 return NULL; 347 return dgc->gc[idx]; 348} 349EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip); 350 351/* 352 * Separate lockdep class for interrupt chip which can nest irq_desc 353 * lock. 354 */ 355static struct lock_class_key irq_nested_lock_class; 356 357/* 358 * irq_map_generic_chip - Map a generic chip for an irq domain 359 */ 360int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 361 irq_hw_number_t hw_irq) 362{ 363 struct irq_data *data = irq_get_irq_data(virq); 364 struct irq_domain_chip_generic *dgc = d->gc; 365 struct irq_chip_generic *gc; 366 struct irq_chip_type *ct; 367 struct irq_chip *chip; 368 unsigned long flags; 369 int idx; 370 371 if (!d->gc) 372 return -ENODEV; 373 374 idx = hw_irq / dgc->irqs_per_chip; 375 if (idx >= dgc->num_chips) 376 return -EINVAL; 377 gc = dgc->gc[idx]; 378 379 idx = hw_irq % dgc->irqs_per_chip; 380 381 if (test_bit(idx, &gc->unused)) 382 return -ENOTSUPP; 383 384 if (test_bit(idx, &gc->installed)) 385 return -EBUSY; 386 387 ct = gc->chip_types; 388 chip = &ct->chip; 389 390 /* We only init the cache for the first mapping of a generic chip */ 391 if (!gc->installed) { 392 raw_spin_lock_irqsave(&gc->lock, flags); 393 irq_gc_init_mask_cache(gc, dgc->gc_flags); 394 raw_spin_unlock_irqrestore(&gc->lock, flags); 395 } 396 397 /* Mark the interrupt as installed */ 398 set_bit(idx, &gc->installed); 399 400 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK) 401 irq_set_lockdep_class(virq, &irq_nested_lock_class); 402 403 if (chip->irq_calc_mask) 404 chip->irq_calc_mask(data); 405 else 406 data->mask = 1 << idx; 407 408 irq_set_chip_and_handler(virq, chip, ct->handler); 409 irq_set_chip_data(virq, gc); 410 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set); 411 return 0; 412} 413EXPORT_SYMBOL_GPL(irq_map_generic_chip); 414 415struct irq_domain_ops irq_generic_chip_ops = { 416 .map = irq_map_generic_chip, 417 .xlate = irq_domain_xlate_onetwocell, 418}; 419EXPORT_SYMBOL_GPL(irq_generic_chip_ops); 420 421/** 422 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip 423 * @gc: Generic irq chip holding all data 424 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base 425 * @flags: Flags for initialization 426 * @clr: IRQ_* bits to clear 427 * @set: IRQ_* bits to set 428 * 429 * Set up max. 32 interrupts starting from gc->irq_base. Note, this 430 * initializes all interrupts to the primary irq_chip_type and its 431 * associated handler. 432 */ 433void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 434 enum irq_gc_flags flags, unsigned int clr, 435 unsigned int set) 436{ 437 struct irq_chip_type *ct = gc->chip_types; 438 struct irq_chip *chip = &ct->chip; 439 unsigned int i; 440 441 raw_spin_lock(&gc_lock); 442 list_add_tail(&gc->list, &gc_list); 443 raw_spin_unlock(&gc_lock); 444 445 irq_gc_init_mask_cache(gc, flags); 446 447 for (i = gc->irq_base; msk; msk >>= 1, i++) { 448 if (!(msk & 0x01)) 449 continue; 450 451 if (flags & IRQ_GC_INIT_NESTED_LOCK) 452 irq_set_lockdep_class(i, &irq_nested_lock_class); 453 454 if (!(flags & IRQ_GC_NO_MASK)) { 455 struct irq_data *d = irq_get_irq_data(i); 456 457 if (chip->irq_calc_mask) 458 chip->irq_calc_mask(d); 459 else 460 d->mask = 1 << (i - gc->irq_base); 461 } 462 irq_set_chip_and_handler(i, chip, ct->handler); 463 irq_set_chip_data(i, gc); 464 irq_modify_status(i, clr, set); 465 } 466 gc->irq_cnt = i - gc->irq_base; 467} 468EXPORT_SYMBOL_GPL(irq_setup_generic_chip); 469 470/** 471 * irq_setup_alt_chip - Switch to alternative chip 472 * @d: irq_data for this interrupt 473 * @type: Flow type to be initialized 474 * 475 * Only to be called from chip->irq_set_type() callbacks. 476 */ 477int irq_setup_alt_chip(struct irq_data *d, unsigned int type) 478{ 479 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 480 struct irq_chip_type *ct = gc->chip_types; 481 unsigned int i; 482 483 for (i = 0; i < gc->num_ct; i++, ct++) { 484 if (ct->type & type) { 485 d->chip = &ct->chip; 486 irq_data_to_desc(d)->handle_irq = ct->handler; 487 return 0; 488 } 489 } 490 return -EINVAL; 491} 492EXPORT_SYMBOL_GPL(irq_setup_alt_chip); 493 494/** 495 * irq_remove_generic_chip - Remove a chip 496 * @gc: Generic irq chip holding all data 497 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base 498 * @clr: IRQ_* bits to clear 499 * @set: IRQ_* bits to set 500 * 501 * Remove up to 32 interrupts starting from gc->irq_base. 502 */ 503void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 504 unsigned int clr, unsigned int set) 505{ 506 unsigned int i = gc->irq_base; 507 508 raw_spin_lock(&gc_lock); 509 list_del(&gc->list); 510 raw_spin_unlock(&gc_lock); 511 512 for (; msk; msk >>= 1, i++) { 513 if (!(msk & 0x01)) 514 continue; 515 516 /* Remove handler first. That will mask the irq line */ 517 irq_set_handler(i, NULL); 518 irq_set_chip(i, &no_irq_chip); 519 irq_set_chip_data(i, NULL); 520 irq_modify_status(i, clr, set); 521 } 522} 523EXPORT_SYMBOL_GPL(irq_remove_generic_chip); 524 525static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) 526{ 527 unsigned int virq; 528 529 if (!gc->domain) 530 return irq_get_irq_data(gc->irq_base); 531 532 /* 533 * We don't know which of the irqs has been actually 534 * installed. Use the first one. 535 */ 536 if (!gc->installed) 537 return NULL; 538 539 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed)); 540 return virq ? irq_get_irq_data(virq) : NULL; 541} 542 543#ifdef CONFIG_PM 544static int irq_gc_suspend(void) 545{ 546 struct irq_chip_generic *gc; 547 548 list_for_each_entry(gc, &gc_list, list) { 549 struct irq_chip_type *ct = gc->chip_types; 550 551 if (ct->chip.irq_suspend) { 552 struct irq_data *data = irq_gc_get_irq_data(gc); 553 554 if (data) 555 ct->chip.irq_suspend(data); 556 } 557 } 558 return 0; 559} 560 561static void irq_gc_resume(void) 562{ 563 struct irq_chip_generic *gc; 564 565 list_for_each_entry(gc, &gc_list, list) { 566 struct irq_chip_type *ct = gc->chip_types; 567 568 if (ct->chip.irq_resume) { 569 struct irq_data *data = irq_gc_get_irq_data(gc); 570 571 if (data) 572 ct->chip.irq_resume(data); 573 } 574 } 575} 576#else 577#define irq_gc_suspend NULL 578#define irq_gc_resume NULL 579#endif 580 581static void irq_gc_shutdown(void) 582{ 583 struct irq_chip_generic *gc; 584 585 list_for_each_entry(gc, &gc_list, list) { 586 struct irq_chip_type *ct = gc->chip_types; 587 588 if (ct->chip.irq_pm_shutdown) { 589 struct irq_data *data = irq_gc_get_irq_data(gc); 590 591 if (data) 592 ct->chip.irq_pm_shutdown(data); 593 } 594 } 595} 596 597static struct syscore_ops irq_gc_syscore_ops = { 598 .suspend = irq_gc_suspend, 599 .resume = irq_gc_resume, 600 .shutdown = irq_gc_shutdown, 601}; 602 603static int __init irq_gc_init_ops(void) 604{ 605 register_syscore_ops(&irq_gc_syscore_ops); 606 return 0; 607} 608device_initcall(irq_gc_init_ops); 609