1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Authors: Thomas Abraham <thomas.ab@samsung.com> 4 * Chander Kashyap <k.chander@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5420 SoC. 11*/ 12 13#include <dt-bindings/clock/exynos5420.h> 14#include <linux/clk.h> 15#include <linux/clkdev.h> 16#include <linux/clk-provider.h> 17#include <linux/of.h> 18#include <linux/of_address.h> 19#include <linux/syscore_ops.h> 20 21#include "clk.h" 22 23#define APLL_LOCK 0x0 24#define APLL_CON0 0x100 25#define SRC_CPU 0x200 26#define DIV_CPU0 0x500 27#define DIV_CPU1 0x504 28#define GATE_BUS_CPU 0x700 29#define GATE_SCLK_CPU 0x800 30#define CLKOUT_CMU_CPU 0xa00 31#define SRC_MASK_CPERI 0x4300 32#define GATE_IP_G2D 0x8800 33#define CPLL_LOCK 0x10020 34#define DPLL_LOCK 0x10030 35#define EPLL_LOCK 0x10040 36#define RPLL_LOCK 0x10050 37#define IPLL_LOCK 0x10060 38#define SPLL_LOCK 0x10070 39#define VPLL_LOCK 0x10080 40#define MPLL_LOCK 0x10090 41#define CPLL_CON0 0x10120 42#define DPLL_CON0 0x10128 43#define EPLL_CON0 0x10130 44#define EPLL_CON1 0x10134 45#define EPLL_CON2 0x10138 46#define RPLL_CON0 0x10140 47#define RPLL_CON1 0x10144 48#define RPLL_CON2 0x10148 49#define IPLL_CON0 0x10150 50#define SPLL_CON0 0x10160 51#define VPLL_CON0 0x10170 52#define MPLL_CON0 0x10180 53#define SRC_TOP0 0x10200 54#define SRC_TOP1 0x10204 55#define SRC_TOP2 0x10208 56#define SRC_TOP3 0x1020c 57#define SRC_TOP4 0x10210 58#define SRC_TOP5 0x10214 59#define SRC_TOP6 0x10218 60#define SRC_TOP7 0x1021c 61#define SRC_TOP8 0x10220 /* 5800 specific */ 62#define SRC_TOP9 0x10224 /* 5800 specific */ 63#define SRC_DISP10 0x1022c 64#define SRC_MAU 0x10240 65#define SRC_FSYS 0x10244 66#define SRC_PERIC0 0x10250 67#define SRC_PERIC1 0x10254 68#define SRC_ISP 0x10270 69#define SRC_CAM 0x10274 /* 5800 specific */ 70#define SRC_TOP10 0x10280 71#define SRC_TOP11 0x10284 72#define SRC_TOP12 0x10288 73#define SRC_TOP13 0x1028c /* 5800 specific */ 74#define SRC_MASK_TOP0 0x10300 75#define SRC_MASK_TOP1 0x10304 76#define SRC_MASK_TOP2 0x10308 77#define SRC_MASK_TOP7 0x1031c 78#define SRC_MASK_DISP10 0x1032c 79#define SRC_MASK_MAU 0x10334 80#define SRC_MASK_FSYS 0x10340 81#define SRC_MASK_PERIC0 0x10350 82#define SRC_MASK_PERIC1 0x10354 83#define SRC_MASK_ISP 0x10370 84#define DIV_TOP0 0x10500 85#define DIV_TOP1 0x10504 86#define DIV_TOP2 0x10508 87#define DIV_TOP8 0x10520 /* 5800 specific */ 88#define DIV_TOP9 0x10524 /* 5800 specific */ 89#define DIV_DISP10 0x1052c 90#define DIV_MAU 0x10544 91#define DIV_FSYS0 0x10548 92#define DIV_FSYS1 0x1054c 93#define DIV_FSYS2 0x10550 94#define DIV_PERIC0 0x10558 95#define DIV_PERIC1 0x1055c 96#define DIV_PERIC2 0x10560 97#define DIV_PERIC3 0x10564 98#define DIV_PERIC4 0x10568 99#define DIV_CAM 0x10574 /* 5800 specific */ 100#define SCLK_DIV_ISP0 0x10580 101#define SCLK_DIV_ISP1 0x10584 102#define DIV2_RATIO0 0x10590 103#define DIV4_RATIO 0x105a0 104#define GATE_BUS_TOP 0x10700 105#define GATE_BUS_DISP1 0x10728 106#define GATE_BUS_GEN 0x1073c 107#define GATE_BUS_FSYS0 0x10740 108#define GATE_BUS_FSYS2 0x10748 109#define GATE_BUS_PERIC 0x10750 110#define GATE_BUS_PERIC1 0x10754 111#define GATE_BUS_PERIS0 0x10760 112#define GATE_BUS_PERIS1 0x10764 113#define GATE_BUS_NOC 0x10770 114#define GATE_TOP_SCLK_ISP 0x10870 115#define GATE_IP_GSCL0 0x10910 116#define GATE_IP_GSCL1 0x10920 117#define GATE_IP_CAM 0x10924 /* 5800 specific */ 118#define GATE_IP_MFC 0x1092c 119#define GATE_IP_DISP1 0x10928 120#define GATE_IP_G3D 0x10930 121#define GATE_IP_GEN 0x10934 122#define GATE_IP_FSYS 0x10944 123#define GATE_IP_PERIC 0x10950 124#define GATE_IP_PERIS 0x10960 125#define GATE_IP_MSCL 0x10970 126#define GATE_TOP_SCLK_GSCL 0x10820 127#define GATE_TOP_SCLK_DISP1 0x10828 128#define GATE_TOP_SCLK_MAU 0x1083c 129#define GATE_TOP_SCLK_FSYS 0x10840 130#define GATE_TOP_SCLK_PERIC 0x10850 131#define TOP_SPARE2 0x10b08 132#define BPLL_LOCK 0x20010 133#define BPLL_CON0 0x20110 134#define KPLL_LOCK 0x28000 135#define KPLL_CON0 0x28100 136#define SRC_KFC 0x28200 137#define DIV_KFC0 0x28500 138 139/* Exynos5x SoC type */ 140enum exynos5x_soc { 141 EXYNOS5420, 142 EXYNOS5800, 143}; 144 145/* list of PLLs */ 146enum exynos5x_plls { 147 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 148 bpll, kpll, 149 nr_plls /* number of PLLs */ 150}; 151 152static void __iomem *reg_base; 153static enum exynos5x_soc exynos5x_soc; 154 155#ifdef CONFIG_PM_SLEEP 156static struct samsung_clk_reg_dump *exynos5x_save; 157static struct samsung_clk_reg_dump *exynos5800_save; 158 159/* 160 * list of controller registers to be saved and restored during a 161 * suspend/resume cycle. 162 */ 163static unsigned long exynos5x_clk_regs[] __initdata = { 164 SRC_CPU, 165 DIV_CPU0, 166 DIV_CPU1, 167 GATE_BUS_CPU, 168 GATE_SCLK_CPU, 169 CLKOUT_CMU_CPU, 170 EPLL_CON0, 171 EPLL_CON1, 172 EPLL_CON2, 173 RPLL_CON0, 174 RPLL_CON1, 175 RPLL_CON2, 176 SRC_TOP0, 177 SRC_TOP1, 178 SRC_TOP2, 179 SRC_TOP3, 180 SRC_TOP4, 181 SRC_TOP5, 182 SRC_TOP6, 183 SRC_TOP7, 184 SRC_DISP10, 185 SRC_MAU, 186 SRC_FSYS, 187 SRC_PERIC0, 188 SRC_PERIC1, 189 SRC_TOP10, 190 SRC_TOP11, 191 SRC_TOP12, 192 SRC_MASK_TOP2, 193 SRC_MASK_TOP7, 194 SRC_MASK_DISP10, 195 SRC_MASK_FSYS, 196 SRC_MASK_PERIC0, 197 SRC_MASK_PERIC1, 198 SRC_MASK_TOP0, 199 SRC_MASK_TOP1, 200 SRC_MASK_MAU, 201 SRC_MASK_ISP, 202 SRC_ISP, 203 DIV_TOP0, 204 DIV_TOP1, 205 DIV_TOP2, 206 DIV_DISP10, 207 DIV_MAU, 208 DIV_FSYS0, 209 DIV_FSYS1, 210 DIV_FSYS2, 211 DIV_PERIC0, 212 DIV_PERIC1, 213 DIV_PERIC2, 214 DIV_PERIC3, 215 DIV_PERIC4, 216 SCLK_DIV_ISP0, 217 SCLK_DIV_ISP1, 218 DIV2_RATIO0, 219 DIV4_RATIO, 220 GATE_BUS_DISP1, 221 GATE_BUS_TOP, 222 GATE_BUS_GEN, 223 GATE_BUS_FSYS0, 224 GATE_BUS_FSYS2, 225 GATE_BUS_PERIC, 226 GATE_BUS_PERIC1, 227 GATE_BUS_PERIS0, 228 GATE_BUS_PERIS1, 229 GATE_BUS_NOC, 230 GATE_TOP_SCLK_ISP, 231 GATE_IP_GSCL0, 232 GATE_IP_GSCL1, 233 GATE_IP_MFC, 234 GATE_IP_DISP1, 235 GATE_IP_G3D, 236 GATE_IP_GEN, 237 GATE_IP_FSYS, 238 GATE_IP_PERIC, 239 GATE_IP_PERIS, 240 GATE_IP_MSCL, 241 GATE_TOP_SCLK_GSCL, 242 GATE_TOP_SCLK_DISP1, 243 GATE_TOP_SCLK_MAU, 244 GATE_TOP_SCLK_FSYS, 245 GATE_TOP_SCLK_PERIC, 246 TOP_SPARE2, 247 SRC_KFC, 248 DIV_KFC0, 249}; 250 251static unsigned long exynos5800_clk_regs[] __initdata = { 252 SRC_TOP8, 253 SRC_TOP9, 254 SRC_CAM, 255 SRC_TOP1, 256 DIV_TOP8, 257 DIV_TOP9, 258 DIV_CAM, 259 GATE_IP_CAM, 260}; 261 262static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 263 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 264 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 265 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 266 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 267 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 268 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 269 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 270 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 271 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 272 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 273 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 274 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 275 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 276 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 277}; 278 279static int exynos5420_clk_suspend(void) 280{ 281 samsung_clk_save(reg_base, exynos5x_save, 282 ARRAY_SIZE(exynos5x_clk_regs)); 283 284 if (exynos5x_soc == EXYNOS5800) 285 samsung_clk_save(reg_base, exynos5800_save, 286 ARRAY_SIZE(exynos5800_clk_regs)); 287 288 samsung_clk_restore(reg_base, exynos5420_set_clksrc, 289 ARRAY_SIZE(exynos5420_set_clksrc)); 290 291 return 0; 292} 293 294static void exynos5420_clk_resume(void) 295{ 296 samsung_clk_restore(reg_base, exynos5x_save, 297 ARRAY_SIZE(exynos5x_clk_regs)); 298 299 if (exynos5x_soc == EXYNOS5800) 300 samsung_clk_restore(reg_base, exynos5800_save, 301 ARRAY_SIZE(exynos5800_clk_regs)); 302} 303 304static struct syscore_ops exynos5420_clk_syscore_ops = { 305 .suspend = exynos5420_clk_suspend, 306 .resume = exynos5420_clk_resume, 307}; 308 309static void exynos5420_clk_sleep_init(void) 310{ 311 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs, 312 ARRAY_SIZE(exynos5x_clk_regs)); 313 if (!exynos5x_save) { 314 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 315 __func__); 316 return; 317 } 318 319 if (exynos5x_soc == EXYNOS5800) { 320 exynos5800_save = 321 samsung_clk_alloc_reg_dump(exynos5800_clk_regs, 322 ARRAY_SIZE(exynos5800_clk_regs)); 323 if (!exynos5800_save) 324 goto err_soc; 325 } 326 327 register_syscore_ops(&exynos5420_clk_syscore_ops); 328 return; 329err_soc: 330 kfree(exynos5x_save); 331 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 332 __func__); 333 return; 334} 335#else 336static void exynos5420_clk_sleep_init(void) {} 337#endif 338 339/* list of all parent clocks */ 340PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 341 "mout_sclk_mpll", "mout_sclk_spll"}; 342PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 343PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 344PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 345PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 346PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 347PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 348PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 349PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 350PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 351PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 352PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 353PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 354PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 355 356PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 357 "mout_sclk_mpll"}; 358PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 359 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 360 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 361PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 362PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 363PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 364 365PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 366PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 367PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 368PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 369 370PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 371PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 372PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 373PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 374 375PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 376PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 377PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 378PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 379 380PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 381PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 382PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 383 384PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 385PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 386 387PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 388 "mout_sclk_spll"}; 389PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 390 391PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 392PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 393 394PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 395PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 396 397PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 398PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 399 400PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 401PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 402 403PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 404PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 405 406PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 407PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 408PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 409 410PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 411PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 412 413PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 414PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 415 416PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 417PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 418PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 419PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 420 421PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 422PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 423 424PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 425PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 426 427PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 428PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 429 430PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 431PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 432 433PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 434 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 435 "mout_sclk_epll", "mout_sclk_rpll"}; 436PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 437 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 438 "mout_sclk_epll", "mout_sclk_rpll"}; 439PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 440 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 441 "mout_sclk_epll", "mout_sclk_rpll"}; 442PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 443 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 444 "mout_sclk_epll", "mout_sclk_rpll"}; 445PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 446PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 447 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 448 "mout_sclk_epll", "mout_sclk_rpll"}; 449PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 450 "mout_sclk_mpll", "mout_sclk_spll"}; 451/* List of parents specific to exynos5800 */ 452PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 453PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 454 "mout_sclk_mpll", "ff_dout_spll2" }; 455PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 456 "mout_sclk_mpll", "ff_dout_spll2", 457 "mout_epll2", "mout_sclk_ipll" }; 458PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 459 "mout_sclk_mpll", "ff_dout_spll2", 460 "mout_epll2" }; 461PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 462 "mout_sclk_mpll", "mout_sclk_spll" }; 463PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 464 "mout_sclk_mpll", "ff_dout_spll2" }; 465PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 466 "mout_sclk_mpll", "mout_sclk_spll", 467 "mout_epll2", "mout_sclk_ipll" }; 468PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 469 "mout_sclk_mpll", 470 "ff_dout_spll2" }; 471PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 472PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 473PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 474PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 475PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 476PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 477PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 478PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 479 480/* fixed rate clocks generated outside the soc */ 481static struct samsung_fixed_rate_clock 482 exynos5x_fixed_rate_ext_clks[] __initdata = { 483 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 484}; 485 486/* fixed rate clocks generated inside the soc */ 487static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { 488 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 489 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 490 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 491 FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 492 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 493}; 494 495static struct samsung_fixed_factor_clock 496 exynos5x_fixed_factor_clks[] __initdata = { 497 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 498 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 499}; 500 501static struct samsung_fixed_factor_clock 502 exynos5800_fixed_factor_clks[] __initdata = { 503 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 504 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 505}; 506 507struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { 508 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 509 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 510 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 511 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 512 513 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 514 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 515 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 516 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 517 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 518 519 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 520 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 521 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 522 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 523 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 524 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 525 526 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 527 20, 2), 528 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 529 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 530 531 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 532 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 533 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 534 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 535 536 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 537 SRC_TOP9, 16, 1), 538 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 539 SRC_TOP9, 20, 1), 540 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 541 SRC_TOP9, 24, 1), 542 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 543 SRC_TOP9, 28, 1), 544 545 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 546 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 547 SRC_TOP13, 20, 1), 548 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 549 SRC_TOP13, 24, 1), 550 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 551 SRC_TOP13, 28, 1), 552 553 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 554}; 555 556struct samsung_div_clock exynos5800_div_clks[] __initdata = { 557 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), 558 559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 560 DIV_TOP8, 16, 3), 561 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 562 DIV_TOP8, 20, 3), 563 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 564 DIV_TOP8, 24, 3), 565 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 566 DIV_TOP8, 28, 3), 567 568 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 569 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 570}; 571 572struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { 573 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 574 GATE_BUS_TOP, 24, 0, 0), 575 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 576 GATE_BUS_TOP, 27, 0, 0), 577}; 578 579struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 580 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 581 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 582 TOP_SPARE2, 4, 1), 583 584 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 585 MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 586 SRC_TOP0, 4, 2, "aclk400_mscl"), 587 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 588 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 589 590 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 591 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 592 SRC_TOP1, 4, 2), 593 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 594 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 595 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 596 597 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 598 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 599 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 600 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 601 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 602 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 603 604 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), 605 606 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 607}; 608 609struct samsung_div_clock exynos5420_div_clks[] __initdata = { 610 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", 611 DIV_TOP0, 16, 3), 612}; 613 614static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 615 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 616 SRC_TOP7, 4, 1), 617 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), 618 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), 619 620 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 621 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 622 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), 623 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 624 625 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 626 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 627 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 628 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 629 630 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 631 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 632 633 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1), 634 635 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 636 SRC_TOP3, 0, 1), 637 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 638 SRC_TOP3, 4, 1), 639 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 640 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 641 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 642 SRC_TOP3, 12, 1), 643 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 644 SRC_TOP3, 16, 1), 645 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 646 SRC_TOP3, 20, 1), 647 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 648 SRC_TOP3, 24, 1), 649 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 650 SRC_TOP3, 28, 1), 651 652 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 653 SRC_TOP4, 0, 1), 654 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 655 SRC_TOP4, 4, 1), 656 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 657 SRC_TOP4, 8, 1), 658 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 659 SRC_TOP4, 12, 1), 660 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 661 SRC_TOP4, 16, 1), 662 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 663 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 664 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 665 SRC_TOP4, 28, 1), 666 667 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 668 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 669 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 670 SRC_TOP5, 4, 1), 671 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 672 SRC_TOP5, 8, 1), 673 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 674 SRC_TOP5, 12, 1), 675 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 676 SRC_TOP5, 16, 1), 677 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 678 SRC_TOP5, 20, 1), 679 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 680 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 681 MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, 682 SRC_TOP5, 28, 1), 683 684 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 685 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), 686 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 687 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 688 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 689 MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1), 690 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 691 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 692 693 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 694 SRC_TOP10, 0, 1), 695 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 696 SRC_TOP10, 4, 1), 697 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 698 SRC_TOP10, 8, 1), 699 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 700 SRC_TOP10, 12, 1), 701 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 702 SRC_TOP10, 16, 1), 703 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 704 SRC_TOP10, 20, 1), 705 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 706 SRC_TOP10, 24, 1), 707 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 708 SRC_TOP10, 28, 1), 709 710 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 711 SRC_TOP11, 0, 1), 712 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 713 SRC_TOP11, 4, 1), 714 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 715 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 716 SRC_TOP11, 12, 1), 717 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 718 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 719 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 720 SRC_TOP11, 28, 1), 721 722 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 723 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 724 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 725 SRC_TOP12, 8, 1), 726 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 727 SRC_TOP12, 12, 1), 728 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1), 729 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 730 SRC_TOP12, 20, 1), 731 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 732 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 733 MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, 734 SRC_TOP12, 28, 1), 735 736 /* DISP1 Block */ 737 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 738 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 739 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 740 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 741 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 742 743 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 744 745 /* MAU Block */ 746 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 747 748 /* FSYS Block */ 749 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 750 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 751 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 752 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 753 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 754 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 755 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 756 757 /* PERIC Block */ 758 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 759 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 760 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 761 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 762 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 763 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 764 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 765 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 766 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 767 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 768 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 769 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 770 771 /* ISP Block */ 772 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 773 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 774 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 775 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 776 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 777}; 778 779static struct samsung_div_clock exynos5x_div_clks[] __initdata = { 780 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 781 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 782 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 783 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 784 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 785 786 DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3), 787 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 788 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 789 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 790 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3), 791 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 792 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 793 794 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 795 DIV_TOP1, 0, 3), 796 DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp", 797 DIV_TOP1, 4, 3), 798 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 799 DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0", 800 DIV_TOP1, 16, 3), 801 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 802 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 803 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 804 805 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 806 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 807 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 808 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 809 DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3), 810 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 811 812 /* DISP1 Block */ 813 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 814 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 815 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 816 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 817 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 818 DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), 819 820 /* Audio Block */ 821 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 822 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 823 824 /* USB3.0 */ 825 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 826 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 827 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 828 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 829 830 /* MMC */ 831 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 832 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 833 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 834 835 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 836 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 837 838 /* UART and PWM */ 839 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 840 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 841 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 842 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 843 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 844 845 /* SPI */ 846 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 847 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 848 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 849 850 /* Mfc Block */ 851 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 852 853 /* PCM */ 854 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 855 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 856 857 /* Audio - I2S */ 858 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 859 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 860 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 861 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 862 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 863 864 /* SPI Pre-Ratio */ 865 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 866 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 867 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 868 869 /* GSCL Block */ 870 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 871 DIV2_RATIO0, 4, 2), 872 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 873 874 /* MSCL Block */ 875 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 876 877 /* PSGEN */ 878 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 879 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 880 881 /* ISP Block */ 882 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 883 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 884 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 885 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 886 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 887 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 888 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 889 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 890 CLK_SET_RATE_PARENT, 0), 891 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 892 CLK_SET_RATE_PARENT, 0), 893}; 894 895static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { 896 /* G2D */ 897 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 898 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 899 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 900 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 901 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 902 903 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 904 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 905 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 906 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 907 908 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 909 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 910 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 911 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 912 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 913 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 914 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 915 GATE_BUS_TOP, 5, 0, 0), 916 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 917 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 918 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 919 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 920 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 921 GATE_BUS_TOP, 8, 0, 0), 922 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 923 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 924 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 925 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 926 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 927 GATE_BUS_TOP, 13, 0, 0), 928 GATE(0, "aclk166", "mout_user_aclk166", 929 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 930 GATE(0, "aclk333", "mout_aclk333", 931 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 932 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 933 GATE_BUS_TOP, 16, 0, 0), 934 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 935 GATE_BUS_TOP, 17, 0, 0), 936 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 937 GATE_BUS_TOP, 18, 0, 0), 938 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 939 GATE_BUS_TOP, 28, 0, 0), 940 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 941 GATE_BUS_TOP, 29, 0, 0), 942 943 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 944 SRC_MASK_TOP2, 24, 0, 0), 945 946 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 947 SRC_MASK_TOP7, 20, 0, 0), 948 949 /* sclk */ 950 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 951 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 952 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 953 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 954 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 955 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 956 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 957 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 958 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 959 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 960 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 961 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 962 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 963 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 964 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 965 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 966 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 967 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 968 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 969 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 970 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 971 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 972 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 973 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 974 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 975 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 976 977 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 978 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 979 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 980 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 981 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 982 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 983 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 984 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 985 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 986 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 987 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 988 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 989 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 990 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 991 992 /* Display */ 993 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 994 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 995 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 996 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 997 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 998 GATE_TOP_SCLK_DISP1, 9, 0, 0), 999 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 1000 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1001 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 1002 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 1003 1004 /* Maudio Block */ 1005 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1006 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1007 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1008 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1009 1010 /* FSYS Block */ 1011 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1012 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1013 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1014 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1015 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1016 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1017 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1018 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1019 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1020 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1021 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1022 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1023 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1024 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1025 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1026 1027 /* PERIC Block */ 1028 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1029 GATE_IP_PERIC, 0, 0, 0), 1030 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1031 GATE_IP_PERIC, 1, 0, 0), 1032 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1033 GATE_IP_PERIC, 2, 0, 0), 1034 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1035 GATE_IP_PERIC, 3, 0, 0), 1036 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1037 GATE_IP_PERIC, 6, 0, 0), 1038 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1039 GATE_IP_PERIC, 7, 0, 0), 1040 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1041 GATE_IP_PERIC, 8, 0, 0), 1042 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1043 GATE_IP_PERIC, 9, 0, 0), 1044 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1045 GATE_IP_PERIC, 10, 0, 0), 1046 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1047 GATE_IP_PERIC, 11, 0, 0), 1048 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1049 GATE_IP_PERIC, 12, 0, 0), 1050 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1051 GATE_IP_PERIC, 13, 0, 0), 1052 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1053 GATE_IP_PERIC, 14, 0, 0), 1054 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1055 GATE_IP_PERIC, 15, 0, 0), 1056 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1057 GATE_IP_PERIC, 16, 0, 0), 1058 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1059 GATE_IP_PERIC, 17, 0, 0), 1060 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1061 GATE_IP_PERIC, 18, 0, 0), 1062 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1063 GATE_IP_PERIC, 20, 0, 0), 1064 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1065 GATE_IP_PERIC, 21, 0, 0), 1066 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1067 GATE_IP_PERIC, 22, 0, 0), 1068 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1069 GATE_IP_PERIC, 23, 0, 0), 1070 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1071 GATE_IP_PERIC, 24, 0, 0), 1072 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1073 GATE_IP_PERIC, 26, 0, 0), 1074 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1075 GATE_IP_PERIC, 28, 0, 0), 1076 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1077 GATE_IP_PERIC, 30, 0, 0), 1078 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1079 GATE_IP_PERIC, 31, 0, 0), 1080 1081 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1082 GATE_BUS_PERIC, 22, 0, 0), 1083 1084 /* PERIS Block */ 1085 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1086 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1087 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1088 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1089 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1090 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1091 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1092 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1093 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1094 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1095 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1096 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1097 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1098 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1099 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1100 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1101 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1102 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1103 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1104 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1105 1106 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 1107 1108 /* GEN Block */ 1109 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1110 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1111 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1112 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1113 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1114 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1115 GATE_IP_GEN, 6, 0, 0), 1116 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1117 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1118 GATE_IP_GEN, 9, 0, 0), 1119 1120 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1121 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1122 GATE_BUS_GEN, 28, 0, 0), 1123 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1124 1125 /* GSCL Block */ 1126 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1127 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1128 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1129 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1130 1131 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1132 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1133 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1134 GATE_IP_GSCL0, 4, 0, 0), 1135 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1136 GATE_IP_GSCL0, 5, 0, 0), 1137 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1138 GATE_IP_GSCL0, 6, 0, 0), 1139 1140 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1141 GATE_IP_GSCL1, 2, 0, 0), 1142 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1143 GATE_IP_GSCL1, 3, 0, 0), 1144 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1145 GATE_IP_GSCL1, 4, 0, 0), 1146 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1147 GATE_IP_GSCL1, 6, 0, 0), 1148 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1149 GATE_IP_GSCL1, 7, 0, 0), 1150 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), 1151 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), 1152 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", 1153 GATE_IP_GSCL1, 16, 0, 0), 1154 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1155 GATE_IP_GSCL1, 17, 0, 0), 1156 1157 /* MSCL Block */ 1158 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1159 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1160 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1161 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1162 GATE_IP_MSCL, 8, 0, 0), 1163 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1164 GATE_IP_MSCL, 9, 0, 0), 1165 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1166 GATE_IP_MSCL, 10, 0, 0), 1167 1168 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1169 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1170 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1171 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1172 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1173 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1174 GATE_IP_DISP1, 7, 0, 0), 1175 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1176 GATE_IP_DISP1, 8, 0, 0), 1177 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1178 GATE_IP_DISP1, 9, 0, 0), 1179 1180 /* ISP */ 1181 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1182 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1183 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1184 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1185 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1186 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1187 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1188 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1189 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1190 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1191 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1192 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1193 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1194 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1195 1196 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1197 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1198 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1199 1200 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1201}; 1202 1203static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = { 1204 PLL_35XX_RATE(2000000000, 250, 3, 0), 1205 PLL_35XX_RATE(1900000000, 475, 6, 0), 1206 PLL_35XX_RATE(1800000000, 225, 3, 0), 1207 PLL_35XX_RATE(1700000000, 425, 6, 0), 1208 PLL_35XX_RATE(1600000000, 200, 3, 0), 1209 PLL_35XX_RATE(1500000000, 250, 4, 0), 1210 PLL_35XX_RATE(1400000000, 175, 3, 0), 1211 PLL_35XX_RATE(1300000000, 325, 6, 0), 1212 PLL_35XX_RATE(1200000000, 200, 2, 1), 1213 PLL_35XX_RATE(1100000000, 275, 3, 1), 1214 PLL_35XX_RATE(1000000000, 250, 3, 1), 1215 PLL_35XX_RATE(900000000, 150, 2, 1), 1216 PLL_35XX_RATE(800000000, 200, 3, 1), 1217 PLL_35XX_RATE(700000000, 175, 3, 1), 1218 PLL_35XX_RATE(600000000, 200, 2, 2), 1219 PLL_35XX_RATE(500000000, 250, 3, 2), 1220 PLL_35XX_RATE(400000000, 200, 3, 2), 1221 PLL_35XX_RATE(300000000, 200, 2, 3), 1222 PLL_35XX_RATE(200000000, 200, 3, 3), 1223}; 1224 1225static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1226 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1227 APLL_CON0, NULL), 1228 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1229 CPLL_CON0, NULL), 1230 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1231 DPLL_CON0, NULL), 1232 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1233 EPLL_CON0, NULL), 1234 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1235 RPLL_CON0, NULL), 1236 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1237 IPLL_CON0, NULL), 1238 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1239 SPLL_CON0, NULL), 1240 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1241 VPLL_CON0, NULL), 1242 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1243 MPLL_CON0, NULL), 1244 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1245 BPLL_CON0, NULL), 1246 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1247 KPLL_CON0, NULL), 1248}; 1249 1250static const struct of_device_id ext_clk_match[] __initconst = { 1251 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1252 { }, 1253}; 1254 1255/* register exynos5420 clocks */ 1256static void __init exynos5x_clk_init(struct device_node *np, 1257 enum exynos5x_soc soc) 1258{ 1259 struct samsung_clk_provider *ctx; 1260 1261 if (np) { 1262 reg_base = of_iomap(np, 0); 1263 if (!reg_base) 1264 panic("%s: failed to map registers\n", __func__); 1265 } else { 1266 panic("%s: unable to determine soc\n", __func__); 1267 } 1268 1269 exynos5x_soc = soc; 1270 1271 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1272 if (!ctx) 1273 panic("%s: unable to allocate context.\n", __func__); 1274 1275 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1276 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1277 ext_clk_match); 1278 1279 if (_get_rate("fin_pll") == 24 * MHZ) { 1280 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1281 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1282 } 1283 1284 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1285 reg_base); 1286 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1287 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1288 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1289 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1290 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1291 ARRAY_SIZE(exynos5x_mux_clks)); 1292 samsung_clk_register_div(ctx, exynos5x_div_clks, 1293 ARRAY_SIZE(exynos5x_div_clks)); 1294 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1295 ARRAY_SIZE(exynos5x_gate_clks)); 1296 1297 if (soc == EXYNOS5420) { 1298 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1299 ARRAY_SIZE(exynos5420_mux_clks)); 1300 samsung_clk_register_div(ctx, exynos5420_div_clks, 1301 ARRAY_SIZE(exynos5420_div_clks)); 1302 } else { 1303 samsung_clk_register_fixed_factor( 1304 ctx, exynos5800_fixed_factor_clks, 1305 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1306 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1307 ARRAY_SIZE(exynos5800_mux_clks)); 1308 samsung_clk_register_div(ctx, exynos5800_div_clks, 1309 ARRAY_SIZE(exynos5800_div_clks)); 1310 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1311 ARRAY_SIZE(exynos5800_gate_clks)); 1312 } 1313 1314 exynos5420_clk_sleep_init(); 1315 1316 samsung_clk_of_add_provider(np, ctx); 1317} 1318 1319static void __init exynos5420_clk_init(struct device_node *np) 1320{ 1321 exynos5x_clk_init(np, EXYNOS5420); 1322} 1323CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 1324 1325static void __init exynos5800_clk_init(struct device_node *np) 1326{ 1327 exynos5x_clk_init(np, EXYNOS5800); 1328} 1329CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init); 1330