65 	void __iomem *reg_base;  member
86 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,  in bcm_kona_gpio_write_lock_regs()  argument
89 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);  in bcm_kona_gpio_write_lock_regs()
90 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_write_lock_regs()
102 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_lock_gpio()
104 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_lock_gpio()
118 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_unlock_gpio()
120 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_unlock_gpio()
128 	void __iomem *reg_base;  in bcm_kona_gpio_set()  local
135 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set()
139 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set()
148 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_set()
150 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_set()
159 	void __iomem *reg_base;  in bcm_kona_gpio_get()  local
166 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get()
170 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_get()
176 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_get()
202 	void __iomem *reg_base;  in bcm_kona_gpio_direction_input()  local
207 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_input()
210 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
213 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
224 	void __iomem *reg_base;  in bcm_kona_gpio_direction_output()  local
231 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_output()
234 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
237 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
240 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
242 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
263 	void __iomem *reg_base;  in bcm_kona_gpio_set_debounce()  local
268 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set_debounce()
290 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
301 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
325 	void __iomem *reg_base;  in bcm_kona_gpio_irq_ack()  local
333 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_ack()
336 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
338 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
346 	void __iomem *reg_base;  in bcm_kona_gpio_irq_mask()  local
354 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_mask()
357 	val = readl(reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
359 	writel(val, reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
367 	void __iomem *reg_base;  in bcm_kona_gpio_irq_unmask()  local
375 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_unmask()
378 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
380 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
388 	void __iomem *reg_base;  in bcm_kona_gpio_irq_set_type()  local
395 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_set_type()
420 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
423 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
432 	void __iomem *reg_base;  in bcm_kona_gpio_irq_handler()  local
445 	reg_base = bank->kona_gpio->reg_base;  in bcm_kona_gpio_irq_handler()
448 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &  in bcm_kona_gpio_irq_handler()
449 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {  in bcm_kona_gpio_irq_handler()
459 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |  in bcm_kona_gpio_irq_handler()
460 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_handler()
545 	void __iomem *reg_base;  in bcm_kona_gpio_reset()  local
548 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_reset()
552 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);  in bcm_kona_gpio_reset()
553 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));  in bcm_kona_gpio_reset()
554 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));  in bcm_kona_gpio_reset()
556 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);  in bcm_kona_gpio_reset()
614 	kona_gpio->reg_base = devm_ioremap_resource(dev, res);  in bcm_kona_gpio_probe()
615 	if (IS_ERR(kona_gpio->reg_base)) {  in bcm_kona_gpio_probe()