1/* 2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de> 3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 */ 15#include <linux/module.h> 16#include <linux/export.h> 17#include <linux/types.h> 18#include <linux/reset.h> 19#include <linux/platform_device.h> 20#include <linux/err.h> 21#include <linux/spinlock.h> 22#include <linux/delay.h> 23#include <linux/interrupt.h> 24#include <linux/io.h> 25#include <linux/clk.h> 26#include <linux/list.h> 27#include <linux/irq.h> 28#include <linux/irqchip/chained_irq.h> 29#include <linux/irqdomain.h> 30#include <linux/of_device.h> 31 32#include <drm/drm_fourcc.h> 33 34#include <video/imx-ipu-v3.h> 35#include "ipu-prv.h" 36 37static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) 38{ 39 return readl(ipu->cm_reg + offset); 40} 41 42static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) 43{ 44 writel(value, ipu->cm_reg + offset); 45} 46 47void ipu_srm_dp_sync_update(struct ipu_soc *ipu) 48{ 49 u32 val; 50 51 val = ipu_cm_read(ipu, IPU_SRM_PRI2); 52 val |= 0x8; 53 ipu_cm_write(ipu, val, IPU_SRM_PRI2); 54} 55EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update); 56 57enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc) 58{ 59 switch (drm_fourcc) { 60 case DRM_FORMAT_RGB565: 61 case DRM_FORMAT_BGR565: 62 case DRM_FORMAT_RGB888: 63 case DRM_FORMAT_BGR888: 64 case DRM_FORMAT_XRGB8888: 65 case DRM_FORMAT_XBGR8888: 66 case DRM_FORMAT_RGBX8888: 67 case DRM_FORMAT_BGRX8888: 68 case DRM_FORMAT_ARGB8888: 69 case DRM_FORMAT_ABGR8888: 70 case DRM_FORMAT_RGBA8888: 71 case DRM_FORMAT_BGRA8888: 72 return IPUV3_COLORSPACE_RGB; 73 case DRM_FORMAT_YUYV: 74 case DRM_FORMAT_UYVY: 75 case DRM_FORMAT_YUV420: 76 case DRM_FORMAT_YVU420: 77 case DRM_FORMAT_YUV422: 78 case DRM_FORMAT_YVU422: 79 case DRM_FORMAT_NV12: 80 case DRM_FORMAT_NV21: 81 case DRM_FORMAT_NV16: 82 case DRM_FORMAT_NV61: 83 return IPUV3_COLORSPACE_YUV; 84 default: 85 return IPUV3_COLORSPACE_UNKNOWN; 86 } 87} 88EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace); 89 90enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat) 91{ 92 switch (pixelformat) { 93 case V4L2_PIX_FMT_YUV420: 94 case V4L2_PIX_FMT_YVU420: 95 case V4L2_PIX_FMT_YUV422P: 96 case V4L2_PIX_FMT_UYVY: 97 case V4L2_PIX_FMT_YUYV: 98 case V4L2_PIX_FMT_NV12: 99 case V4L2_PIX_FMT_NV21: 100 case V4L2_PIX_FMT_NV16: 101 case V4L2_PIX_FMT_NV61: 102 return IPUV3_COLORSPACE_YUV; 103 case V4L2_PIX_FMT_RGB32: 104 case V4L2_PIX_FMT_BGR32: 105 case V4L2_PIX_FMT_RGB24: 106 case V4L2_PIX_FMT_BGR24: 107 case V4L2_PIX_FMT_RGB565: 108 return IPUV3_COLORSPACE_RGB; 109 default: 110 return IPUV3_COLORSPACE_UNKNOWN; 111 } 112} 113EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace); 114 115bool ipu_pixelformat_is_planar(u32 pixelformat) 116{ 117 switch (pixelformat) { 118 case V4L2_PIX_FMT_YUV420: 119 case V4L2_PIX_FMT_YVU420: 120 case V4L2_PIX_FMT_YUV422P: 121 case V4L2_PIX_FMT_NV12: 122 case V4L2_PIX_FMT_NV21: 123 case V4L2_PIX_FMT_NV16: 124 case V4L2_PIX_FMT_NV61: 125 return true; 126 } 127 128 return false; 129} 130EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar); 131 132enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code) 133{ 134 switch (mbus_code & 0xf000) { 135 case 0x1000: 136 return IPUV3_COLORSPACE_RGB; 137 case 0x2000: 138 return IPUV3_COLORSPACE_YUV; 139 default: 140 return IPUV3_COLORSPACE_UNKNOWN; 141 } 142} 143EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace); 144 145int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat) 146{ 147 switch (pixelformat) { 148 case V4L2_PIX_FMT_YUV420: 149 case V4L2_PIX_FMT_YVU420: 150 case V4L2_PIX_FMT_YUV422P: 151 case V4L2_PIX_FMT_NV12: 152 case V4L2_PIX_FMT_NV21: 153 case V4L2_PIX_FMT_NV16: 154 case V4L2_PIX_FMT_NV61: 155 /* 156 * for the planar YUV formats, the stride passed to 157 * cpmem must be the stride in bytes of the Y plane. 158 * And all the planar YUV formats have an 8-bit 159 * Y component. 160 */ 161 return (8 * pixel_stride) >> 3; 162 case V4L2_PIX_FMT_RGB565: 163 case V4L2_PIX_FMT_YUYV: 164 case V4L2_PIX_FMT_UYVY: 165 return (16 * pixel_stride) >> 3; 166 case V4L2_PIX_FMT_BGR24: 167 case V4L2_PIX_FMT_RGB24: 168 return (24 * pixel_stride) >> 3; 169 case V4L2_PIX_FMT_BGR32: 170 case V4L2_PIX_FMT_RGB32: 171 return (32 * pixel_stride) >> 3; 172 default: 173 break; 174 } 175 176 return -EINVAL; 177} 178EXPORT_SYMBOL_GPL(ipu_stride_to_bytes); 179 180int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, 181 bool hflip, bool vflip) 182{ 183 u32 r90, vf, hf; 184 185 switch (degrees) { 186 case 0: 187 vf = hf = r90 = 0; 188 break; 189 case 90: 190 vf = hf = 0; 191 r90 = 1; 192 break; 193 case 180: 194 vf = hf = 1; 195 r90 = 0; 196 break; 197 case 270: 198 vf = hf = r90 = 1; 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 hf ^= (u32)hflip; 205 vf ^= (u32)vflip; 206 207 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf); 208 return 0; 209} 210EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode); 211 212int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, 213 bool hflip, bool vflip) 214{ 215 u32 r90, vf, hf; 216 217 r90 = ((u32)mode >> 2) & 0x1; 218 hf = ((u32)mode >> 1) & 0x1; 219 vf = ((u32)mode >> 0) & 0x1; 220 hf ^= (u32)hflip; 221 vf ^= (u32)vflip; 222 223 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) { 224 case IPU_ROTATE_NONE: 225 *degrees = 0; 226 break; 227 case IPU_ROTATE_90_RIGHT: 228 *degrees = 90; 229 break; 230 case IPU_ROTATE_180: 231 *degrees = 180; 232 break; 233 case IPU_ROTATE_90_LEFT: 234 *degrees = 270; 235 break; 236 default: 237 return -EINVAL; 238 } 239 240 return 0; 241} 242EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees); 243 244struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) 245{ 246 struct ipuv3_channel *channel; 247 248 dev_dbg(ipu->dev, "%s %d\n", __func__, num); 249 250 if (num > 63) 251 return ERR_PTR(-ENODEV); 252 253 mutex_lock(&ipu->channel_lock); 254 255 channel = &ipu->channel[num]; 256 257 if (channel->busy) { 258 channel = ERR_PTR(-EBUSY); 259 goto out; 260 } 261 262 channel->busy = true; 263 channel->num = num; 264 265out: 266 mutex_unlock(&ipu->channel_lock); 267 268 return channel; 269} 270EXPORT_SYMBOL_GPL(ipu_idmac_get); 271 272void ipu_idmac_put(struct ipuv3_channel *channel) 273{ 274 struct ipu_soc *ipu = channel->ipu; 275 276 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); 277 278 mutex_lock(&ipu->channel_lock); 279 280 channel->busy = false; 281 282 mutex_unlock(&ipu->channel_lock); 283} 284EXPORT_SYMBOL_GPL(ipu_idmac_put); 285 286#define idma_mask(ch) (1 << ((ch) & 0x1f)) 287 288/* 289 * This is an undocumented feature, a write one to a channel bit in 290 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's 291 * internal current buffer pointer so that transfers start from buffer 292 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM 293 * only says these are read-only registers). This operation is required 294 * for channel linking to work correctly, for instance video capture 295 * pipelines that carry out image rotations will fail after the first 296 * streaming unless this function is called for each channel before 297 * re-enabling the channels. 298 */ 299static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel) 300{ 301 struct ipu_soc *ipu = channel->ipu; 302 unsigned int chno = channel->num; 303 304 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); 305} 306 307void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, 308 bool doublebuffer) 309{ 310 struct ipu_soc *ipu = channel->ipu; 311 unsigned long flags; 312 u32 reg; 313 314 spin_lock_irqsave(&ipu->lock, flags); 315 316 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 317 if (doublebuffer) 318 reg |= idma_mask(channel->num); 319 else 320 reg &= ~idma_mask(channel->num); 321 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); 322 323 __ipu_idmac_reset_current_buffer(channel); 324 325 spin_unlock_irqrestore(&ipu->lock, flags); 326} 327EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer); 328 329static const struct { 330 int chnum; 331 u32 reg; 332 int shift; 333} idmac_lock_en_info[] = { 334 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, }, 335 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, }, 336 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, }, 337 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, }, 338 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, }, 339 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, }, 340 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, }, 341 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, }, 342 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, }, 343 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, }, 344 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, }, 345 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, }, 346 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, }, 347 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, }, 348 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, }, 349 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, }, 350 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, }, 351}; 352 353int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts) 354{ 355 struct ipu_soc *ipu = channel->ipu; 356 unsigned long flags; 357 u32 bursts, regval; 358 int i; 359 360 switch (num_bursts) { 361 case 0: 362 case 1: 363 bursts = 0x00; /* locking disabled */ 364 break; 365 case 2: 366 bursts = 0x01; 367 break; 368 case 4: 369 bursts = 0x02; 370 break; 371 case 8: 372 bursts = 0x03; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) { 379 if (channel->num == idmac_lock_en_info[i].chnum) 380 break; 381 } 382 if (i >= ARRAY_SIZE(idmac_lock_en_info)) 383 return -EINVAL; 384 385 spin_lock_irqsave(&ipu->lock, flags); 386 387 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); 388 regval &= ~(0x03 << idmac_lock_en_info[i].shift); 389 regval |= (bursts << idmac_lock_en_info[i].shift); 390 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); 391 392 spin_unlock_irqrestore(&ipu->lock, flags); 393 394 return 0; 395} 396EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable); 397 398int ipu_module_enable(struct ipu_soc *ipu, u32 mask) 399{ 400 unsigned long lock_flags; 401 u32 val; 402 403 spin_lock_irqsave(&ipu->lock, lock_flags); 404 405 val = ipu_cm_read(ipu, IPU_DISP_GEN); 406 407 if (mask & IPU_CONF_DI0_EN) 408 val |= IPU_DI0_COUNTER_RELEASE; 409 if (mask & IPU_CONF_DI1_EN) 410 val |= IPU_DI1_COUNTER_RELEASE; 411 412 ipu_cm_write(ipu, val, IPU_DISP_GEN); 413 414 val = ipu_cm_read(ipu, IPU_CONF); 415 val |= mask; 416 ipu_cm_write(ipu, val, IPU_CONF); 417 418 spin_unlock_irqrestore(&ipu->lock, lock_flags); 419 420 return 0; 421} 422EXPORT_SYMBOL_GPL(ipu_module_enable); 423 424int ipu_module_disable(struct ipu_soc *ipu, u32 mask) 425{ 426 unsigned long lock_flags; 427 u32 val; 428 429 spin_lock_irqsave(&ipu->lock, lock_flags); 430 431 val = ipu_cm_read(ipu, IPU_CONF); 432 val &= ~mask; 433 ipu_cm_write(ipu, val, IPU_CONF); 434 435 val = ipu_cm_read(ipu, IPU_DISP_GEN); 436 437 if (mask & IPU_CONF_DI0_EN) 438 val &= ~IPU_DI0_COUNTER_RELEASE; 439 if (mask & IPU_CONF_DI1_EN) 440 val &= ~IPU_DI1_COUNTER_RELEASE; 441 442 ipu_cm_write(ipu, val, IPU_DISP_GEN); 443 444 spin_unlock_irqrestore(&ipu->lock, lock_flags); 445 446 return 0; 447} 448EXPORT_SYMBOL_GPL(ipu_module_disable); 449 450int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel) 451{ 452 struct ipu_soc *ipu = channel->ipu; 453 unsigned int chno = channel->num; 454 455 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; 456} 457EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer); 458 459bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num) 460{ 461 struct ipu_soc *ipu = channel->ipu; 462 unsigned long flags; 463 u32 reg = 0; 464 465 spin_lock_irqsave(&ipu->lock, flags); 466 switch (buf_num) { 467 case 0: 468 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); 469 break; 470 case 1: 471 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); 472 break; 473 case 2: 474 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); 475 break; 476 } 477 spin_unlock_irqrestore(&ipu->lock, flags); 478 479 return ((reg & idma_mask(channel->num)) != 0); 480} 481EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready); 482 483void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num) 484{ 485 struct ipu_soc *ipu = channel->ipu; 486 unsigned int chno = channel->num; 487 unsigned long flags; 488 489 spin_lock_irqsave(&ipu->lock, flags); 490 491 /* Mark buffer as ready. */ 492 if (buf_num == 0) 493 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 494 else 495 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 496 497 spin_unlock_irqrestore(&ipu->lock, flags); 498} 499EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer); 500 501void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num) 502{ 503 struct ipu_soc *ipu = channel->ipu; 504 unsigned int chno = channel->num; 505 unsigned long flags; 506 507 spin_lock_irqsave(&ipu->lock, flags); 508 509 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ 510 switch (buf_num) { 511 case 0: 512 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); 513 break; 514 case 1: 515 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); 516 break; 517 case 2: 518 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); 519 break; 520 default: 521 break; 522 } 523 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 524 525 spin_unlock_irqrestore(&ipu->lock, flags); 526} 527EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer); 528 529int ipu_idmac_enable_channel(struct ipuv3_channel *channel) 530{ 531 struct ipu_soc *ipu = channel->ipu; 532 u32 val; 533 unsigned long flags; 534 535 spin_lock_irqsave(&ipu->lock, flags); 536 537 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 538 val |= idma_mask(channel->num); 539 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 540 541 spin_unlock_irqrestore(&ipu->lock, flags); 542 543 return 0; 544} 545EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel); 546 547bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) 548{ 549 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); 550} 551EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy); 552 553int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms) 554{ 555 struct ipu_soc *ipu = channel->ipu; 556 unsigned long timeout; 557 558 timeout = jiffies + msecs_to_jiffies(ms); 559 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & 560 idma_mask(channel->num)) { 561 if (time_after(jiffies, timeout)) 562 return -ETIMEDOUT; 563 cpu_relax(); 564 } 565 566 return 0; 567} 568EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy); 569 570int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms) 571{ 572 unsigned long timeout; 573 574 timeout = jiffies + msecs_to_jiffies(ms); 575 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32)); 576 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) { 577 if (time_after(jiffies, timeout)) 578 return -ETIMEDOUT; 579 cpu_relax(); 580 } 581 582 return 0; 583} 584EXPORT_SYMBOL_GPL(ipu_wait_interrupt); 585 586int ipu_idmac_disable_channel(struct ipuv3_channel *channel) 587{ 588 struct ipu_soc *ipu = channel->ipu; 589 u32 val; 590 unsigned long flags; 591 592 spin_lock_irqsave(&ipu->lock, flags); 593 594 /* Disable DMA channel(s) */ 595 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); 596 val &= ~idma_mask(channel->num); 597 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); 598 599 __ipu_idmac_reset_current_buffer(channel); 600 601 /* Set channel buffers NOT to be ready */ 602 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ 603 604 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & 605 idma_mask(channel->num)) { 606 ipu_cm_write(ipu, idma_mask(channel->num), 607 IPU_CHA_BUF0_RDY(channel->num)); 608 } 609 610 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & 611 idma_mask(channel->num)) { 612 ipu_cm_write(ipu, idma_mask(channel->num), 613 IPU_CHA_BUF1_RDY(channel->num)); 614 } 615 616 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ 617 618 /* Reset the double buffer */ 619 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); 620 val &= ~idma_mask(channel->num); 621 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); 622 623 spin_unlock_irqrestore(&ipu->lock, flags); 624 625 return 0; 626} 627EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel); 628 629/* 630 * The imx6 rev. D TRM says that enabling the WM feature will increase 631 * a channel's priority. Refer to Table 36-8 Calculated priority value. 632 * The sub-module that is the sink or source for the channel must enable 633 * watermark signal for this to take effect (SMFC_WM for instance). 634 */ 635void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable) 636{ 637 struct ipu_soc *ipu = channel->ipu; 638 unsigned long flags; 639 u32 val; 640 641 spin_lock_irqsave(&ipu->lock, flags); 642 643 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); 644 if (enable) 645 val |= 1 << (channel->num % 32); 646 else 647 val &= ~(1 << (channel->num % 32)); 648 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); 649 650 spin_unlock_irqrestore(&ipu->lock, flags); 651} 652EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark); 653 654static int ipu_memory_reset(struct ipu_soc *ipu) 655{ 656 unsigned long timeout; 657 658 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); 659 660 timeout = jiffies + msecs_to_jiffies(1000); 661 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { 662 if (time_after(jiffies, timeout)) 663 return -ETIME; 664 cpu_relax(); 665 } 666 667 return 0; 668} 669 670/* 671 * Set the source mux for the given CSI. Selects either parallel or 672 * MIPI CSI2 sources. 673 */ 674void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) 675{ 676 unsigned long flags; 677 u32 val, mask; 678 679 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : 680 IPU_CONF_CSI0_DATA_SOURCE; 681 682 spin_lock_irqsave(&ipu->lock, flags); 683 684 val = ipu_cm_read(ipu, IPU_CONF); 685 if (mipi_csi2) 686 val |= mask; 687 else 688 val &= ~mask; 689 ipu_cm_write(ipu, val, IPU_CONF); 690 691 spin_unlock_irqrestore(&ipu->lock, flags); 692} 693EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux); 694 695/* 696 * Set the source mux for the IC. Selects either CSI[01] or the VDI. 697 */ 698void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) 699{ 700 unsigned long flags; 701 u32 val; 702 703 spin_lock_irqsave(&ipu->lock, flags); 704 705 val = ipu_cm_read(ipu, IPU_CONF); 706 if (vdi) { 707 val |= IPU_CONF_IC_INPUT; 708 } else { 709 val &= ~IPU_CONF_IC_INPUT; 710 if (csi_id == 1) 711 val |= IPU_CONF_CSI_SEL; 712 else 713 val &= ~IPU_CONF_CSI_SEL; 714 } 715 ipu_cm_write(ipu, val, IPU_CONF); 716 717 spin_unlock_irqrestore(&ipu->lock, flags); 718} 719EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux); 720 721struct ipu_devtype { 722 const char *name; 723 unsigned long cm_ofs; 724 unsigned long cpmem_ofs; 725 unsigned long srm_ofs; 726 unsigned long tpm_ofs; 727 unsigned long csi0_ofs; 728 unsigned long csi1_ofs; 729 unsigned long ic_ofs; 730 unsigned long disp0_ofs; 731 unsigned long disp1_ofs; 732 unsigned long dc_tmpl_ofs; 733 unsigned long vdi_ofs; 734 enum ipuv3_type type; 735}; 736 737static struct ipu_devtype ipu_type_imx51 = { 738 .name = "IPUv3EX", 739 .cm_ofs = 0x1e000000, 740 .cpmem_ofs = 0x1f000000, 741 .srm_ofs = 0x1f040000, 742 .tpm_ofs = 0x1f060000, 743 .csi0_ofs = 0x1f030000, 744 .csi1_ofs = 0x1f038000, 745 .ic_ofs = 0x1e020000, 746 .disp0_ofs = 0x1e040000, 747 .disp1_ofs = 0x1e048000, 748 .dc_tmpl_ofs = 0x1f080000, 749 .vdi_ofs = 0x1e068000, 750 .type = IPUV3EX, 751}; 752 753static struct ipu_devtype ipu_type_imx53 = { 754 .name = "IPUv3M", 755 .cm_ofs = 0x06000000, 756 .cpmem_ofs = 0x07000000, 757 .srm_ofs = 0x07040000, 758 .tpm_ofs = 0x07060000, 759 .csi0_ofs = 0x07030000, 760 .csi1_ofs = 0x07038000, 761 .ic_ofs = 0x06020000, 762 .disp0_ofs = 0x06040000, 763 .disp1_ofs = 0x06048000, 764 .dc_tmpl_ofs = 0x07080000, 765 .vdi_ofs = 0x06068000, 766 .type = IPUV3M, 767}; 768 769static struct ipu_devtype ipu_type_imx6q = { 770 .name = "IPUv3H", 771 .cm_ofs = 0x00200000, 772 .cpmem_ofs = 0x00300000, 773 .srm_ofs = 0x00340000, 774 .tpm_ofs = 0x00360000, 775 .csi0_ofs = 0x00230000, 776 .csi1_ofs = 0x00238000, 777 .ic_ofs = 0x00220000, 778 .disp0_ofs = 0x00240000, 779 .disp1_ofs = 0x00248000, 780 .dc_tmpl_ofs = 0x00380000, 781 .vdi_ofs = 0x00268000, 782 .type = IPUV3H, 783}; 784 785static const struct of_device_id imx_ipu_dt_ids[] = { 786 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, }, 787 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, }, 788 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, }, 789 { /* sentinel */ } 790}; 791MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids); 792 793static int ipu_submodules_init(struct ipu_soc *ipu, 794 struct platform_device *pdev, unsigned long ipu_base, 795 struct clk *ipu_clk) 796{ 797 char *unit; 798 int ret; 799 struct device *dev = &pdev->dev; 800 const struct ipu_devtype *devtype = ipu->devtype; 801 802 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); 803 if (ret) { 804 unit = "cpmem"; 805 goto err_cpmem; 806 } 807 808 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, 809 IPU_CONF_CSI0_EN, ipu_clk); 810 if (ret) { 811 unit = "csi0"; 812 goto err_csi_0; 813 } 814 815 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, 816 IPU_CONF_CSI1_EN, ipu_clk); 817 if (ret) { 818 unit = "csi1"; 819 goto err_csi_1; 820 } 821 822 ret = ipu_ic_init(ipu, dev, 823 ipu_base + devtype->ic_ofs, 824 ipu_base + devtype->tpm_ofs); 825 if (ret) { 826 unit = "ic"; 827 goto err_ic; 828 } 829 830 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, 831 IPU_CONF_DI0_EN, ipu_clk); 832 if (ret) { 833 unit = "di0"; 834 goto err_di_0; 835 } 836 837 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, 838 IPU_CONF_DI1_EN, ipu_clk); 839 if (ret) { 840 unit = "di1"; 841 goto err_di_1; 842 } 843 844 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + 845 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs); 846 if (ret) { 847 unit = "dc_template"; 848 goto err_dc; 849 } 850 851 ret = ipu_dmfc_init(ipu, dev, ipu_base + 852 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk); 853 if (ret) { 854 unit = "dmfc"; 855 goto err_dmfc; 856 } 857 858 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); 859 if (ret) { 860 unit = "dp"; 861 goto err_dp; 862 } 863 864 ret = ipu_smfc_init(ipu, dev, ipu_base + 865 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS); 866 if (ret) { 867 unit = "smfc"; 868 goto err_smfc; 869 } 870 871 return 0; 872 873err_smfc: 874 ipu_dp_exit(ipu); 875err_dp: 876 ipu_dmfc_exit(ipu); 877err_dmfc: 878 ipu_dc_exit(ipu); 879err_dc: 880 ipu_di_exit(ipu, 1); 881err_di_1: 882 ipu_di_exit(ipu, 0); 883err_di_0: 884 ipu_ic_exit(ipu); 885err_ic: 886 ipu_csi_exit(ipu, 1); 887err_csi_1: 888 ipu_csi_exit(ipu, 0); 889err_csi_0: 890 ipu_cpmem_exit(ipu); 891err_cpmem: 892 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); 893 return ret; 894} 895 896static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) 897{ 898 unsigned long status; 899 int i, bit, irq; 900 901 for (i = 0; i < num_regs; i++) { 902 903 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); 904 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); 905 906 for_each_set_bit(bit, &status, 32) { 907 irq = irq_linear_revmap(ipu->domain, 908 regs[i] * 32 + bit); 909 if (irq) 910 generic_handle_irq(irq); 911 } 912 } 913} 914 915static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc) 916{ 917 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 918 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14}; 919 struct irq_chip *chip = irq_get_chip(irq); 920 921 chained_irq_enter(chip, desc); 922 923 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 924 925 chained_irq_exit(chip, desc); 926} 927 928static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc) 929{ 930 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); 931 const int int_reg[] = { 4, 5, 8, 9}; 932 struct irq_chip *chip = irq_get_chip(irq); 933 934 chained_irq_enter(chip, desc); 935 936 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); 937 938 chained_irq_exit(chip, desc); 939} 940 941int ipu_map_irq(struct ipu_soc *ipu, int irq) 942{ 943 int virq; 944 945 virq = irq_linear_revmap(ipu->domain, irq); 946 if (!virq) 947 virq = irq_create_mapping(ipu->domain, irq); 948 949 return virq; 950} 951EXPORT_SYMBOL_GPL(ipu_map_irq); 952 953int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, 954 enum ipu_channel_irq irq_type) 955{ 956 return ipu_map_irq(ipu, irq_type + channel->num); 957} 958EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq); 959 960static void ipu_submodules_exit(struct ipu_soc *ipu) 961{ 962 ipu_smfc_exit(ipu); 963 ipu_dp_exit(ipu); 964 ipu_dmfc_exit(ipu); 965 ipu_dc_exit(ipu); 966 ipu_di_exit(ipu, 1); 967 ipu_di_exit(ipu, 0); 968 ipu_ic_exit(ipu); 969 ipu_csi_exit(ipu, 1); 970 ipu_csi_exit(ipu, 0); 971 ipu_cpmem_exit(ipu); 972} 973 974static int platform_remove_devices_fn(struct device *dev, void *unused) 975{ 976 struct platform_device *pdev = to_platform_device(dev); 977 978 platform_device_unregister(pdev); 979 980 return 0; 981} 982 983static void platform_device_unregister_children(struct platform_device *pdev) 984{ 985 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn); 986} 987 988struct ipu_platform_reg { 989 struct ipu_client_platformdata pdata; 990 const char *name; 991 int reg_offset; 992}; 993 994static const struct ipu_platform_reg client_reg[] = { 995 { 996 .pdata = { 997 .di = 0, 998 .dc = 5, 999 .dp = IPU_DP_FLOW_SYNC_BG, 1000 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC, 1001 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC, 1002 }, 1003 .name = "imx-ipuv3-crtc", 1004 }, { 1005 .pdata = { 1006 .di = 1, 1007 .dc = 1, 1008 .dp = -EINVAL, 1009 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC, 1010 .dma[1] = -EINVAL, 1011 }, 1012 .name = "imx-ipuv3-crtc", 1013 }, { 1014 .pdata = { 1015 .csi = 0, 1016 .dma[0] = IPUV3_CHANNEL_CSI0, 1017 .dma[1] = -EINVAL, 1018 }, 1019 .reg_offset = IPU_CM_CSI0_REG_OFS, 1020 .name = "imx-ipuv3-camera", 1021 }, { 1022 .pdata = { 1023 .csi = 1, 1024 .dma[0] = IPUV3_CHANNEL_CSI1, 1025 .dma[1] = -EINVAL, 1026 }, 1027 .reg_offset = IPU_CM_CSI1_REG_OFS, 1028 .name = "imx-ipuv3-camera", 1029 }, 1030}; 1031 1032static DEFINE_MUTEX(ipu_client_id_mutex); 1033static int ipu_client_id; 1034 1035static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) 1036{ 1037 struct device *dev = ipu->dev; 1038 unsigned i; 1039 int id, ret; 1040 1041 mutex_lock(&ipu_client_id_mutex); 1042 id = ipu_client_id; 1043 ipu_client_id += ARRAY_SIZE(client_reg); 1044 mutex_unlock(&ipu_client_id_mutex); 1045 1046 for (i = 0; i < ARRAY_SIZE(client_reg); i++) { 1047 const struct ipu_platform_reg *reg = &client_reg[i]; 1048 struct platform_device *pdev; 1049 struct resource res; 1050 1051 if (reg->reg_offset) { 1052 memset(&res, 0, sizeof(res)); 1053 res.flags = IORESOURCE_MEM; 1054 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset; 1055 res.end = res.start + PAGE_SIZE - 1; 1056 pdev = platform_device_register_resndata(dev, reg->name, 1057 id++, &res, 1, ®->pdata, sizeof(reg->pdata)); 1058 } else { 1059 pdev = platform_device_register_data(dev, reg->name, 1060 id++, ®->pdata, sizeof(reg->pdata)); 1061 } 1062 1063 if (IS_ERR(pdev)) { 1064 ret = PTR_ERR(pdev); 1065 goto err_register; 1066 } 1067 } 1068 1069 return 0; 1070 1071err_register: 1072 platform_device_unregister_children(to_platform_device(dev)); 1073 1074 return ret; 1075} 1076 1077 1078static int ipu_irq_init(struct ipu_soc *ipu) 1079{ 1080 struct irq_chip_generic *gc; 1081 struct irq_chip_type *ct; 1082 unsigned long unused[IPU_NUM_IRQS / 32] = { 1083 0x400100d0, 0xffe000fd, 1084 0x400100d0, 0xffe000fd, 1085 0x400100d0, 0xffe000fd, 1086 0x4077ffff, 0xffe7e1fd, 1087 0x23fffffe, 0x8880fff0, 1088 0xf98fe7d0, 0xfff81fff, 1089 0x400100d0, 0xffe000fd, 1090 0x00000000, 1091 }; 1092 int ret, i; 1093 1094 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, 1095 &irq_generic_chip_ops, ipu); 1096 if (!ipu->domain) { 1097 dev_err(ipu->dev, "failed to add irq domain\n"); 1098 return -ENODEV; 1099 } 1100 1101 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", 1102 handle_level_irq, 0, 1103 IRQF_VALID, 0); 1104 if (ret < 0) { 1105 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); 1106 irq_domain_remove(ipu->domain); 1107 return ret; 1108 } 1109 1110 for (i = 0; i < IPU_NUM_IRQS; i += 32) { 1111 gc = irq_get_domain_generic_chip(ipu->domain, i); 1112 gc->reg_base = ipu->cm_reg; 1113 gc->unused = unused[i / 32]; 1114 ct = gc->chip_types; 1115 ct->chip.irq_ack = irq_gc_ack_set_bit; 1116 ct->chip.irq_mask = irq_gc_mask_clr_bit; 1117 ct->chip.irq_unmask = irq_gc_mask_set_bit; 1118 ct->regs.ack = IPU_INT_STAT(i / 32); 1119 ct->regs.mask = IPU_INT_CTRL(i / 32); 1120 } 1121 1122 irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler); 1123 irq_set_handler_data(ipu->irq_sync, ipu); 1124 irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler); 1125 irq_set_handler_data(ipu->irq_err, ipu); 1126 1127 return 0; 1128} 1129 1130static void ipu_irq_exit(struct ipu_soc *ipu) 1131{ 1132 int i, irq; 1133 1134 irq_set_chained_handler(ipu->irq_err, NULL); 1135 irq_set_handler_data(ipu->irq_err, NULL); 1136 irq_set_chained_handler(ipu->irq_sync, NULL); 1137 irq_set_handler_data(ipu->irq_sync, NULL); 1138 1139 /* TODO: remove irq_domain_generic_chips */ 1140 1141 for (i = 0; i < IPU_NUM_IRQS; i++) { 1142 irq = irq_linear_revmap(ipu->domain, i); 1143 if (irq) 1144 irq_dispose_mapping(irq); 1145 } 1146 1147 irq_domain_remove(ipu->domain); 1148} 1149 1150void ipu_dump(struct ipu_soc *ipu) 1151{ 1152 int i; 1153 1154 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", 1155 ipu_cm_read(ipu, IPU_CONF)); 1156 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", 1157 ipu_idmac_read(ipu, IDMAC_CONF)); 1158 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", 1159 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); 1160 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", 1161 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); 1162 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", 1163 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); 1164 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", 1165 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); 1166 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", 1167 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); 1168 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", 1169 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); 1170 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", 1171 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); 1172 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", 1173 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); 1174 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", 1175 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); 1176 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", 1177 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); 1178 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", 1179 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); 1180 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", 1181 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); 1182 for (i = 0; i < 15; i++) 1183 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, 1184 ipu_cm_read(ipu, IPU_INT_CTRL(i))); 1185} 1186EXPORT_SYMBOL_GPL(ipu_dump); 1187 1188static int ipu_probe(struct platform_device *pdev) 1189{ 1190 const struct of_device_id *of_id = 1191 of_match_device(imx_ipu_dt_ids, &pdev->dev); 1192 struct ipu_soc *ipu; 1193 struct resource *res; 1194 unsigned long ipu_base; 1195 int i, ret, irq_sync, irq_err; 1196 const struct ipu_devtype *devtype; 1197 1198 devtype = of_id->data; 1199 1200 irq_sync = platform_get_irq(pdev, 0); 1201 irq_err = platform_get_irq(pdev, 1); 1202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1203 1204 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n", 1205 irq_sync, irq_err); 1206 1207 if (!res || irq_sync < 0 || irq_err < 0) 1208 return -ENODEV; 1209 1210 ipu_base = res->start; 1211 1212 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); 1213 if (!ipu) 1214 return -ENODEV; 1215 1216 for (i = 0; i < 64; i++) 1217 ipu->channel[i].ipu = ipu; 1218 ipu->devtype = devtype; 1219 ipu->ipu_type = devtype->type; 1220 1221 spin_lock_init(&ipu->lock); 1222 mutex_init(&ipu->channel_lock); 1223 1224 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n", 1225 ipu_base + devtype->cm_ofs); 1226 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n", 1227 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); 1228 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", 1229 ipu_base + devtype->cpmem_ofs); 1230 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n", 1231 ipu_base + devtype->csi0_ofs); 1232 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n", 1233 ipu_base + devtype->csi1_ofs); 1234 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1235 ipu_base + devtype->ic_ofs); 1236 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", 1237 ipu_base + devtype->disp0_ofs); 1238 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", 1239 ipu_base + devtype->disp1_ofs); 1240 dev_dbg(&pdev->dev, "srm: 0x%08lx\n", 1241 ipu_base + devtype->srm_ofs); 1242 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n", 1243 ipu_base + devtype->tpm_ofs); 1244 dev_dbg(&pdev->dev, "dc: 0x%08lx\n", 1245 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS); 1246 dev_dbg(&pdev->dev, "ic: 0x%08lx\n", 1247 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS); 1248 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n", 1249 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS); 1250 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n", 1251 ipu_base + devtype->vdi_ofs); 1252 1253 ipu->cm_reg = devm_ioremap(&pdev->dev, 1254 ipu_base + devtype->cm_ofs, PAGE_SIZE); 1255 ipu->idmac_reg = devm_ioremap(&pdev->dev, 1256 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS, 1257 PAGE_SIZE); 1258 1259 if (!ipu->cm_reg || !ipu->idmac_reg) 1260 return -ENOMEM; 1261 1262 ipu->clk = devm_clk_get(&pdev->dev, "bus"); 1263 if (IS_ERR(ipu->clk)) { 1264 ret = PTR_ERR(ipu->clk); 1265 dev_err(&pdev->dev, "clk_get failed with %d", ret); 1266 return ret; 1267 } 1268 1269 platform_set_drvdata(pdev, ipu); 1270 1271 ret = clk_prepare_enable(ipu->clk); 1272 if (ret) { 1273 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1274 return ret; 1275 } 1276 1277 ipu->dev = &pdev->dev; 1278 ipu->irq_sync = irq_sync; 1279 ipu->irq_err = irq_err; 1280 1281 ret = ipu_irq_init(ipu); 1282 if (ret) 1283 goto out_failed_irq; 1284 1285 ret = device_reset(&pdev->dev); 1286 if (ret) { 1287 dev_err(&pdev->dev, "failed to reset: %d\n", ret); 1288 goto out_failed_reset; 1289 } 1290 ret = ipu_memory_reset(ipu); 1291 if (ret) 1292 goto out_failed_reset; 1293 1294 /* Set MCU_T to divide MCU access window into 2 */ 1295 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), 1296 IPU_DISP_GEN); 1297 1298 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); 1299 if (ret) 1300 goto failed_submodules_init; 1301 1302 ret = ipu_add_client_devices(ipu, ipu_base); 1303 if (ret) { 1304 dev_err(&pdev->dev, "adding client devices failed with %d\n", 1305 ret); 1306 goto failed_add_clients; 1307 } 1308 1309 dev_info(&pdev->dev, "%s probed\n", devtype->name); 1310 1311 return 0; 1312 1313failed_add_clients: 1314 ipu_submodules_exit(ipu); 1315failed_submodules_init: 1316out_failed_reset: 1317 ipu_irq_exit(ipu); 1318out_failed_irq: 1319 clk_disable_unprepare(ipu->clk); 1320 return ret; 1321} 1322 1323static int ipu_remove(struct platform_device *pdev) 1324{ 1325 struct ipu_soc *ipu = platform_get_drvdata(pdev); 1326 1327 platform_device_unregister_children(pdev); 1328 ipu_submodules_exit(ipu); 1329 ipu_irq_exit(ipu); 1330 1331 clk_disable_unprepare(ipu->clk); 1332 1333 return 0; 1334} 1335 1336static struct platform_driver imx_ipu_driver = { 1337 .driver = { 1338 .name = "imx-ipuv3", 1339 .of_match_table = imx_ipu_dt_ids, 1340 }, 1341 .probe = ipu_probe, 1342 .remove = ipu_remove, 1343}; 1344 1345module_platform_driver(imx_ipu_driver); 1346 1347MODULE_ALIAS("platform:imx-ipuv3"); 1348MODULE_DESCRIPTION("i.MX IPU v3 driver"); 1349MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 1350MODULE_LICENSE("GPL"); 1351