1/*
2 * PCIe host controller driver for Xilinx AXI PCIe Bridge
3 *
4 * Copyright (c) 2012 - 2014 Xilinx, Inc.
5 *
6 * Based on the Tegra PCIe driver
7 *
8 * Bits taken from Synopsys Designware Host controller driver and
9 * ARM PCI Host generic driver.
10 *
11 * This program is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/msi.h>
23#include <linux/of_address.h>
24#include <linux/of_pci.h>
25#include <linux/of_platform.h>
26#include <linux/of_irq.h>
27#include <linux/pci.h>
28#include <linux/platform_device.h>
29
30/* Register definitions */
31#define XILINX_PCIE_REG_BIR		0x00000130
32#define XILINX_PCIE_REG_IDR		0x00000138
33#define XILINX_PCIE_REG_IMR		0x0000013c
34#define XILINX_PCIE_REG_PSCR		0x00000144
35#define XILINX_PCIE_REG_RPSC		0x00000148
36#define XILINX_PCIE_REG_MSIBASE1	0x0000014c
37#define XILINX_PCIE_REG_MSIBASE2	0x00000150
38#define XILINX_PCIE_REG_RPEFR		0x00000154
39#define XILINX_PCIE_REG_RPIFR1		0x00000158
40#define XILINX_PCIE_REG_RPIFR2		0x0000015c
41
42/* Interrupt registers definitions */
43#define XILINX_PCIE_INTR_LINK_DOWN	BIT(0)
44#define XILINX_PCIE_INTR_ECRC_ERR	BIT(1)
45#define XILINX_PCIE_INTR_STR_ERR	BIT(2)
46#define XILINX_PCIE_INTR_HOT_RESET	BIT(3)
47#define XILINX_PCIE_INTR_CFG_TIMEOUT	BIT(8)
48#define XILINX_PCIE_INTR_CORRECTABLE	BIT(9)
49#define XILINX_PCIE_INTR_NONFATAL	BIT(10)
50#define XILINX_PCIE_INTR_FATAL		BIT(11)
51#define XILINX_PCIE_INTR_INTX		BIT(16)
52#define XILINX_PCIE_INTR_MSI		BIT(17)
53#define XILINX_PCIE_INTR_SLV_UNSUPP	BIT(20)
54#define XILINX_PCIE_INTR_SLV_UNEXP	BIT(21)
55#define XILINX_PCIE_INTR_SLV_COMPL	BIT(22)
56#define XILINX_PCIE_INTR_SLV_ERRP	BIT(23)
57#define XILINX_PCIE_INTR_SLV_CMPABT	BIT(24)
58#define XILINX_PCIE_INTR_SLV_ILLBUR	BIT(25)
59#define XILINX_PCIE_INTR_MST_DECERR	BIT(26)
60#define XILINX_PCIE_INTR_MST_SLVERR	BIT(27)
61#define XILINX_PCIE_INTR_MST_ERRP	BIT(28)
62#define XILINX_PCIE_IMR_ALL_MASK	0x1FF30FED
63#define XILINX_PCIE_IDR_ALL_MASK	0xFFFFFFFF
64
65/* Root Port Error FIFO Read Register definitions */
66#define XILINX_PCIE_RPEFR_ERR_VALID	BIT(18)
67#define XILINX_PCIE_RPEFR_REQ_ID	GENMASK(15, 0)
68#define XILINX_PCIE_RPEFR_ALL_MASK	0xFFFFFFFF
69
70/* Root Port Interrupt FIFO Read Register 1 definitions */
71#define XILINX_PCIE_RPIFR1_INTR_VALID	BIT(31)
72#define XILINX_PCIE_RPIFR1_MSI_INTR	BIT(30)
73#define XILINX_PCIE_RPIFR1_INTR_MASK	GENMASK(28, 27)
74#define XILINX_PCIE_RPIFR1_ALL_MASK	0xFFFFFFFF
75#define XILINX_PCIE_RPIFR1_INTR_SHIFT	27
76
77/* Bridge Info Register definitions */
78#define XILINX_PCIE_BIR_ECAM_SZ_MASK	GENMASK(18, 16)
79#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT	16
80
81/* Root Port Interrupt FIFO Read Register 2 definitions */
82#define XILINX_PCIE_RPIFR2_MSG_DATA	GENMASK(15, 0)
83
84/* Root Port Status/control Register definitions */
85#define XILINX_PCIE_REG_RPSC_BEN	BIT(0)
86
87/* Phy Status/Control Register definitions */
88#define XILINX_PCIE_REG_PSCR_LNKUP	BIT(11)
89
90/* ECAM definitions */
91#define ECAM_BUS_NUM_SHIFT		20
92#define ECAM_DEV_NUM_SHIFT		12
93
94/* Number of MSI IRQs */
95#define XILINX_NUM_MSI_IRQS		128
96
97/* Number of Memory Resources */
98#define XILINX_MAX_NUM_RESOURCES	3
99
100/**
101 * struct xilinx_pcie_port - PCIe port information
102 * @reg_base: IO Mapped Register Base
103 * @irq: Interrupt number
104 * @msi_pages: MSI pages
105 * @root_busno: Root Bus number
106 * @dev: Device pointer
107 * @irq_domain: IRQ domain pointer
108 * @bus_range: Bus range
109 * @resources: Bus Resources
110 */
111struct xilinx_pcie_port {
112	void __iomem *reg_base;
113	u32 irq;
114	unsigned long msi_pages;
115	u8 root_busno;
116	struct device *dev;
117	struct irq_domain *irq_domain;
118	struct resource bus_range;
119	struct list_head resources;
120};
121
122static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
123
124static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
125{
126	return sys->private_data;
127}
128
129static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
130{
131	return readl(port->reg_base + reg);
132}
133
134static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
135{
136	writel(val, port->reg_base + reg);
137}
138
139static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
140{
141	return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
142		XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
143}
144
145/**
146 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
147 * @port: PCIe port information
148 */
149static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
150{
151	unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
152
153	if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
154		dev_dbg(port->dev, "Requester ID %lu\n",
155			val & XILINX_PCIE_RPEFR_REQ_ID);
156		pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
157			   XILINX_PCIE_REG_RPEFR);
158	}
159}
160
161/**
162 * xilinx_pcie_valid_device - Check if a valid device is present on bus
163 * @bus: PCI Bus structure
164 * @devfn: device/function
165 *
166 * Return: 'true' on success and 'false' if invalid device is found
167 */
168static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
169{
170	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
171
172	/* Check if link is up when trying to access downstream ports */
173	if (bus->number != port->root_busno)
174		if (!xilinx_pcie_link_is_up(port))
175			return false;
176
177	/* Only one device down on each root port */
178	if (bus->number == port->root_busno && devfn > 0)
179		return false;
180
181	/*
182	 * Do not read more than one device on the bus directly attached
183	 * to RC.
184	 */
185	if (bus->primary == port->root_busno && devfn > 0)
186		return false;
187
188	return true;
189}
190
191/**
192 * xilinx_pcie_map_bus - Get configuration base
193 * @bus: PCI Bus structure
194 * @devfn: Device/function
195 * @where: Offset from base
196 *
197 * Return: Base address of the configuration space needed to be
198 *	   accessed.
199 */
200static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
201					 unsigned int devfn, int where)
202{
203	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
204	int relbus;
205
206	if (!xilinx_pcie_valid_device(bus, devfn))
207		return NULL;
208
209	relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
210		 (devfn << ECAM_DEV_NUM_SHIFT);
211
212	return port->reg_base + relbus + where;
213}
214
215/* PCIe operations */
216static struct pci_ops xilinx_pcie_ops = {
217	.map_bus = xilinx_pcie_map_bus,
218	.read	= pci_generic_config_read,
219	.write	= pci_generic_config_write,
220};
221
222/* MSI functions */
223
224/**
225 * xilinx_pcie_destroy_msi - Free MSI number
226 * @irq: IRQ to be freed
227 */
228static void xilinx_pcie_destroy_msi(unsigned int irq)
229{
230	struct irq_desc *desc;
231	struct msi_desc *msi;
232	struct xilinx_pcie_port *port;
233
234	desc = irq_to_desc(irq);
235	msi = irq_desc_get_msi_desc(desc);
236	port = sys_to_pcie(msi->dev->bus->sysdata);
237
238	if (!test_bit(irq, msi_irq_in_use))
239		dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
240	else
241		clear_bit(irq, msi_irq_in_use);
242}
243
244/**
245 * xilinx_pcie_assign_msi - Allocate MSI number
246 * @port: PCIe port structure
247 *
248 * Return: A valid IRQ on success and error value on failure.
249 */
250static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
251{
252	int pos;
253
254	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
255	if (pos < XILINX_NUM_MSI_IRQS)
256		set_bit(pos, msi_irq_in_use);
257	else
258		return -ENOSPC;
259
260	return pos;
261}
262
263/**
264 * xilinx_msi_teardown_irq - Destroy the MSI
265 * @chip: MSI Chip descriptor
266 * @irq: MSI IRQ to destroy
267 */
268static void xilinx_msi_teardown_irq(struct msi_controller *chip,
269				    unsigned int irq)
270{
271	xilinx_pcie_destroy_msi(irq);
272}
273
274/**
275 * xilinx_pcie_msi_setup_irq - Setup MSI request
276 * @chip: MSI chip pointer
277 * @pdev: PCIe device pointer
278 * @desc: MSI descriptor pointer
279 *
280 * Return: '0' on success and error value on failure
281 */
282static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
283				     struct pci_dev *pdev,
284				     struct msi_desc *desc)
285{
286	struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
287	unsigned int irq;
288	int hwirq;
289	struct msi_msg msg;
290	phys_addr_t msg_addr;
291
292	hwirq = xilinx_pcie_assign_msi(port);
293	if (hwirq < 0)
294		return hwirq;
295
296	irq = irq_create_mapping(port->irq_domain, hwirq);
297	if (!irq)
298		return -EINVAL;
299
300	irq_set_msi_desc(irq, desc);
301
302	msg_addr = virt_to_phys((void *)port->msi_pages);
303
304	msg.address_hi = 0;
305	msg.address_lo = msg_addr;
306	msg.data = irq;
307
308	pci_write_msi_msg(irq, &msg);
309
310	return 0;
311}
312
313/* MSI Chip Descriptor */
314static struct msi_controller xilinx_pcie_msi_chip = {
315	.setup_irq = xilinx_pcie_msi_setup_irq,
316	.teardown_irq = xilinx_msi_teardown_irq,
317};
318
319/* HW Interrupt Chip Descriptor */
320static struct irq_chip xilinx_msi_irq_chip = {
321	.name = "Xilinx PCIe MSI",
322	.irq_enable = pci_msi_unmask_irq,
323	.irq_disable = pci_msi_mask_irq,
324	.irq_mask = pci_msi_mask_irq,
325	.irq_unmask = pci_msi_unmask_irq,
326};
327
328/**
329 * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
330 * @domain: IRQ domain
331 * @irq: Virtual IRQ number
332 * @hwirq: HW interrupt number
333 *
334 * Return: Always returns 0.
335 */
336static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
337			       irq_hw_number_t hwirq)
338{
339	irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
340	irq_set_chip_data(irq, domain->host_data);
341	set_irq_flags(irq, IRQF_VALID);
342
343	return 0;
344}
345
346/* IRQ Domain operations */
347static const struct irq_domain_ops msi_domain_ops = {
348	.map = xilinx_pcie_msi_map,
349};
350
351/**
352 * xilinx_pcie_enable_msi - Enable MSI support
353 * @port: PCIe port information
354 */
355static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
356{
357	phys_addr_t msg_addr;
358
359	port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
360	msg_addr = virt_to_phys((void *)port->msi_pages);
361	pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
362	pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
363}
364
365/* INTx Functions */
366
367/**
368 * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
369 * @domain: IRQ domain
370 * @irq: Virtual IRQ number
371 * @hwirq: HW interrupt number
372 *
373 * Return: Always returns 0.
374 */
375static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
376				irq_hw_number_t hwirq)
377{
378	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
379	irq_set_chip_data(irq, domain->host_data);
380	set_irq_flags(irq, IRQF_VALID);
381
382	return 0;
383}
384
385/* INTx IRQ Domain operations */
386static const struct irq_domain_ops intx_domain_ops = {
387	.map = xilinx_pcie_intx_map,
388};
389
390/* PCIe HW Functions */
391
392/**
393 * xilinx_pcie_intr_handler - Interrupt Service Handler
394 * @irq: IRQ number
395 * @data: PCIe port information
396 *
397 * Return: IRQ_HANDLED on success and IRQ_NONE on failure
398 */
399static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
400{
401	struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
402	u32 val, mask, status, msi_data;
403
404	/* Read interrupt decode and mask registers */
405	val = pcie_read(port, XILINX_PCIE_REG_IDR);
406	mask = pcie_read(port, XILINX_PCIE_REG_IMR);
407
408	status = val & mask;
409	if (!status)
410		return IRQ_NONE;
411
412	if (status & XILINX_PCIE_INTR_LINK_DOWN)
413		dev_warn(port->dev, "Link Down\n");
414
415	if (status & XILINX_PCIE_INTR_ECRC_ERR)
416		dev_warn(port->dev, "ECRC failed\n");
417
418	if (status & XILINX_PCIE_INTR_STR_ERR)
419		dev_warn(port->dev, "Streaming error\n");
420
421	if (status & XILINX_PCIE_INTR_HOT_RESET)
422		dev_info(port->dev, "Hot reset\n");
423
424	if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
425		dev_warn(port->dev, "ECAM access timeout\n");
426
427	if (status & XILINX_PCIE_INTR_CORRECTABLE) {
428		dev_warn(port->dev, "Correctable error message\n");
429		xilinx_pcie_clear_err_interrupts(port);
430	}
431
432	if (status & XILINX_PCIE_INTR_NONFATAL) {
433		dev_warn(port->dev, "Non fatal error message\n");
434		xilinx_pcie_clear_err_interrupts(port);
435	}
436
437	if (status & XILINX_PCIE_INTR_FATAL) {
438		dev_warn(port->dev, "Fatal error message\n");
439		xilinx_pcie_clear_err_interrupts(port);
440	}
441
442	if (status & XILINX_PCIE_INTR_INTX) {
443		/* INTx interrupt received */
444		val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
445
446		/* Check whether interrupt valid */
447		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
448			dev_warn(port->dev, "RP Intr FIFO1 read error\n");
449			return IRQ_HANDLED;
450		}
451
452		/* Clear interrupt FIFO register 1 */
453		pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
454			   XILINX_PCIE_REG_RPIFR1);
455
456		/* Handle INTx Interrupt */
457		val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
458			XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
459		generic_handle_irq(irq_find_mapping(port->irq_domain, val));
460	}
461
462	if (status & XILINX_PCIE_INTR_MSI) {
463		/* MSI Interrupt */
464		val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
465
466		if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
467			dev_warn(port->dev, "RP Intr FIFO1 read error\n");
468			return IRQ_HANDLED;
469		}
470
471		if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
472			msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
473				   XILINX_PCIE_RPIFR2_MSG_DATA;
474
475			/* Clear interrupt FIFO register 1 */
476			pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
477				   XILINX_PCIE_REG_RPIFR1);
478
479			if (IS_ENABLED(CONFIG_PCI_MSI)) {
480				/* Handle MSI Interrupt */
481				generic_handle_irq(msi_data);
482			}
483		}
484	}
485
486	if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
487		dev_warn(port->dev, "Slave unsupported request\n");
488
489	if (status & XILINX_PCIE_INTR_SLV_UNEXP)
490		dev_warn(port->dev, "Slave unexpected completion\n");
491
492	if (status & XILINX_PCIE_INTR_SLV_COMPL)
493		dev_warn(port->dev, "Slave completion timeout\n");
494
495	if (status & XILINX_PCIE_INTR_SLV_ERRP)
496		dev_warn(port->dev, "Slave Error Poison\n");
497
498	if (status & XILINX_PCIE_INTR_SLV_CMPABT)
499		dev_warn(port->dev, "Slave Completer Abort\n");
500
501	if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
502		dev_warn(port->dev, "Slave Illegal Burst\n");
503
504	if (status & XILINX_PCIE_INTR_MST_DECERR)
505		dev_warn(port->dev, "Master decode error\n");
506
507	if (status & XILINX_PCIE_INTR_MST_SLVERR)
508		dev_warn(port->dev, "Master slave error\n");
509
510	if (status & XILINX_PCIE_INTR_MST_ERRP)
511		dev_warn(port->dev, "Master error poison\n");
512
513	/* Clear the Interrupt Decode register */
514	pcie_write(port, status, XILINX_PCIE_REG_IDR);
515
516	return IRQ_HANDLED;
517}
518
519/**
520 * xilinx_pcie_free_irq_domain - Free IRQ domain
521 * @port: PCIe port information
522 */
523static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
524{
525	int i;
526	u32 irq, num_irqs;
527
528	/* Free IRQ Domain */
529	if (IS_ENABLED(CONFIG_PCI_MSI)) {
530
531		free_pages(port->msi_pages, 0);
532
533		num_irqs = XILINX_NUM_MSI_IRQS;
534	} else {
535		/* INTx */
536		num_irqs = 4;
537	}
538
539	for (i = 0; i < num_irqs; i++) {
540		irq = irq_find_mapping(port->irq_domain, i);
541		if (irq > 0)
542			irq_dispose_mapping(irq);
543	}
544
545	irq_domain_remove(port->irq_domain);
546}
547
548/**
549 * xilinx_pcie_init_irq_domain - Initialize IRQ domain
550 * @port: PCIe port information
551 *
552 * Return: '0' on success and error value on failure
553 */
554static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
555{
556	struct device *dev = port->dev;
557	struct device_node *node = dev->of_node;
558	struct device_node *pcie_intc_node;
559
560	/* Setup INTx */
561	pcie_intc_node = of_get_next_child(node, NULL);
562	if (!pcie_intc_node) {
563		dev_err(dev, "No PCIe Intc node found\n");
564		return PTR_ERR(pcie_intc_node);
565	}
566
567	port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
568						 &intx_domain_ops,
569						 port);
570	if (!port->irq_domain) {
571		dev_err(dev, "Failed to get a INTx IRQ domain\n");
572		return PTR_ERR(port->irq_domain);
573	}
574
575	/* Setup MSI */
576	if (IS_ENABLED(CONFIG_PCI_MSI)) {
577		port->irq_domain = irq_domain_add_linear(node,
578							 XILINX_NUM_MSI_IRQS,
579							 &msi_domain_ops,
580							 &xilinx_pcie_msi_chip);
581		if (!port->irq_domain) {
582			dev_err(dev, "Failed to get a MSI IRQ domain\n");
583			return PTR_ERR(port->irq_domain);
584		}
585
586		xilinx_pcie_enable_msi(port);
587	}
588
589	return 0;
590}
591
592/**
593 * xilinx_pcie_init_port - Initialize hardware
594 * @port: PCIe port information
595 */
596static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
597{
598	if (xilinx_pcie_link_is_up(port))
599		dev_info(port->dev, "PCIe Link is UP\n");
600	else
601		dev_info(port->dev, "PCIe Link is DOWN\n");
602
603	/* Disable all interrupts */
604	pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
605		   XILINX_PCIE_REG_IMR);
606
607	/* Clear pending interrupts */
608	pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
609			 XILINX_PCIE_IMR_ALL_MASK,
610		   XILINX_PCIE_REG_IDR);
611
612	/* Enable all interrupts */
613	pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
614
615	/* Enable the Bridge enable bit */
616	pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
617			 XILINX_PCIE_REG_RPSC_BEN,
618		   XILINX_PCIE_REG_RPSC);
619}
620
621/**
622 * xilinx_pcie_setup - Setup memory resources
623 * @nr: Bus number
624 * @sys: Per controller structure
625 *
626 * Return: '1' on success and error value on failure
627 */
628static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
629{
630	struct xilinx_pcie_port *port = sys_to_pcie(sys);
631
632	list_splice_init(&port->resources, &sys->resources);
633
634	return 1;
635}
636
637/**
638 * xilinx_pcie_scan_bus - Scan PCIe bus for devices
639 * @nr: Bus number
640 * @sys: Per controller structure
641 *
642 * Return: Valid Bus pointer on success and NULL on failure
643 */
644static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
645{
646	struct xilinx_pcie_port *port = sys_to_pcie(sys);
647	struct pci_bus *bus;
648
649	port->root_busno = sys->busnr;
650	bus = pci_scan_root_bus(port->dev, sys->busnr, &xilinx_pcie_ops,
651				sys, &sys->resources);
652
653	return bus;
654}
655
656/**
657 * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
658 * @port: PCIe port information
659 *
660 * Return: '0' on success and error value on failure
661 */
662static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
663{
664	struct device *dev = port->dev;
665	struct device_node *node = dev->of_node;
666	struct resource *mem;
667	resource_size_t offset;
668	struct of_pci_range_parser parser;
669	struct of_pci_range range;
670	struct resource_entry *win;
671	int err = 0, mem_resno = 0;
672
673	/* Get the ranges */
674	if (of_pci_range_parser_init(&parser, node)) {
675		dev_err(dev, "missing \"ranges\" property\n");
676		return -EINVAL;
677	}
678
679	/* Parse the ranges and add the resources found to the list */
680	for_each_of_pci_range(&parser, &range) {
681
682		if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
683			dev_err(dev, "Maximum memory resources exceeded\n");
684			return -EINVAL;
685		}
686
687		mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
688		if (!mem) {
689			err = -ENOMEM;
690			goto free_resources;
691		}
692
693		of_pci_range_to_resource(&range, node, mem);
694
695		switch (mem->flags & IORESOURCE_TYPE_BITS) {
696		case IORESOURCE_MEM:
697			offset = range.cpu_addr - range.pci_addr;
698			mem_resno++;
699			break;
700		default:
701			err = -EINVAL;
702			break;
703		}
704
705		if (err < 0) {
706			dev_warn(dev, "Invalid resource found %pR\n", mem);
707			continue;
708		}
709
710		err = request_resource(&iomem_resource, mem);
711		if (err)
712			goto free_resources;
713
714		pci_add_resource_offset(&port->resources, mem, offset);
715	}
716
717	/* Get the bus range */
718	if (of_pci_parse_bus_range(node, &port->bus_range)) {
719		u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
720		u8 last;
721
722		last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
723			XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
724
725		port->bus_range = (struct resource) {
726			.name	= node->name,
727			.start	= 0,
728			.end	= last,
729			.flags	= IORESOURCE_BUS,
730		};
731	}
732
733	/* Register bus resource */
734	pci_add_resource(&port->resources, &port->bus_range);
735
736	return 0;
737
738free_resources:
739	release_child_resources(&iomem_resource);
740	resource_list_for_each_entry(win, &port->resources)
741		devm_kfree(dev, win->res);
742	pci_free_resource_list(&port->resources);
743
744	return err;
745}
746
747/**
748 * xilinx_pcie_parse_dt - Parse Device tree
749 * @port: PCIe port information
750 *
751 * Return: '0' on success and error value on failure
752 */
753static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
754{
755	struct device *dev = port->dev;
756	struct device_node *node = dev->of_node;
757	struct resource regs;
758	const char *type;
759	int err;
760
761	type = of_get_property(node, "device_type", NULL);
762	if (!type || strcmp(type, "pci")) {
763		dev_err(dev, "invalid \"device_type\" %s\n", type);
764		return -EINVAL;
765	}
766
767	err = of_address_to_resource(node, 0, &regs);
768	if (err) {
769		dev_err(dev, "missing \"reg\" property\n");
770		return err;
771	}
772
773	port->reg_base = devm_ioremap_resource(dev, &regs);
774	if (IS_ERR(port->reg_base))
775		return PTR_ERR(port->reg_base);
776
777	port->irq = irq_of_parse_and_map(node, 0);
778	err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
779			       IRQF_SHARED | IRQF_NO_THREAD,
780			       "xilinx-pcie", port);
781	if (err) {
782		dev_err(dev, "unable to request irq %d\n", port->irq);
783		return err;
784	}
785
786	return 0;
787}
788
789/**
790 * xilinx_pcie_probe - Probe function
791 * @pdev: Platform device pointer
792 *
793 * Return: '0' on success and error value on failure
794 */
795static int xilinx_pcie_probe(struct platform_device *pdev)
796{
797	struct xilinx_pcie_port *port;
798	struct hw_pci hw;
799	struct device *dev = &pdev->dev;
800	int err;
801
802	if (!dev->of_node)
803		return -ENODEV;
804
805	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
806	if (!port)
807		return -ENOMEM;
808
809	port->dev = dev;
810
811	err = xilinx_pcie_parse_dt(port);
812	if (err) {
813		dev_err(dev, "Parsing DT failed\n");
814		return err;
815	}
816
817	xilinx_pcie_init_port(port);
818
819	err = xilinx_pcie_init_irq_domain(port);
820	if (err) {
821		dev_err(dev, "Failed creating IRQ Domain\n");
822		return err;
823	}
824
825	/*
826	 * Parse PCI ranges, configuration bus range and
827	 * request their resources
828	 */
829	INIT_LIST_HEAD(&port->resources);
830	err = xilinx_pcie_parse_and_add_res(port);
831	if (err) {
832		dev_err(dev, "Failed adding resources\n");
833		return err;
834	}
835
836	platform_set_drvdata(pdev, port);
837
838	/* Register the device */
839	memset(&hw, 0, sizeof(hw));
840	hw = (struct hw_pci) {
841		.nr_controllers	= 1,
842		.private_data	= (void **)&port,
843		.setup		= xilinx_pcie_setup,
844		.map_irq	= of_irq_parse_and_map_pci,
845		.scan		= xilinx_pcie_scan_bus,
846		.ops		= &xilinx_pcie_ops,
847	};
848
849#ifdef CONFIG_PCI_MSI
850	xilinx_pcie_msi_chip.dev = port->dev;
851	hw.msi_ctrl = &xilinx_pcie_msi_chip;
852#endif
853	pci_common_init_dev(dev, &hw);
854
855	return 0;
856}
857
858/**
859 * xilinx_pcie_remove - Remove function
860 * @pdev: Platform device pointer
861 *
862 * Return: '0' always
863 */
864static int xilinx_pcie_remove(struct platform_device *pdev)
865{
866	struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
867
868	xilinx_pcie_free_irq_domain(port);
869
870	return 0;
871}
872
873static struct of_device_id xilinx_pcie_of_match[] = {
874	{ .compatible = "xlnx,axi-pcie-host-1.00.a", },
875	{}
876};
877
878static struct platform_driver xilinx_pcie_driver = {
879	.driver = {
880		.name = "xilinx-pcie",
881		.of_match_table = xilinx_pcie_of_match,
882		.suppress_bind_attrs = true,
883	},
884	.probe = xilinx_pcie_probe,
885	.remove = xilinx_pcie_remove,
886};
887module_platform_driver(xilinx_pcie_driver);
888
889MODULE_AUTHOR("Xilinx Inc");
890MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
891MODULE_LICENSE("GPL v2");
892