1/* 2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Common Clock Framework support for S3C2443 and following SoCs. 9 */ 10 11#include <linux/clk.h> 12#include <linux/clkdev.h> 13#include <linux/clk-provider.h> 14#include <linux/of.h> 15#include <linux/of_address.h> 16#include <linux/syscore_ops.h> 17#include <linux/reboot.h> 18 19#include <dt-bindings/clock/s3c2443.h> 20 21#include "clk.h" 22#include "clk-pll.h" 23 24/* S3C2416 clock controller register offsets */ 25#define LOCKCON0 0x00 26#define LOCKCON1 0x04 27#define MPLLCON 0x10 28#define EPLLCON 0x18 29#define EPLLCON_K 0x1C 30#define CLKSRC 0x20 31#define CLKDIV0 0x24 32#define CLKDIV1 0x28 33#define CLKDIV2 0x2C 34#define HCLKCON 0x30 35#define PCLKCON 0x34 36#define SCLKCON 0x38 37#define SWRST 0x44 38 39/* the soc types */ 40enum supported_socs { 41 S3C2416, 42 S3C2443, 43 S3C2450, 44}; 45 46/* list of PLLs to be registered */ 47enum s3c2443_plls { 48 mpll, epll, 49}; 50 51static void __iomem *reg_base; 52 53#ifdef CONFIG_PM_SLEEP 54static struct samsung_clk_reg_dump *s3c2443_save; 55 56/* 57 * list of controller registers to be saved and restored during a 58 * suspend/resume cycle. 59 */ 60static unsigned long s3c2443_clk_regs[] __initdata = { 61 LOCKCON0, 62 LOCKCON1, 63 MPLLCON, 64 EPLLCON, 65 EPLLCON_K, 66 CLKSRC, 67 CLKDIV0, 68 CLKDIV1, 69 CLKDIV2, 70 PCLKCON, 71 HCLKCON, 72 SCLKCON, 73}; 74 75static int s3c2443_clk_suspend(void) 76{ 77 samsung_clk_save(reg_base, s3c2443_save, 78 ARRAY_SIZE(s3c2443_clk_regs)); 79 80 return 0; 81} 82 83static void s3c2443_clk_resume(void) 84{ 85 samsung_clk_restore(reg_base, s3c2443_save, 86 ARRAY_SIZE(s3c2443_clk_regs)); 87} 88 89static struct syscore_ops s3c2443_clk_syscore_ops = { 90 .suspend = s3c2443_clk_suspend, 91 .resume = s3c2443_clk_resume, 92}; 93 94static void s3c2443_clk_sleep_init(void) 95{ 96 s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs, 97 ARRAY_SIZE(s3c2443_clk_regs)); 98 if (!s3c2443_save) { 99 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 100 __func__); 101 return; 102 } 103 104 register_syscore_ops(&s3c2443_clk_syscore_ops); 105 return; 106} 107#else 108static void s3c2443_clk_sleep_init(void) {} 109#endif 110 111PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" }; 112PNAME(esysclk_p) = { "epllref", "epll" }; 113PNAME(mpllref_p) = { "xti", "mdivclk" }; 114PNAME(msysclk_p) = { "mpllref", "mpll" }; 115PNAME(armclk_p) = { "armdiv" , "hclk" }; 116PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" }; 117 118struct samsung_mux_clock s3c2443_common_muxes[] __initdata = { 119 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2), 120 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1), 121 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1), 122 MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"), 123 MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"), 124 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2), 125}; 126 127static struct clk_div_table hclk_d[] = { 128 { .val = 0, .div = 1 }, 129 { .val = 1, .div = 2 }, 130 { .val = 3, .div = 4 }, 131 { /* sentinel */ }, 132}; 133 134static struct clk_div_table mdivclk_d[] = { 135 { .val = 0, .div = 1 }, 136 { .val = 1, .div = 3 }, 137 { .val = 2, .div = 5 }, 138 { .val = 3, .div = 7 }, 139 { .val = 4, .div = 9 }, 140 { .val = 5, .div = 11 }, 141 { .val = 6, .div = 13 }, 142 { .val = 7, .div = 15 }, 143 { /* sentinel */ }, 144}; 145 146struct samsung_div_clock s3c2443_common_dividers[] __initdata = { 147 DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d), 148 DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2), 149 DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d), 150 DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1), 151 DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2), 152 DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8), 153 DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4), 154 DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4), 155 DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2), 156 DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2), 157}; 158 159struct samsung_gate_clock s3c2443_common_gates[] __initdata = { 160 GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0), 161 GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0), 162 GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0), 163 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0), 164 GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0), 165 GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0), 166 GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0), 167 GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0), 168 GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0), 169 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0), 170 GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0), 171 GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0), 172 GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0), 173 GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0), 174 GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0), 175 GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0), 176 GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0), 177 GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0), 178 GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0), 179 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0), 180 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0), 181 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0), 182 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0), 183 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0), 184 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0), 185 GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0), 186 GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0), 187 GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0), 188 GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0), 189 GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0), 190 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0), 191}; 192 193struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { 194 ALIAS(HCLK, NULL, "hclk"), 195 ALIAS(HCLK_SSMC, NULL, "nand"), 196 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), 197 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"), 198 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"), 199 ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"), 200 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"), 201 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"), 202 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"), 203 ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"), 204 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"), 205 ALIAS(PCLK_PWM, NULL, "timers"), 206 ALIAS(PCLK_RTC, NULL, "rtc"), 207 ALIAS(PCLK_WDT, NULL, "watchdog"), 208 ALIAS(PCLK_ADC, NULL, "adc"), 209 ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"), 210 ALIAS(HCLK_USBD, NULL, "usb-device"), 211 ALIAS(HCLK_USBH, NULL, "usb-host"), 212 ALIAS(SCLK_USBH, NULL, "usb-bus-host"), 213 ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"), 214 ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"), 215 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"), 216 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), 217 ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"), 218 ALIAS(SCLK_I2S0, NULL, "i2s-if"), 219 ALIAS(HCLK_LCD, NULL, "lcd"), 220 ALIAS(SCLK_FIMD, NULL, "sclk_fimd"), 221}; 222 223/* S3C2416 specific clocks */ 224 225static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { 226 [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref", 227 LOCKCON0, MPLLCON, NULL), 228 [epll] = PLL(pll_6553, 0, "epll", "epllref", 229 LOCKCON1, EPLLCON, NULL), 230}; 231 232PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" }; 233PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" }; 234PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" }; 235 236static struct clk_div_table armdiv_s3c2416_d[] = { 237 { .val = 0, .div = 1 }, 238 { .val = 1, .div = 2 }, 239 { .val = 2, .div = 3 }, 240 { .val = 3, .div = 4 }, 241 { .val = 5, .div = 6 }, 242 { .val = 7, .div = 8 }, 243 { /* sentinel */ }, 244}; 245 246struct samsung_div_clock s3c2416_dividers[] __initdata = { 247 DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d), 248 DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4), 249 DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2), 250}; 251 252struct samsung_mux_clock s3c2416_muxes[] __initdata = { 253 MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1), 254 MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1), 255 MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1), 256}; 257 258struct samsung_gate_clock s3c2416_gates[] __initdata = { 259 GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0), 260 GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0), 261 GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0), 262 GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0), 263 GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0), 264 GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0), 265 GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0), 266}; 267 268struct samsung_clock_alias s3c2416_aliases[] __initdata = { 269 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), 270 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), 271 ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"), 272 ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"), 273 ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"), 274 ALIAS(ARMDIV, NULL, "armdiv"), 275}; 276 277/* S3C2443 specific clocks */ 278 279static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = { 280 [mpll] = PLL(pll_3000, 0, "mpll", "mpllref", 281 LOCKCON0, MPLLCON, NULL), 282 [epll] = PLL(pll_2126, 0, "epll", "epllref", 283 LOCKCON1, EPLLCON, NULL), 284}; 285 286static struct clk_div_table armdiv_s3c2443_d[] = { 287 { .val = 0, .div = 1 }, 288 { .val = 8, .div = 2 }, 289 { .val = 2, .div = 3 }, 290 { .val = 9, .div = 4 }, 291 { .val = 10, .div = 6 }, 292 { .val = 11, .div = 8 }, 293 { .val = 13, .div = 12 }, 294 { .val = 15, .div = 16 }, 295 { /* sentinel */ }, 296}; 297 298struct samsung_div_clock s3c2443_dividers[] __initdata = { 299 DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d), 300 DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4), 301}; 302 303struct samsung_gate_clock s3c2443_gates[] __initdata = { 304 GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0), 305 GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0), 306 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0), 307 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0), 308 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0), 309 GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0), 310}; 311 312struct samsung_clock_alias s3c2443_aliases[] __initdata = { 313 ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"), 314 ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"), 315 ALIAS(SCLK_CAM, NULL, "camif-upll"), 316 ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"), 317 ALIAS(PCLK_SDI, NULL, "sdi"), 318 ALIAS(HCLK_CFC, NULL, "cfc"), 319 ALIAS(ARMDIV, NULL, "armdiv"), 320}; 321 322/* S3C2450 specific clocks */ 323 324PNAME(s3c2450_cam_p) = { "div_cam", "hclk" }; 325PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" }; 326PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" }; 327 328struct samsung_div_clock s3c2450_dividers[] __initdata = { 329 DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4), 330 DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2), 331 DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4), 332 DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4), 333}; 334 335struct samsung_mux_clock s3c2450_muxes[] __initdata = { 336 MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1), 337 MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1), 338 MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2), 339}; 340 341struct samsung_gate_clock s3c2450_gates[] __initdata = { 342 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0), 343 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0), 344 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0), 345 GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0), 346 GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0), 347 GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0), 348 GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0), 349 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0), 350}; 351 352struct samsung_clock_alias s3c2450_aliases[] __initdata = { 353 ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"), 354 ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"), 355 ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"), 356 ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"), 357}; 358 359static int s3c2443_restart(struct notifier_block *this, 360 unsigned long mode, void *cmd) 361{ 362 __raw_writel(0x533c2443, reg_base + SWRST); 363 return NOTIFY_DONE; 364} 365 366static struct notifier_block s3c2443_restart_handler = { 367 .notifier_call = s3c2443_restart, 368 .priority = 129, 369}; 370 371/* 372 * fixed rate clocks generated outside the soc 373 * Only necessary until the devicetree-move is complete 374 */ 375struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = { 376 FRATE(0, "xti", NULL, CLK_IS_ROOT, 0), 377 FRATE(0, "ext", NULL, CLK_IS_ROOT, 0), 378 FRATE(0, "ext_i2s", NULL, CLK_IS_ROOT, 0), 379 FRATE(0, "ext_uart", NULL, CLK_IS_ROOT, 0), 380}; 381 382static void __init s3c2443_common_clk_register_fixed_ext( 383 struct samsung_clk_provider *ctx, unsigned long xti_f) 384{ 385 s3c2443_common_frate_clks[0].fixed_rate = xti_f; 386 samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks, 387 ARRAY_SIZE(s3c2443_common_frate_clks)); 388} 389 390void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, 391 int current_soc, 392 void __iomem *base) 393{ 394 struct samsung_clk_provider *ctx; 395 int ret; 396 reg_base = base; 397 398 if (np) { 399 reg_base = of_iomap(np, 0); 400 if (!reg_base) 401 panic("%s: failed to map registers\n", __func__); 402 } 403 404 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 405 if (!ctx) 406 panic("%s: unable to allocate context.\n", __func__); 407 408 /* Register external clocks only in non-dt cases */ 409 if (!np) 410 s3c2443_common_clk_register_fixed_ext(ctx, xti_f); 411 412 /* Register PLLs. */ 413 if (current_soc == S3C2416 || current_soc == S3C2450) 414 samsung_clk_register_pll(ctx, s3c2416_pll_clks, 415 ARRAY_SIZE(s3c2416_pll_clks), reg_base); 416 else 417 samsung_clk_register_pll(ctx, s3c2443_pll_clks, 418 ARRAY_SIZE(s3c2443_pll_clks), reg_base); 419 420 /* Register common internal clocks. */ 421 samsung_clk_register_mux(ctx, s3c2443_common_muxes, 422 ARRAY_SIZE(s3c2443_common_muxes)); 423 samsung_clk_register_div(ctx, s3c2443_common_dividers, 424 ARRAY_SIZE(s3c2443_common_dividers)); 425 samsung_clk_register_gate(ctx, s3c2443_common_gates, 426 ARRAY_SIZE(s3c2443_common_gates)); 427 samsung_clk_register_alias(ctx, s3c2443_common_aliases, 428 ARRAY_SIZE(s3c2443_common_aliases)); 429 430 /* Register SoC-specific clocks. */ 431 switch (current_soc) { 432 case S3C2450: 433 samsung_clk_register_div(ctx, s3c2450_dividers, 434 ARRAY_SIZE(s3c2450_dividers)); 435 samsung_clk_register_mux(ctx, s3c2450_muxes, 436 ARRAY_SIZE(s3c2450_muxes)); 437 samsung_clk_register_gate(ctx, s3c2450_gates, 438 ARRAY_SIZE(s3c2450_gates)); 439 samsung_clk_register_alias(ctx, s3c2450_aliases, 440 ARRAY_SIZE(s3c2450_aliases)); 441 /* fall through, as s3c2450 extends the s3c2416 clocks */ 442 case S3C2416: 443 samsung_clk_register_div(ctx, s3c2416_dividers, 444 ARRAY_SIZE(s3c2416_dividers)); 445 samsung_clk_register_mux(ctx, s3c2416_muxes, 446 ARRAY_SIZE(s3c2416_muxes)); 447 samsung_clk_register_gate(ctx, s3c2416_gates, 448 ARRAY_SIZE(s3c2416_gates)); 449 samsung_clk_register_alias(ctx, s3c2416_aliases, 450 ARRAY_SIZE(s3c2416_aliases)); 451 break; 452 case S3C2443: 453 samsung_clk_register_div(ctx, s3c2443_dividers, 454 ARRAY_SIZE(s3c2443_dividers)); 455 samsung_clk_register_gate(ctx, s3c2443_gates, 456 ARRAY_SIZE(s3c2443_gates)); 457 samsung_clk_register_alias(ctx, s3c2443_aliases, 458 ARRAY_SIZE(s3c2443_aliases)); 459 break; 460 } 461 462 s3c2443_clk_sleep_init(); 463 464 samsung_clk_of_add_provider(np, ctx); 465 466 ret = register_restart_handler(&s3c2443_restart_handler); 467 if (ret) 468 pr_warn("cannot register restart handler, %d\n", ret); 469} 470 471static void __init s3c2416_clk_init(struct device_node *np) 472{ 473 s3c2443_common_clk_init(np, 0, S3C2416, 0); 474} 475CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init); 476 477static void __init s3c2443_clk_init(struct device_node *np) 478{ 479 s3c2443_common_clk_init(np, 0, S3C2443, 0); 480} 481CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init); 482 483static void __init s3c2450_clk_init(struct device_node *np) 484{ 485 s3c2443_common_clk_init(np, 0, S3C2450, 0); 486} 487CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init); 488