1 2/* 3 * Texas Instruments AM35x "glue layer" 4 * 5 * Copyright (c) 2010, by Texas Instruments 6 * 7 * Based on the DA8xx "glue layer" code. 8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> 9 * 10 * This file is part of the Inventra Controller Driver for Linux. 11 * 12 * The Inventra Controller Driver for Linux is free software; you 13 * can redistribute it and/or modify it under the terms of the GNU 14 * General Public License version 2 as published by the Free Software 15 * Foundation. 16 * 17 * The Inventra Controller Driver for Linux is distributed in 18 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 19 * without even the implied warranty of MERCHANTABILITY or 20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 21 * License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with The Inventra Controller Driver for Linux ; if not, 25 * write to the Free Software Foundation, Inc., 59 Temple Place, 26 * Suite 330, Boston, MA 02111-1307 USA 27 * 28 */ 29 30#include <linux/module.h> 31#include <linux/clk.h> 32#include <linux/err.h> 33#include <linux/io.h> 34#include <linux/platform_device.h> 35#include <linux/dma-mapping.h> 36#include <linux/usb/usb_phy_generic.h> 37#include <linux/platform_data/usb-omap.h> 38 39#include "musb_core.h" 40 41/* 42 * AM35x specific definitions 43 */ 44/* USB 2.0 OTG module registers */ 45#define USB_REVISION_REG 0x00 46#define USB_CTRL_REG 0x04 47#define USB_STAT_REG 0x08 48#define USB_EMULATION_REG 0x0c 49/* 0x10 Reserved */ 50#define USB_AUTOREQ_REG 0x14 51#define USB_SRP_FIX_TIME_REG 0x18 52#define USB_TEARDOWN_REG 0x1c 53#define EP_INTR_SRC_REG 0x20 54#define EP_INTR_SRC_SET_REG 0x24 55#define EP_INTR_SRC_CLEAR_REG 0x28 56#define EP_INTR_MASK_REG 0x2c 57#define EP_INTR_MASK_SET_REG 0x30 58#define EP_INTR_MASK_CLEAR_REG 0x34 59#define EP_INTR_SRC_MASKED_REG 0x38 60#define CORE_INTR_SRC_REG 0x40 61#define CORE_INTR_SRC_SET_REG 0x44 62#define CORE_INTR_SRC_CLEAR_REG 0x48 63#define CORE_INTR_MASK_REG 0x4c 64#define CORE_INTR_MASK_SET_REG 0x50 65#define CORE_INTR_MASK_CLEAR_REG 0x54 66#define CORE_INTR_SRC_MASKED_REG 0x58 67/* 0x5c Reserved */ 68#define USB_END_OF_INTR_REG 0x60 69 70/* Control register bits */ 71#define AM35X_SOFT_RESET_MASK 1 72 73/* USB interrupt register bits */ 74#define AM35X_INTR_USB_SHIFT 16 75#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) 76#define AM35X_INTR_DRVVBUS 0x100 77#define AM35X_INTR_RX_SHIFT 16 78#define AM35X_INTR_TX_SHIFT 0 79#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ 80#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ 81#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) 82#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) 83 84#define USB_MENTOR_CORE_OFFSET 0x400 85 86struct am35x_glue { 87 struct device *dev; 88 struct platform_device *musb; 89 struct platform_device *phy; 90 struct clk *phy_clk; 91 struct clk *clk; 92}; 93 94/* 95 * am35x_musb_enable - enable interrupts 96 */ 97static void am35x_musb_enable(struct musb *musb) 98{ 99 void __iomem *reg_base = musb->ctrl_base; 100 u32 epmask; 101 102 /* Workaround: setup IRQs through both register sets. */ 103 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | 104 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); 105 106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); 107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); 108 109 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, 111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); 112} 113 114/* 115 * am35x_musb_disable - disable HDRC and flush interrupts 116 */ 117static void am35x_musb_disable(struct musb *musb) 118{ 119 void __iomem *reg_base = musb->ctrl_base; 120 121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); 122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, 123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); 124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0); 125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 126} 127 128#define portstate(stmt) stmt 129 130static void am35x_musb_set_vbus(struct musb *musb, int is_on) 131{ 132 WARN_ON(is_on && is_peripheral_active(musb)); 133} 134 135#define POLL_SECONDS 2 136 137static struct timer_list otg_workaround; 138 139static void otg_timer(unsigned long _musb) 140{ 141 struct musb *musb = (void *)_musb; 142 void __iomem *mregs = musb->mregs; 143 u8 devctl; 144 unsigned long flags; 145 146 /* 147 * We poll because AM35x's won't expose several OTG-critical 148 * status change events (from the transceiver) otherwise. 149 */ 150 devctl = musb_readb(mregs, MUSB_DEVCTL); 151 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 152 usb_otg_state_string(musb->xceiv->otg->state)); 153 154 spin_lock_irqsave(&musb->lock, flags); 155 switch (musb->xceiv->otg->state) { 156 case OTG_STATE_A_WAIT_BCON: 157 devctl &= ~MUSB_DEVCTL_SESSION; 158 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 159 160 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 161 if (devctl & MUSB_DEVCTL_BDEVICE) { 162 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 163 MUSB_DEV_MODE(musb); 164 } else { 165 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 166 MUSB_HST_MODE(musb); 167 } 168 break; 169 case OTG_STATE_A_WAIT_VFALL: 170 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, 172 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); 173 break; 174 case OTG_STATE_B_IDLE: 175 devctl = musb_readb(mregs, MUSB_DEVCTL); 176 if (devctl & MUSB_DEVCTL_BDEVICE) 177 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 178 else 179 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 180 break; 181 default: 182 break; 183 } 184 spin_unlock_irqrestore(&musb->lock, flags); 185} 186 187static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) 188{ 189 static unsigned long last_timer; 190 191 if (timeout == 0) 192 timeout = jiffies + msecs_to_jiffies(3); 193 194 /* Never idle if active, or when VBUS timeout is not set as host */ 195 if (musb->is_active || (musb->a_wait_bcon == 0 && 196 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { 197 dev_dbg(musb->controller, "%s active, deleting timer\n", 198 usb_otg_state_string(musb->xceiv->otg->state)); 199 del_timer(&otg_workaround); 200 last_timer = jiffies; 201 return; 202 } 203 204 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { 205 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); 206 return; 207 } 208 last_timer = timeout; 209 210 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 211 usb_otg_state_string(musb->xceiv->otg->state), 212 jiffies_to_msecs(timeout - jiffies)); 213 mod_timer(&otg_workaround, timeout); 214} 215 216static irqreturn_t am35x_musb_interrupt(int irq, void *hci) 217{ 218 struct musb *musb = hci; 219 void __iomem *reg_base = musb->ctrl_base; 220 struct device *dev = musb->controller; 221 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 222 struct omap_musb_board_data *data = plat->board_data; 223 struct usb_otg *otg = musb->xceiv->otg; 224 unsigned long flags; 225 irqreturn_t ret = IRQ_NONE; 226 u32 epintr, usbintr; 227 228 spin_lock_irqsave(&musb->lock, flags); 229 230 /* Get endpoint interrupts */ 231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); 232 233 if (epintr) { 234 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); 235 236 musb->int_rx = 237 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; 238 musb->int_tx = 239 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; 240 } 241 242 /* Get usb core interrupts */ 243 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); 244 if (!usbintr && !epintr) 245 goto eoi; 246 247 if (usbintr) { 248 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); 249 250 musb->int_usb = 251 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; 252 } 253 /* 254 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 255 * AM35x's missing ID change IRQ. We need an ID change IRQ to 256 * switch appropriately between halves of the OTG state machine. 257 * Managing DEVCTL.SESSION per Mentor docs requires that we know its 258 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. 259 * Also, DRVVBUS pulses for SRP (but not at 5V) ... 260 */ 261 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { 262 int drvvbus = musb_readl(reg_base, USB_STAT_REG); 263 void __iomem *mregs = musb->mregs; 264 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 265 int err; 266 267 err = musb->int_usb & MUSB_INTR_VBUSERROR; 268 if (err) { 269 /* 270 * The Mentor core doesn't debounce VBUS as needed 271 * to cope with device connect current spikes. This 272 * means it's not uncommon for bus-powered devices 273 * to get VBUS errors during enumeration. 274 * 275 * This is a workaround, but newer RTL from Mentor 276 * seems to allow a better one: "re"-starting sessions 277 * without waiting for VBUS to stop registering in 278 * devctl. 279 */ 280 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 281 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 282 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 283 WARNING("VBUS error workaround (delay coming)\n"); 284 } else if (drvvbus) { 285 MUSB_HST_MODE(musb); 286 otg->default_a = 1; 287 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 288 portstate(musb->port1_status |= USB_PORT_STAT_POWER); 289 del_timer(&otg_workaround); 290 } else { 291 musb->is_active = 0; 292 MUSB_DEV_MODE(musb); 293 otg->default_a = 0; 294 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 295 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); 296 } 297 298 /* NOTE: this must complete power-on within 100 ms. */ 299 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 300 drvvbus ? "on" : "off", 301 usb_otg_state_string(musb->xceiv->otg->state), 302 err ? " ERROR" : "", 303 devctl); 304 ret = IRQ_HANDLED; 305 } 306 307 /* Drop spurious RX and TX if device is disconnected */ 308 if (musb->int_usb & MUSB_INTR_DISCONNECT) { 309 musb->int_tx = 0; 310 musb->int_rx = 0; 311 } 312 313 if (musb->int_tx || musb->int_rx || musb->int_usb) 314 ret |= musb_interrupt(musb); 315 316eoi: 317 /* EOI needs to be written for the IRQ to be re-asserted. */ 318 if (ret == IRQ_HANDLED || epintr || usbintr) { 319 /* clear level interrupt */ 320 if (data->clear_irq) 321 data->clear_irq(); 322 /* write EOI */ 323 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 324 } 325 326 /* Poll for ID change */ 327 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) 328 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); 329 330 spin_unlock_irqrestore(&musb->lock, flags); 331 332 return ret; 333} 334 335static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) 336{ 337 struct device *dev = musb->controller; 338 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 339 struct omap_musb_board_data *data = plat->board_data; 340 int retval = 0; 341 342 if (data->set_mode) 343 data->set_mode(musb_mode); 344 else 345 retval = -EIO; 346 347 return retval; 348} 349 350static int am35x_musb_init(struct musb *musb) 351{ 352 struct device *dev = musb->controller; 353 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 354 struct omap_musb_board_data *data = plat->board_data; 355 void __iomem *reg_base = musb->ctrl_base; 356 u32 rev; 357 358 musb->mregs += USB_MENTOR_CORE_OFFSET; 359 360 /* Returns zero if e.g. not clocked */ 361 rev = musb_readl(reg_base, USB_REVISION_REG); 362 if (!rev) 363 return -ENODEV; 364 365 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 366 if (IS_ERR_OR_NULL(musb->xceiv)) 367 return -EPROBE_DEFER; 368 369 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); 370 371 /* Reset the musb */ 372 if (data->reset) 373 data->reset(); 374 375 /* Reset the controller */ 376 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); 377 378 /* Start the on-chip PHY and its PLL. */ 379 if (data->set_phy_power) 380 data->set_phy_power(1); 381 382 msleep(5); 383 384 musb->isr = am35x_musb_interrupt; 385 386 /* clear level interrupt */ 387 if (data->clear_irq) 388 data->clear_irq(); 389 390 return 0; 391} 392 393static int am35x_musb_exit(struct musb *musb) 394{ 395 struct device *dev = musb->controller; 396 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 397 struct omap_musb_board_data *data = plat->board_data; 398 399 del_timer_sync(&otg_workaround); 400 401 /* Shutdown the on-chip PHY and its PLL. */ 402 if (data->set_phy_power) 403 data->set_phy_power(0); 404 405 usb_put_phy(musb->xceiv); 406 407 return 0; 408} 409 410/* AM35x supports only 32bit read operation */ 411static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) 412{ 413 void __iomem *fifo = hw_ep->fifo; 414 u32 val; 415 int i; 416 417 /* Read for 32bit-aligned destination address */ 418 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { 419 readsl(fifo, dst, len >> 2); 420 dst += len & ~0x03; 421 len &= 0x03; 422 } 423 /* 424 * Now read the remaining 1 to 3 byte or complete length if 425 * unaligned address. 426 */ 427 if (len > 4) { 428 for (i = 0; i < (len >> 2); i++) { 429 *(u32 *) dst = musb_readl(fifo, 0); 430 dst += 4; 431 } 432 len &= 0x03; 433 } 434 if (len > 0) { 435 val = musb_readl(fifo, 0); 436 memcpy(dst, &val, len); 437 } 438} 439 440static const struct musb_platform_ops am35x_ops = { 441 .quirks = MUSB_INDEXED_EP, 442 .init = am35x_musb_init, 443 .exit = am35x_musb_exit, 444 445 .read_fifo = am35x_read_fifo, 446 .enable = am35x_musb_enable, 447 .disable = am35x_musb_disable, 448 449 .set_mode = am35x_musb_set_mode, 450 .try_idle = am35x_musb_try_idle, 451 452 .set_vbus = am35x_musb_set_vbus, 453}; 454 455static const struct platform_device_info am35x_dev_info = { 456 .name = "musb-hdrc", 457 .id = PLATFORM_DEVID_AUTO, 458 .dma_mask = DMA_BIT_MASK(32), 459}; 460 461static int am35x_probe(struct platform_device *pdev) 462{ 463 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 464 struct platform_device *musb; 465 struct am35x_glue *glue; 466 struct platform_device_info pinfo; 467 struct clk *phy_clk; 468 struct clk *clk; 469 470 int ret = -ENOMEM; 471 472 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 473 if (!glue) { 474 dev_err(&pdev->dev, "failed to allocate glue context\n"); 475 goto err0; 476 } 477 478 phy_clk = clk_get(&pdev->dev, "fck"); 479 if (IS_ERR(phy_clk)) { 480 dev_err(&pdev->dev, "failed to get PHY clock\n"); 481 ret = PTR_ERR(phy_clk); 482 goto err3; 483 } 484 485 clk = clk_get(&pdev->dev, "ick"); 486 if (IS_ERR(clk)) { 487 dev_err(&pdev->dev, "failed to get clock\n"); 488 ret = PTR_ERR(clk); 489 goto err4; 490 } 491 492 ret = clk_enable(phy_clk); 493 if (ret) { 494 dev_err(&pdev->dev, "failed to enable PHY clock\n"); 495 goto err5; 496 } 497 498 ret = clk_enable(clk); 499 if (ret) { 500 dev_err(&pdev->dev, "failed to enable clock\n"); 501 goto err6; 502 } 503 504 glue->dev = &pdev->dev; 505 glue->phy_clk = phy_clk; 506 glue->clk = clk; 507 508 pdata->platform_ops = &am35x_ops; 509 510 glue->phy = usb_phy_generic_register(); 511 if (IS_ERR(glue->phy)) 512 goto err7; 513 platform_set_drvdata(pdev, glue); 514 515 pinfo = am35x_dev_info; 516 pinfo.parent = &pdev->dev; 517 pinfo.res = pdev->resource; 518 pinfo.num_res = pdev->num_resources; 519 pinfo.data = pdata; 520 pinfo.size_data = sizeof(*pdata); 521 522 glue->musb = musb = platform_device_register_full(&pinfo); 523 if (IS_ERR(musb)) { 524 ret = PTR_ERR(musb); 525 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 526 goto err8; 527 } 528 529 return 0; 530 531err8: 532 usb_phy_generic_unregister(glue->phy); 533 534err7: 535 clk_disable(clk); 536 537err6: 538 clk_disable(phy_clk); 539 540err5: 541 clk_put(clk); 542 543err4: 544 clk_put(phy_clk); 545 546err3: 547 kfree(glue); 548 549err0: 550 return ret; 551} 552 553static int am35x_remove(struct platform_device *pdev) 554{ 555 struct am35x_glue *glue = platform_get_drvdata(pdev); 556 557 platform_device_unregister(glue->musb); 558 usb_phy_generic_unregister(glue->phy); 559 clk_disable(glue->clk); 560 clk_disable(glue->phy_clk); 561 clk_put(glue->clk); 562 clk_put(glue->phy_clk); 563 kfree(glue); 564 565 return 0; 566} 567 568#ifdef CONFIG_PM 569static int am35x_suspend(struct device *dev) 570{ 571 struct am35x_glue *glue = dev_get_drvdata(dev); 572 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 573 struct omap_musb_board_data *data = plat->board_data; 574 575 /* Shutdown the on-chip PHY and its PLL. */ 576 if (data->set_phy_power) 577 data->set_phy_power(0); 578 579 clk_disable(glue->phy_clk); 580 clk_disable(glue->clk); 581 582 return 0; 583} 584 585static int am35x_resume(struct device *dev) 586{ 587 struct am35x_glue *glue = dev_get_drvdata(dev); 588 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 589 struct omap_musb_board_data *data = plat->board_data; 590 int ret; 591 592 /* Start the on-chip PHY and its PLL. */ 593 if (data->set_phy_power) 594 data->set_phy_power(1); 595 596 ret = clk_enable(glue->phy_clk); 597 if (ret) { 598 dev_err(dev, "failed to enable PHY clock\n"); 599 return ret; 600 } 601 602 ret = clk_enable(glue->clk); 603 if (ret) { 604 dev_err(dev, "failed to enable clock\n"); 605 return ret; 606 } 607 608 return 0; 609} 610#endif 611 612static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume); 613 614static struct platform_driver am35x_driver = { 615 .probe = am35x_probe, 616 .remove = am35x_remove, 617 .driver = { 618 .name = "musb-am35x", 619 .pm = &am35x_pm_ops, 620 }, 621}; 622 623MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); 624MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); 625MODULE_LICENSE("GPL v2"); 626module_platform_driver(am35x_driver); 627