1/*
2 * Broadcom BCM7120 style Level 2 interrupt controller driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
12
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/kconfig.h>
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_irq.h>
21#include <linux/of_address.h>
22#include <linux/of_platform.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/irqdomain.h>
27#include <linux/reboot.h>
28#include <linux/bitops.h>
29#include <linux/irqchip/chained_irq.h>
30
31#include "irqchip.h"
32
33/* Register offset in the L2 interrupt controller */
34#define IRQEN		0x00
35#define IRQSTAT		0x04
36
37#define MAX_WORDS	4
38#define MAX_MAPPINGS	(MAX_WORDS * 2)
39#define IRQS_PER_WORD	32
40
41struct bcm7120_l2_intc_data {
42	unsigned int n_words;
43	void __iomem *map_base[MAX_MAPPINGS];
44	void __iomem *pair_base[MAX_WORDS];
45	int en_offset[MAX_WORDS];
46	int stat_offset[MAX_WORDS];
47	struct irq_domain *domain;
48	bool can_wake;
49	u32 irq_fwd_mask[MAX_WORDS];
50	u32 irq_map_mask[MAX_WORDS];
51	int num_parent_irqs;
52	const __be32 *map_mask_prop;
53};
54
55static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
56{
57	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
58	struct irq_chip *chip = irq_desc_get_chip(desc);
59	unsigned int idx;
60
61	chained_irq_enter(chip, desc);
62
63	for (idx = 0; idx < b->n_words; idx++) {
64		int base = idx * IRQS_PER_WORD;
65		struct irq_chip_generic *gc =
66			irq_get_domain_generic_chip(b->domain, base);
67		unsigned long pending;
68		int hwirq;
69
70		irq_gc_lock(gc);
71		pending = irq_reg_readl(gc, b->stat_offset[idx]) &
72					    gc->mask_cache;
73		irq_gc_unlock(gc);
74
75		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
76			generic_handle_irq(irq_find_mapping(b->domain,
77					   base + hwirq));
78		}
79	}
80
81	chained_irq_exit(chip, desc);
82}
83
84static void bcm7120_l2_intc_suspend(struct irq_data *d)
85{
86	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
87	struct irq_chip_type *ct = irq_data_get_chip_type(d);
88	struct bcm7120_l2_intc_data *b = gc->private;
89
90	irq_gc_lock(gc);
91	if (b->can_wake)
92		irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
93			       ct->regs.mask);
94	irq_gc_unlock(gc);
95}
96
97static void bcm7120_l2_intc_resume(struct irq_data *d)
98{
99	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
100	struct irq_chip_type *ct = irq_data_get_chip_type(d);
101
102	/* Restore the saved mask */
103	irq_gc_lock(gc);
104	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
105	irq_gc_unlock(gc);
106}
107
108static int bcm7120_l2_intc_init_one(struct device_node *dn,
109					struct bcm7120_l2_intc_data *data,
110					int irq)
111{
112	int parent_irq;
113	unsigned int idx;
114
115	parent_irq = irq_of_parse_and_map(dn, irq);
116	if (!parent_irq) {
117		pr_err("failed to map interrupt %d\n", irq);
118		return -EINVAL;
119	}
120
121	/* For multiple parent IRQs with multiple words, this looks like:
122	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
123	 */
124	for (idx = 0; idx < data->n_words; idx++) {
125		if (data->map_mask_prop) {
126			data->irq_map_mask[idx] |=
127				be32_to_cpup(data->map_mask_prop +
128					     irq * data->n_words + idx);
129		} else {
130			data->irq_map_mask[idx] = 0xffffffff;
131		}
132	}
133
134	irq_set_handler_data(parent_irq, data);
135	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
136
137	return 0;
138}
139
140static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
141					     struct bcm7120_l2_intc_data *data)
142{
143	int ret;
144
145	data->map_base[0] = of_iomap(dn, 0);
146	if (!data->map_base[0]) {
147		pr_err("unable to map registers\n");
148		return -ENOMEM;
149	}
150
151	data->pair_base[0] = data->map_base[0];
152	data->en_offset[0] = IRQEN;
153	data->stat_offset[0] = IRQSTAT;
154	data->n_words = 1;
155
156	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
157					 data->irq_fwd_mask, data->n_words);
158	if (ret != 0 && ret != -EINVAL) {
159		/* property exists but has the wrong number of words */
160		pr_err("invalid brcm,int-fwd-mask property\n");
161		return -EINVAL;
162	}
163
164	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
165	if (!data->map_mask_prop ||
166	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
167		pr_err("invalid brcm,int-map-mask property\n");
168		return -EINVAL;
169	}
170
171	return 0;
172}
173
174static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
175					     struct bcm7120_l2_intc_data *data)
176{
177	unsigned int gc_idx;
178
179	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
180		unsigned int map_idx = gc_idx * 2;
181		void __iomem *en = of_iomap(dn, map_idx + 0);
182		void __iomem *stat = of_iomap(dn, map_idx + 1);
183		void __iomem *base = min(en, stat);
184
185		data->map_base[map_idx + 0] = en;
186		data->map_base[map_idx + 1] = stat;
187
188		if (!base)
189			break;
190
191		data->pair_base[gc_idx] = base;
192		data->en_offset[gc_idx] = en - base;
193		data->stat_offset[gc_idx] = stat - base;
194	}
195
196	if (!gc_idx) {
197		pr_err("unable to map registers\n");
198		return -EINVAL;
199	}
200
201	data->n_words = gc_idx;
202	return 0;
203}
204
205int __init bcm7120_l2_intc_probe(struct device_node *dn,
206				 struct device_node *parent,
207				 int (*iomap_regs_fn)(struct device_node *,
208					struct bcm7120_l2_intc_data *),
209				 const char *intc_name)
210{
211	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
212	struct bcm7120_l2_intc_data *data;
213	struct irq_chip_generic *gc;
214	struct irq_chip_type *ct;
215	int ret = 0;
216	unsigned int idx, irq, flags;
217
218	data = kzalloc(sizeof(*data), GFP_KERNEL);
219	if (!data)
220		return -ENOMEM;
221
222	data->num_parent_irqs = of_irq_count(dn);
223	if (data->num_parent_irqs <= 0) {
224		pr_err("invalid number of parent interrupts\n");
225		ret = -ENOMEM;
226		goto out_unmap;
227	}
228
229	ret = iomap_regs_fn(dn, data);
230	if (ret < 0)
231		goto out_unmap;
232
233	for (idx = 0; idx < data->n_words; idx++) {
234		__raw_writel(data->irq_fwd_mask[idx],
235			     data->pair_base[idx] +
236			     data->en_offset[idx]);
237	}
238
239	for (irq = 0; irq < data->num_parent_irqs; irq++) {
240		ret = bcm7120_l2_intc_init_one(dn, data, irq);
241		if (ret)
242			goto out_unmap;
243	}
244
245	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
246					     &irq_generic_chip_ops, NULL);
247	if (!data->domain) {
248		ret = -ENOMEM;
249		goto out_unmap;
250	}
251
252	/* MIPS chips strapped for BE will automagically configure the
253	 * peripheral registers for CPU-native byte order.
254	 */
255	flags = IRQ_GC_INIT_MASK_CACHE;
256	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
257		flags |= IRQ_GC_BE_IO;
258
259	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
260				dn->full_name, handle_level_irq, clr, 0, flags);
261	if (ret) {
262		pr_err("failed to allocate generic irq chip\n");
263		goto out_free_domain;
264	}
265
266	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
267		data->can_wake = true;
268
269	for (idx = 0; idx < data->n_words; idx++) {
270		irq = idx * IRQS_PER_WORD;
271		gc = irq_get_domain_generic_chip(data->domain, irq);
272
273		gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
274		gc->private = data;
275		ct = gc->chip_types;
276
277		gc->reg_base = data->pair_base[idx];
278		ct->regs.mask = data->en_offset[idx];
279
280		ct->chip.irq_mask = irq_gc_mask_clr_bit;
281		ct->chip.irq_unmask = irq_gc_mask_set_bit;
282		ct->chip.irq_ack = irq_gc_noop;
283		ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
284		ct->chip.irq_resume = bcm7120_l2_intc_resume;
285
286		if (data->can_wake) {
287			/* This IRQ chip can wake the system, set all
288			 * relevant child interupts in wake_enabled mask
289			 */
290			gc->wake_enabled = 0xffffffff;
291			gc->wake_enabled &= ~gc->unused;
292			ct->chip.irq_set_wake = irq_gc_set_wake;
293		}
294	}
295
296	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
297			intc_name, data->map_base[0], data->num_parent_irqs);
298
299	return 0;
300
301out_free_domain:
302	irq_domain_remove(data->domain);
303out_unmap:
304	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
305		if (data->map_base[idx])
306			iounmap(data->map_base[idx]);
307	}
308	kfree(data);
309	return ret;
310}
311
312int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
313				      struct device_node *parent)
314{
315	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
316				     "BCM7120 L2");
317}
318
319int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
320				      struct device_node *parent)
321{
322	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
323				     "BCM3380 L2");
324}
325
326IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
327		bcm7120_l2_intc_probe_7120);
328
329IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
330		bcm7120_l2_intc_probe_3380);
331