103 	addr = __raw_readl(hose->reg_base + SH4_PCIALR);  in sh7780_pci_err_irq()
108 	status = __raw_readw(hose->reg_base + PCI_STATUS);  in sh7780_pci_err_irq()
116 			__raw_writew(cmd, hose->reg_base + PCI_STATUS);  in sh7780_pci_err_irq()
122 	status = __raw_readl(hose->reg_base + SH4_PCIAINT);  in sh7780_pci_err_irq()
130 	__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);  in sh7780_pci_err_irq()
135 	status = __raw_readl(hose->reg_base + SH4_PCIINT);  in sh7780_pci_err_irq()
143 	__raw_writel(cmd, hose->reg_base + SH4_PCIINT);  in sh7780_pci_err_irq()
157 	__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);  in sh7780_pci_serr_irq()
172 	__raw_writel(0, hose->reg_base + SH4_PCIAINT);  in sh7780_pci_setup_irqs()
180 		     PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);  in sh7780_pci_setup_irqs()
205 		     SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);  in sh7780_pci_setup_irqs()
213 		     SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);  in sh7780_pci_setup_irqs()
232 	tmp = __raw_readl(hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
234 	__raw_writel(tmp, hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
237 	tmp = __raw_readw(hose->reg_base + PCI_STATUS);  in sh7780_pci66_init()
239 	__raw_writew(tmp, hose->reg_base + PCI_STATUS);  in sh7780_pci66_init()
242 	tmp = __raw_readl(hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
244 	__raw_writel(tmp, hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
258 	chan->reg_base = 0xfe040000;  in sh7780_pci_init()
265 		     chan->reg_base + SH4_PCICR);  in sh7780_pci_init()
274 	id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);  in sh7780_pci_init()
280 	id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);  in sh7780_pci_init()
294 	       __raw_readb(chan->reg_base + PCI_REVISION_ID));  in sh7780_pci_init()
301 		     chan->reg_base + SH4_PCICR);  in sh7780_pci_init()
311 		__raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);  in sh7780_pci_init()
313 			     chan->reg_base + SH4_PCILSR1);  in sh7780_pci_init()
319 		__raw_writel(0, chan->reg_base + SH4_PCILAR1);  in sh7780_pci_init()
320 		__raw_writel(0, chan->reg_base + SH4_PCILSR1);  in sh7780_pci_init()
327 	__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);  in sh7780_pci_init()
329 		     chan->reg_base + SH4_PCILSR0);  in sh7780_pci_init()
341 	__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);  in sh7780_pci_init()
342 	__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);  in sh7780_pci_init()
343 	__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);  in sh7780_pci_init()
344 	__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);  in sh7780_pci_init()
372 			     chan->reg_base + SH7780_PCIMBMR(i - 1));  in sh7780_pci_init()
373 		__raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));  in sh7780_pci_init()
379 	__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);  in sh7780_pci_init()
380 	__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);  in sh7780_pci_init()
381 	__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);  in sh7780_pci_init()
385 		     PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);  in sh7780_pci_init()
393 		     chan->reg_base + SH4_PCICR);  in sh7780_pci_init()
402 	       (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ?  in sh7780_pci_init()