107 	void __iomem			*reg_base;  member
877 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);  in _rockchip_pmx_gpio_set_direction()
883 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);  in _rockchip_pmx_gpio_set_direction()
1313 	void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;  in rockchip_gpio_set()
1337 	data = readl(bank->reg_base + GPIO_EXT_PORT);  in rockchip_gpio_get()
1407 	pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);  in rockchip_irq_demux()
1431 			data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);  in rockchip_irq_demux()
1435 				polarity = readl_relaxed(bank->reg_base +  in rockchip_irq_demux()
1442 				       bank->reg_base + GPIO_INT_POLARITY);  in rockchip_irq_demux()
1447 				data = readl_relaxed(bank->reg_base +  in rockchip_irq_demux()
1476 	data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);  in rockchip_irq_set_type()
1478 	writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);  in rockchip_irq_set_type()
1490 	level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);  in rockchip_irq_set_type()
1491 	polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);  in rockchip_irq_set_type()
1502 		data = readl(bank->reg_base + GPIO_EXT_PORT);  in rockchip_irq_set_type()
1534 	writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);  in rockchip_irq_set_type()
1535 	writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);  in rockchip_irq_set_type()
1600 		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);  in rockchip_interrupts_register()
1601 		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);  in rockchip_interrupts_register()
1604 		gc->reg_base = bank->reg_base;  in rockchip_interrupts_register()
1697 	bank->reg_base = devm_ioremap_resource(info->dev, &res);  in rockchip_get_bank_data()
1698 	if (IS_ERR(bank->reg_base))  in rockchip_get_bank_data()
1699 		return PTR_ERR(bank->reg_base);  in rockchip_get_bank_data()