1/*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <drm/drmP.h>
14#include <drm/drm_crtc_helper.h>
15#include <drm/drm_mipi_dsi.h>
16#include <drm/drm_panel.h>
17
18#include <linux/clk.h>
19#include <linux/gpio/consumer.h>
20#include <linux/irq.h>
21#include <linux/of_device.h>
22#include <linux/of_gpio.h>
23#include <linux/phy/phy.h>
24#include <linux/regulator/consumer.h>
25#include <linux/component.h>
26
27#include <video/mipi_display.h>
28#include <video/videomode.h>
29
30#include "exynos_drm_crtc.h"
31#include "exynos_drm_drv.h"
32
33/* returns true iff both arguments logically differs */
34#define NEQV(a, b) (!(a) ^ !(b))
35
36#define DSIM_STATUS_REG		0x0	/* Status register */
37#define DSIM_SWRST_REG		0x4	/* Software reset register */
38#define DSIM_CLKCTRL_REG	0x8	/* Clock control register */
39#define DSIM_TIMEOUT_REG	0xc	/* Time out register */
40#define DSIM_CONFIG_REG		0x10	/* Configuration register */
41#define DSIM_ESCMODE_REG	0x14	/* Escape mode register */
42
43/* Main display image resolution register */
44#define DSIM_MDRESOL_REG	0x18
45#define DSIM_MVPORCH_REG	0x1c	/* Main display Vporch register */
46#define DSIM_MHPORCH_REG	0x20	/* Main display Hporch register */
47#define DSIM_MSYNC_REG		0x24	/* Main display sync area register */
48
49/* Sub display image resolution register */
50#define DSIM_SDRESOL_REG	0x28
51#define DSIM_INTSRC_REG		0x2c	/* Interrupt source register */
52#define DSIM_INTMSK_REG		0x30	/* Interrupt mask register */
53#define DSIM_PKTHDR_REG		0x34	/* Packet Header FIFO register */
54#define DSIM_PAYLOAD_REG	0x38	/* Payload FIFO register */
55#define DSIM_RXFIFO_REG		0x3c	/* Read FIFO register */
56#define DSIM_FIFOTHLD_REG	0x40	/* FIFO threshold level register */
57#define DSIM_FIFOCTRL_REG	0x44	/* FIFO status and control register */
58
59/* FIFO memory AC characteristic register */
60#define DSIM_PLLCTRL_REG	0x4c	/* PLL control register */
61#define DSIM_PHYACCHR_REG	0x54	/* D-PHY AC characteristic register */
62#define DSIM_PHYACCHR1_REG	0x58	/* D-PHY AC characteristic register1 */
63#define DSIM_PHYCTRL_REG	0x5c
64#define DSIM_PHYTIMING_REG	0x64
65#define DSIM_PHYTIMING1_REG	0x68
66#define DSIM_PHYTIMING2_REG	0x6c
67
68/* DSIM_STATUS */
69#define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
70#define DSIM_STOP_STATE_CLK		(1 << 8)
71#define DSIM_TX_READY_HS_CLK		(1 << 10)
72#define DSIM_PLL_STABLE			(1 << 31)
73
74/* DSIM_SWRST */
75#define DSIM_FUNCRST			(1 << 16)
76#define DSIM_SWRST			(1 << 0)
77
78/* DSIM_TIMEOUT */
79#define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
80#define DSIM_BTA_TIMEOUT(x)		((x) << 16)
81
82/* DSIM_CLKCTRL */
83#define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
84#define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
85#define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
86#define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
87#define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
88#define DSIM_BYTE_CLKEN			(1 << 24)
89#define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
90#define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
91#define DSIM_PLL_BYPASS			(1 << 27)
92#define DSIM_ESC_CLKEN			(1 << 28)
93#define DSIM_TX_REQUEST_HSCLK		(1 << 31)
94
95/* DSIM_CONFIG */
96#define DSIM_LANE_EN_CLK		(1 << 0)
97#define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
98#define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
99#define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
100#define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
101#define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
102#define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
103#define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
104#define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
105#define DSIM_SUB_VC			(((x) & 0x3) << 16)
106#define DSIM_MAIN_VC			(((x) & 0x3) << 18)
107#define DSIM_HSA_MODE			(1 << 20)
108#define DSIM_HBP_MODE			(1 << 21)
109#define DSIM_HFP_MODE			(1 << 22)
110#define DSIM_HSE_MODE			(1 << 23)
111#define DSIM_AUTO_MODE			(1 << 24)
112#define DSIM_VIDEO_MODE			(1 << 25)
113#define DSIM_BURST_MODE			(1 << 26)
114#define DSIM_SYNC_INFORM		(1 << 27)
115#define DSIM_EOT_DISABLE		(1 << 28)
116#define DSIM_MFLUSH_VS			(1 << 29)
117/* This flag is valid only for exynos3250/3472/4415/5260/5430 */
118#define DSIM_CLKLANE_STOP		(1 << 30)
119
120/* DSIM_ESCMODE */
121#define DSIM_TX_TRIGGER_RST		(1 << 4)
122#define DSIM_TX_LPDT_LP			(1 << 6)
123#define DSIM_CMD_LPDT_LP		(1 << 7)
124#define DSIM_FORCE_BTA			(1 << 16)
125#define DSIM_FORCE_STOP_STATE		(1 << 20)
126#define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
127#define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
128
129/* DSIM_MDRESOL */
130#define DSIM_MAIN_STAND_BY		(1 << 31)
131#define DSIM_MAIN_VRESOL(x)		(((x) & 0x7ff) << 16)
132#define DSIM_MAIN_HRESOL(x)		(((x) & 0X7ff) << 0)
133
134/* DSIM_MVPORCH */
135#define DSIM_CMD_ALLOW(x)		((x) << 28)
136#define DSIM_STABLE_VFP(x)		((x) << 16)
137#define DSIM_MAIN_VBP(x)		((x) << 0)
138#define DSIM_CMD_ALLOW_MASK		(0xf << 28)
139#define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
140#define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
141
142/* DSIM_MHPORCH */
143#define DSIM_MAIN_HFP(x)		((x) << 16)
144#define DSIM_MAIN_HBP(x)		((x) << 0)
145#define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
146#define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
147
148/* DSIM_MSYNC */
149#define DSIM_MAIN_VSA(x)		((x) << 22)
150#define DSIM_MAIN_HSA(x)		((x) << 0)
151#define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
152#define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
153
154/* DSIM_SDRESOL */
155#define DSIM_SUB_STANDY(x)		((x) << 31)
156#define DSIM_SUB_VRESOL(x)		((x) << 16)
157#define DSIM_SUB_HRESOL(x)		((x) << 0)
158#define DSIM_SUB_STANDY_MASK		((0x1) << 31)
159#define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
160#define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
161
162/* DSIM_INTSRC */
163#define DSIM_INT_PLL_STABLE		(1 << 31)
164#define DSIM_INT_SW_RST_RELEASE		(1 << 30)
165#define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
166#define DSIM_INT_BTA			(1 << 25)
167#define DSIM_INT_FRAME_DONE		(1 << 24)
168#define DSIM_INT_RX_TIMEOUT		(1 << 21)
169#define DSIM_INT_BTA_TIMEOUT		(1 << 20)
170#define DSIM_INT_RX_DONE		(1 << 18)
171#define DSIM_INT_RX_TE			(1 << 17)
172#define DSIM_INT_RX_ACK			(1 << 16)
173#define DSIM_INT_RX_ECC_ERR		(1 << 15)
174#define DSIM_INT_RX_CRC_ERR		(1 << 14)
175
176/* DSIM_FIFOCTRL */
177#define DSIM_RX_DATA_FULL		(1 << 25)
178#define DSIM_RX_DATA_EMPTY		(1 << 24)
179#define DSIM_SFR_HEADER_FULL		(1 << 23)
180#define DSIM_SFR_HEADER_EMPTY		(1 << 22)
181#define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
182#define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
183#define DSIM_I80_HEADER_FULL		(1 << 19)
184#define DSIM_I80_HEADER_EMPTY		(1 << 18)
185#define DSIM_I80_PAYLOAD_FULL		(1 << 17)
186#define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
187#define DSIM_SD_HEADER_FULL		(1 << 15)
188#define DSIM_SD_HEADER_EMPTY		(1 << 14)
189#define DSIM_SD_PAYLOAD_FULL		(1 << 13)
190#define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
191#define DSIM_MD_HEADER_FULL		(1 << 11)
192#define DSIM_MD_HEADER_EMPTY		(1 << 10)
193#define DSIM_MD_PAYLOAD_FULL		(1 << 9)
194#define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
195#define DSIM_RX_FIFO			(1 << 4)
196#define DSIM_SFR_FIFO			(1 << 3)
197#define DSIM_I80_FIFO			(1 << 2)
198#define DSIM_SD_FIFO			(1 << 1)
199#define DSIM_MD_FIFO			(1 << 0)
200
201/* DSIM_PHYACCHR */
202#define DSIM_AFC_EN			(1 << 14)
203#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
204
205/* DSIM_PLLCTRL */
206#define DSIM_FREQ_BAND(x)		((x) << 24)
207#define DSIM_PLL_EN			(1 << 23)
208#define DSIM_PLL_P(x)			((x) << 13)
209#define DSIM_PLL_M(x)			((x) << 4)
210#define DSIM_PLL_S(x)			((x) << 1)
211
212/* DSIM_PHYCTRL */
213#define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
214
215/* DSIM_PHYTIMING */
216#define DSIM_PHYTIMING_LPX(x)		((x) << 8)
217#define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
218
219/* DSIM_PHYTIMING1 */
220#define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
221#define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
222#define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
223#define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
224
225/* DSIM_PHYTIMING2 */
226#define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
227#define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
228#define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
229
230#define DSI_MAX_BUS_WIDTH		4
231#define DSI_NUM_VIRTUAL_CHANNELS	4
232#define DSI_TX_FIFO_SIZE		2048
233#define DSI_RX_FIFO_SIZE		256
234#define DSI_XFER_TIMEOUT_MS		100
235#define DSI_RX_FIFO_EMPTY		0x30800002
236
237enum exynos_dsi_transfer_type {
238	EXYNOS_DSI_TX,
239	EXYNOS_DSI_RX,
240};
241
242struct exynos_dsi_transfer {
243	struct list_head list;
244	struct completion completed;
245	int result;
246	u8 data_id;
247	u8 data[2];
248	u16 flags;
249
250	const u8 *tx_payload;
251	u16 tx_len;
252	u16 tx_done;
253
254	u8 *rx_payload;
255	u16 rx_len;
256	u16 rx_done;
257};
258
259#define DSIM_STATE_ENABLED		BIT(0)
260#define DSIM_STATE_INITIALIZED		BIT(1)
261#define DSIM_STATE_CMD_LPM		BIT(2)
262
263struct exynos_dsi_driver_data {
264	unsigned int plltmr_reg;
265
266	unsigned int has_freqband:1;
267	unsigned int has_clklane_stop:1;
268};
269
270struct exynos_dsi {
271	struct exynos_drm_display display;
272	struct mipi_dsi_host dsi_host;
273	struct drm_connector connector;
274	struct device_node *panel_node;
275	struct drm_panel *panel;
276	struct device *dev;
277
278	void __iomem *reg_base;
279	struct phy *phy;
280	struct clk *pll_clk;
281	struct clk *bus_clk;
282	struct regulator_bulk_data supplies[2];
283	int irq;
284	int te_gpio;
285
286	u32 pll_clk_rate;
287	u32 burst_clk_rate;
288	u32 esc_clk_rate;
289	u32 lanes;
290	u32 mode_flags;
291	u32 format;
292	struct videomode vm;
293
294	int state;
295	struct drm_property *brightness;
296	struct completion completed;
297
298	spinlock_t transfer_lock; /* protects transfer_list */
299	struct list_head transfer_list;
300
301	struct exynos_dsi_driver_data *driver_data;
302};
303
304#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
305#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
306
307static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
308{
309	return container_of(d, struct exynos_dsi, display);
310}
311
312static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
313	.plltmr_reg = 0x50,
314	.has_freqband = 1,
315	.has_clklane_stop = 1,
316};
317
318static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
319	.plltmr_reg = 0x50,
320	.has_freqband = 1,
321	.has_clklane_stop = 1,
322};
323
324static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
325	.plltmr_reg = 0x58,
326	.has_clklane_stop = 1,
327};
328
329static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
330	.plltmr_reg = 0x58,
331};
332
333static struct of_device_id exynos_dsi_of_match[] = {
334	{ .compatible = "samsung,exynos3250-mipi-dsi",
335	  .data = &exynos3_dsi_driver_data },
336	{ .compatible = "samsung,exynos4210-mipi-dsi",
337	  .data = &exynos4_dsi_driver_data },
338	{ .compatible = "samsung,exynos4415-mipi-dsi",
339	  .data = &exynos4415_dsi_driver_data },
340	{ .compatible = "samsung,exynos5410-mipi-dsi",
341	  .data = &exynos5_dsi_driver_data },
342	{ }
343};
344
345static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
346						struct platform_device *pdev)
347{
348	const struct of_device_id *of_id =
349			of_match_device(exynos_dsi_of_match, &pdev->dev);
350
351	return (struct exynos_dsi_driver_data *)of_id->data;
352}
353
354static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
355{
356	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
357		return;
358
359	dev_err(dsi->dev, "timeout waiting for reset\n");
360}
361
362static void exynos_dsi_reset(struct exynos_dsi *dsi)
363{
364	reinit_completion(&dsi->completed);
365	writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
366}
367
368#ifndef MHZ
369#define MHZ	(1000*1000)
370#endif
371
372static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
373		unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
374{
375	unsigned long best_freq = 0;
376	u32 min_delta = 0xffffffff;
377	u8 p_min, p_max;
378	u8 _p, uninitialized_var(best_p);
379	u16 _m, uninitialized_var(best_m);
380	u8 _s, uninitialized_var(best_s);
381
382	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
383	p_max = fin / (6 * MHZ);
384
385	for (_p = p_min; _p <= p_max; ++_p) {
386		for (_s = 0; _s <= 5; ++_s) {
387			u64 tmp;
388			u32 delta;
389
390			tmp = (u64)fout * (_p << _s);
391			do_div(tmp, fin);
392			_m = tmp;
393			if (_m < 41 || _m > 125)
394				continue;
395
396			tmp = (u64)_m * fin;
397			do_div(tmp, _p);
398			if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
399				continue;
400
401			tmp = (u64)_m * fin;
402			do_div(tmp, _p << _s);
403
404			delta = abs(fout - tmp);
405			if (delta < min_delta) {
406				best_p = _p;
407				best_m = _m;
408				best_s = _s;
409				min_delta = delta;
410				best_freq = tmp;
411			}
412		}
413	}
414
415	if (best_freq) {
416		*p = best_p;
417		*m = best_m;
418		*s = best_s;
419	}
420
421	return best_freq;
422}
423
424static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
425					unsigned long freq)
426{
427	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
428	unsigned long fin, fout;
429	int timeout;
430	u8 p, s;
431	u16 m;
432	u32 reg;
433
434	clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
435
436	fin = clk_get_rate(dsi->pll_clk);
437	if (!fin) {
438		dev_err(dsi->dev, "failed to get PLL clock frequency\n");
439		return 0;
440	}
441
442	dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
443
444	fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
445	if (!fout) {
446		dev_err(dsi->dev,
447			"failed to find PLL PMS for requested frequency\n");
448		return 0;
449	}
450	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
451
452	writel(500, dsi->reg_base + driver_data->plltmr_reg);
453
454	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
455
456	if (driver_data->has_freqband) {
457		static const unsigned long freq_bands[] = {
458			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
459			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
460			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
461			770 * MHZ, 870 * MHZ, 950 * MHZ,
462		};
463		int band;
464
465		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
466			if (fout < freq_bands[band])
467				break;
468
469		dev_dbg(dsi->dev, "band %d\n", band);
470
471		reg |= DSIM_FREQ_BAND(band);
472	}
473
474	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
475
476	timeout = 1000;
477	do {
478		if (timeout-- == 0) {
479			dev_err(dsi->dev, "PLL failed to stabilize\n");
480			return 0;
481		}
482		reg = readl(dsi->reg_base + DSIM_STATUS_REG);
483	} while ((reg & DSIM_PLL_STABLE) == 0);
484
485	return fout;
486}
487
488static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
489{
490	unsigned long hs_clk, byte_clk, esc_clk;
491	unsigned long esc_div;
492	u32 reg;
493
494	hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
495	if (!hs_clk) {
496		dev_err(dsi->dev, "failed to configure DSI PLL\n");
497		return -EFAULT;
498	}
499
500	byte_clk = hs_clk / 8;
501	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
502	esc_clk = byte_clk / esc_div;
503
504	if (esc_clk > 20 * MHZ) {
505		++esc_div;
506		esc_clk = byte_clk / esc_div;
507	}
508
509	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
510		hs_clk, byte_clk, esc_clk);
511
512	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
513	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
514			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
515			| DSIM_BYTE_CLK_SRC_MASK);
516	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
517			| DSIM_ESC_PRESCALER(esc_div)
518			| DSIM_LANE_ESC_CLK_EN_CLK
519			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
520			| DSIM_BYTE_CLK_SRC(0)
521			| DSIM_TX_REQUEST_HSCLK;
522	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
523
524	return 0;
525}
526
527static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
528{
529	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
530	u32 reg;
531
532	if (driver_data->has_freqband)
533		return;
534
535	/* B D-PHY: D-PHY Master & Slave Analog Block control */
536	reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
537	writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
538
539	/*
540	 * T LPX: Transmitted length of any Low-Power state period
541	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
542	 *	burst
543	 */
544	reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
545	writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
546
547	/*
548	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
549	 *	Line state immediately before the HS-0 Line state starting the
550	 *	HS transmission
551	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
552	 *	transmitting the Clock.
553	 * T CLK_POST: Time that the transmitter continues to send HS clock
554	 *	after the last associated Data Lane has transitioned to LP Mode
555	 *	Interval is defined as the period from the end of T HS-TRAIL to
556	 *	the beginning of T CLK-TRAIL
557	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
558	 *	the last payload clock bit of a HS transmission burst
559	 */
560	reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) |
561			DSIM_PHYTIMING1_CLK_ZERO(0x27) |
562			DSIM_PHYTIMING1_CLK_POST(0x0d) |
563			DSIM_PHYTIMING1_CLK_TRAIL(0x08);
564	writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
565
566	/*
567	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
568	 *	Line state immediately before the HS-0 Line state starting the
569	 *	HS transmission
570	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
571	 *	transmitting the Sync sequence.
572	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
573	 *	state after last payload data bit of a HS transmission burst
574	 */
575	reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
576			DSIM_PHYTIMING2_HS_TRAIL(0x0b);
577	writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
578}
579
580static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
581{
582	u32 reg;
583
584	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
585	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
586			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
587	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
588
589	reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
590	reg &= ~DSIM_PLL_EN;
591	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
592}
593
594static int exynos_dsi_init_link(struct exynos_dsi *dsi)
595{
596	struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
597	int timeout;
598	u32 reg;
599	u32 lanes_mask;
600
601	/* Initialize FIFO pointers */
602	reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
603	reg &= ~0x1f;
604	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
605
606	usleep_range(9000, 11000);
607
608	reg |= 0x1f;
609	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
610
611	usleep_range(9000, 11000);
612
613	/* DSI configuration */
614	reg = 0;
615
616	/*
617	 * The first bit of mode_flags specifies display configuration.
618	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
619	 * mode, otherwise it will support command mode.
620	 */
621	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
622		reg |= DSIM_VIDEO_MODE;
623
624		/*
625		 * The user manual describes that following bits are ignored in
626		 * command mode.
627		 */
628		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
629			reg |= DSIM_MFLUSH_VS;
630		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
631			reg |= DSIM_SYNC_INFORM;
632		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
633			reg |= DSIM_BURST_MODE;
634		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
635			reg |= DSIM_AUTO_MODE;
636		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
637			reg |= DSIM_HSE_MODE;
638		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
639			reg |= DSIM_HFP_MODE;
640		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
641			reg |= DSIM_HBP_MODE;
642		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
643			reg |= DSIM_HSA_MODE;
644	}
645
646	if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
647		reg |= DSIM_EOT_DISABLE;
648
649	switch (dsi->format) {
650	case MIPI_DSI_FMT_RGB888:
651		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
652		break;
653	case MIPI_DSI_FMT_RGB666:
654		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
655		break;
656	case MIPI_DSI_FMT_RGB666_PACKED:
657		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
658		break;
659	case MIPI_DSI_FMT_RGB565:
660		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
661		break;
662	default:
663		dev_err(dsi->dev, "invalid pixel format\n");
664		return -EINVAL;
665	}
666
667	reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
668
669	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
670
671	reg |= DSIM_LANE_EN_CLK;
672	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
673
674	lanes_mask = BIT(dsi->lanes) - 1;
675	reg |= DSIM_LANE_EN(lanes_mask);
676	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
677
678	/*
679	 * Use non-continuous clock mode if the periparal wants and
680	 * host controller supports
681	 *
682	 * In non-continous clock mode, host controller will turn off
683	 * the HS clock between high-speed transmissions to reduce
684	 * power consumption.
685	 */
686	if (driver_data->has_clklane_stop &&
687			dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
688		reg |= DSIM_CLKLANE_STOP;
689		writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
690	}
691
692	/* Check clock and data lane state are stop state */
693	timeout = 100;
694	do {
695		if (timeout-- == 0) {
696			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
697			return -EFAULT;
698		}
699
700		reg = readl(dsi->reg_base + DSIM_STATUS_REG);
701		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
702		    != DSIM_STOP_STATE_DAT(lanes_mask))
703			continue;
704	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
705
706	reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
707	reg &= ~DSIM_STOP_STATE_CNT_MASK;
708	reg |= DSIM_STOP_STATE_CNT(0xf);
709	writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
710
711	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
712	writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
713
714	return 0;
715}
716
717static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
718{
719	struct videomode *vm = &dsi->vm;
720	u32 reg;
721
722	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
723		reg = DSIM_CMD_ALLOW(0xf)
724			| DSIM_STABLE_VFP(vm->vfront_porch)
725			| DSIM_MAIN_VBP(vm->vback_porch);
726		writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
727
728		reg = DSIM_MAIN_HFP(vm->hfront_porch)
729			| DSIM_MAIN_HBP(vm->hback_porch);
730		writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
731
732		reg = DSIM_MAIN_VSA(vm->vsync_len)
733			| DSIM_MAIN_HSA(vm->hsync_len);
734		writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
735	}
736
737	reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
738	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
739
740	dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
741}
742
743static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
744{
745	u32 reg;
746
747	reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
748	if (enable)
749		reg |= DSIM_MAIN_STAND_BY;
750	else
751		reg &= ~DSIM_MAIN_STAND_BY;
752	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
753}
754
755static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
756{
757	int timeout = 2000;
758
759	do {
760		u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
761
762		if (!(reg & DSIM_SFR_HEADER_FULL))
763			return 0;
764
765		if (!cond_resched())
766			usleep_range(950, 1050);
767	} while (--timeout);
768
769	return -ETIMEDOUT;
770}
771
772static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
773{
774	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
775
776	if (lpm)
777		v |= DSIM_CMD_LPDT_LP;
778	else
779		v &= ~DSIM_CMD_LPDT_LP;
780
781	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
782}
783
784static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
785{
786	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
787
788	v |= DSIM_FORCE_BTA;
789	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
790}
791
792static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
793					struct exynos_dsi_transfer *xfer)
794{
795	struct device *dev = dsi->dev;
796	const u8 *payload = xfer->tx_payload + xfer->tx_done;
797	u16 length = xfer->tx_len - xfer->tx_done;
798	bool first = !xfer->tx_done;
799	u32 reg;
800
801	dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
802		xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
803
804	if (length > DSI_TX_FIFO_SIZE)
805		length = DSI_TX_FIFO_SIZE;
806
807	xfer->tx_done += length;
808
809	/* Send payload */
810	while (length >= 4) {
811		reg = (payload[3] << 24) | (payload[2] << 16)
812					| (payload[1] << 8) | payload[0];
813		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
814		payload += 4;
815		length -= 4;
816	}
817
818	reg = 0;
819	switch (length) {
820	case 3:
821		reg |= payload[2] << 16;
822		/* Fall through */
823	case 2:
824		reg |= payload[1] << 8;
825		/* Fall through */
826	case 1:
827		reg |= payload[0];
828		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
829		break;
830	case 0:
831		/* Do nothing */
832		break;
833	}
834
835	/* Send packet header */
836	if (!first)
837		return;
838
839	reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
840	if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
841		dev_err(dev, "waiting for header FIFO timed out\n");
842		return;
843	}
844
845	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
846		 dsi->state & DSIM_STATE_CMD_LPM)) {
847		exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
848		dsi->state ^= DSIM_STATE_CMD_LPM;
849	}
850
851	writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
852
853	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
854		exynos_dsi_force_bta(dsi);
855}
856
857static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
858					struct exynos_dsi_transfer *xfer)
859{
860	u8 *payload = xfer->rx_payload + xfer->rx_done;
861	bool first = !xfer->rx_done;
862	struct device *dev = dsi->dev;
863	u16 length;
864	u32 reg;
865
866	if (first) {
867		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
868
869		switch (reg & 0x3f) {
870		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
871		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
872			if (xfer->rx_len >= 2) {
873				payload[1] = reg >> 16;
874				++xfer->rx_done;
875			}
876			/* Fall through */
877		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
878		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
879			payload[0] = reg >> 8;
880			++xfer->rx_done;
881			xfer->rx_len = xfer->rx_done;
882			xfer->result = 0;
883			goto clear_fifo;
884		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
885			dev_err(dev, "DSI Error Report: 0x%04x\n",
886				(reg >> 8) & 0xffff);
887			xfer->result = 0;
888			goto clear_fifo;
889		}
890
891		length = (reg >> 8) & 0xffff;
892		if (length > xfer->rx_len) {
893			dev_err(dev,
894				"response too long (%u > %u bytes), stripping\n",
895				xfer->rx_len, length);
896			length = xfer->rx_len;
897		} else if (length < xfer->rx_len)
898			xfer->rx_len = length;
899	}
900
901	length = xfer->rx_len - xfer->rx_done;
902	xfer->rx_done += length;
903
904	/* Receive payload */
905	while (length >= 4) {
906		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
907		payload[0] = (reg >>  0) & 0xff;
908		payload[1] = (reg >>  8) & 0xff;
909		payload[2] = (reg >> 16) & 0xff;
910		payload[3] = (reg >> 24) & 0xff;
911		payload += 4;
912		length -= 4;
913	}
914
915	if (length) {
916		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
917		switch (length) {
918		case 3:
919			payload[2] = (reg >> 16) & 0xff;
920			/* Fall through */
921		case 2:
922			payload[1] = (reg >> 8) & 0xff;
923			/* Fall through */
924		case 1:
925			payload[0] = reg & 0xff;
926		}
927	}
928
929	if (xfer->rx_done == xfer->rx_len)
930		xfer->result = 0;
931
932clear_fifo:
933	length = DSI_RX_FIFO_SIZE / 4;
934	do {
935		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
936		if (reg == DSI_RX_FIFO_EMPTY)
937			break;
938	} while (--length);
939}
940
941static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
942{
943	unsigned long flags;
944	struct exynos_dsi_transfer *xfer;
945	bool start = false;
946
947again:
948	spin_lock_irqsave(&dsi->transfer_lock, flags);
949
950	if (list_empty(&dsi->transfer_list)) {
951		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
952		return;
953	}
954
955	xfer = list_first_entry(&dsi->transfer_list,
956					struct exynos_dsi_transfer, list);
957
958	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
959
960	if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
961		/* waiting for RX */
962		return;
963
964	exynos_dsi_send_to_fifo(dsi, xfer);
965
966	if (xfer->tx_len || xfer->rx_len)
967		return;
968
969	xfer->result = 0;
970	complete(&xfer->completed);
971
972	spin_lock_irqsave(&dsi->transfer_lock, flags);
973
974	list_del_init(&xfer->list);
975	start = !list_empty(&dsi->transfer_list);
976
977	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
978
979	if (start)
980		goto again;
981}
982
983static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
984{
985	struct exynos_dsi_transfer *xfer;
986	unsigned long flags;
987	bool start = true;
988
989	spin_lock_irqsave(&dsi->transfer_lock, flags);
990
991	if (list_empty(&dsi->transfer_list)) {
992		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
993		return false;
994	}
995
996	xfer = list_first_entry(&dsi->transfer_list,
997					struct exynos_dsi_transfer, list);
998
999	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1000
1001	dev_dbg(dsi->dev,
1002		"> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
1003		xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1004
1005	if (xfer->tx_done != xfer->tx_len)
1006		return true;
1007
1008	if (xfer->rx_done != xfer->rx_len)
1009		exynos_dsi_read_from_fifo(dsi, xfer);
1010
1011	if (xfer->rx_done != xfer->rx_len)
1012		return true;
1013
1014	spin_lock_irqsave(&dsi->transfer_lock, flags);
1015
1016	list_del_init(&xfer->list);
1017	start = !list_empty(&dsi->transfer_list);
1018
1019	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1020
1021	if (!xfer->rx_len)
1022		xfer->result = 0;
1023	complete(&xfer->completed);
1024
1025	return start;
1026}
1027
1028static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1029					struct exynos_dsi_transfer *xfer)
1030{
1031	unsigned long flags;
1032	bool start;
1033
1034	spin_lock_irqsave(&dsi->transfer_lock, flags);
1035
1036	if (!list_empty(&dsi->transfer_list) &&
1037	    xfer == list_first_entry(&dsi->transfer_list,
1038				     struct exynos_dsi_transfer, list)) {
1039		list_del_init(&xfer->list);
1040		start = !list_empty(&dsi->transfer_list);
1041		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1042		if (start)
1043			exynos_dsi_transfer_start(dsi);
1044		return;
1045	}
1046
1047	list_del_init(&xfer->list);
1048
1049	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1050}
1051
1052static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1053					struct exynos_dsi_transfer *xfer)
1054{
1055	unsigned long flags;
1056	bool stopped;
1057
1058	xfer->tx_done = 0;
1059	xfer->rx_done = 0;
1060	xfer->result = -ETIMEDOUT;
1061	init_completion(&xfer->completed);
1062
1063	spin_lock_irqsave(&dsi->transfer_lock, flags);
1064
1065	stopped = list_empty(&dsi->transfer_list);
1066	list_add_tail(&xfer->list, &dsi->transfer_list);
1067
1068	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1069
1070	if (stopped)
1071		exynos_dsi_transfer_start(dsi);
1072
1073	wait_for_completion_timeout(&xfer->completed,
1074				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1075	if (xfer->result == -ETIMEDOUT) {
1076		exynos_dsi_remove_transfer(dsi, xfer);
1077		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1078			xfer->tx_len, xfer->tx_payload);
1079		return -ETIMEDOUT;
1080	}
1081
1082	/* Also covers hardware timeout condition */
1083	return xfer->result;
1084}
1085
1086static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1087{
1088	struct exynos_dsi *dsi = dev_id;
1089	u32 status;
1090
1091	status = readl(dsi->reg_base + DSIM_INTSRC_REG);
1092	if (!status) {
1093		static unsigned long int j;
1094		if (printk_timed_ratelimit(&j, 500))
1095			dev_warn(dsi->dev, "spurious interrupt\n");
1096		return IRQ_HANDLED;
1097	}
1098	writel(status, dsi->reg_base + DSIM_INTSRC_REG);
1099
1100	if (status & DSIM_INT_SW_RST_RELEASE) {
1101		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
1102		writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
1103		complete(&dsi->completed);
1104		return IRQ_HANDLED;
1105	}
1106
1107	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
1108		return IRQ_HANDLED;
1109
1110	if (exynos_dsi_transfer_finish(dsi))
1111		exynos_dsi_transfer_start(dsi);
1112
1113	return IRQ_HANDLED;
1114}
1115
1116static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1117{
1118	struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1119	struct drm_encoder *encoder = dsi->display.encoder;
1120
1121	if (dsi->state & DSIM_STATE_ENABLED)
1122		exynos_drm_crtc_te_handler(encoder->crtc);
1123
1124	return IRQ_HANDLED;
1125}
1126
1127static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1128{
1129	enable_irq(dsi->irq);
1130
1131	if (gpio_is_valid(dsi->te_gpio))
1132		enable_irq(gpio_to_irq(dsi->te_gpio));
1133}
1134
1135static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1136{
1137	if (gpio_is_valid(dsi->te_gpio))
1138		disable_irq(gpio_to_irq(dsi->te_gpio));
1139
1140	disable_irq(dsi->irq);
1141}
1142
1143static int exynos_dsi_init(struct exynos_dsi *dsi)
1144{
1145	exynos_dsi_reset(dsi);
1146	exynos_dsi_enable_irq(dsi);
1147	exynos_dsi_enable_clock(dsi);
1148	exynos_dsi_wait_for_reset(dsi);
1149	exynos_dsi_set_phy_ctrl(dsi);
1150	exynos_dsi_init_link(dsi);
1151
1152	return 0;
1153}
1154
1155static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1156{
1157	int ret;
1158	int te_gpio_irq;
1159
1160	dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1161	if (!gpio_is_valid(dsi->te_gpio)) {
1162		dev_err(dsi->dev, "no te-gpios specified\n");
1163		ret = dsi->te_gpio;
1164		goto out;
1165	}
1166
1167	ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1168	if (ret) {
1169		dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1170		goto out;
1171	}
1172
1173	te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1174
1175	irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1176	ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1177					IRQF_TRIGGER_RISING, "TE", dsi);
1178	if (ret) {
1179		dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1180		gpio_free(dsi->te_gpio);
1181		goto out;
1182	}
1183
1184out:
1185	return ret;
1186}
1187
1188static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1189{
1190	if (gpio_is_valid(dsi->te_gpio)) {
1191		free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1192		gpio_free(dsi->te_gpio);
1193		dsi->te_gpio = -ENOENT;
1194	}
1195}
1196
1197static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1198				  struct mipi_dsi_device *device)
1199{
1200	struct exynos_dsi *dsi = host_to_dsi(host);
1201
1202	dsi->lanes = device->lanes;
1203	dsi->format = device->format;
1204	dsi->mode_flags = device->mode_flags;
1205	dsi->panel_node = device->dev.of_node;
1206
1207	/*
1208	 * This is a temporary solution and should be made by more generic way.
1209	 *
1210	 * If attached panel device is for command mode one, dsi should register
1211	 * TE interrupt handler.
1212	 */
1213	if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1214		int ret = exynos_dsi_register_te_irq(dsi);
1215
1216		if (ret)
1217			return ret;
1218	}
1219
1220	if (dsi->connector.dev)
1221		drm_helper_hpd_irq_event(dsi->connector.dev);
1222
1223	return 0;
1224}
1225
1226static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1227				  struct mipi_dsi_device *device)
1228{
1229	struct exynos_dsi *dsi = host_to_dsi(host);
1230
1231	exynos_dsi_unregister_te_irq(dsi);
1232
1233	dsi->panel_node = NULL;
1234
1235	if (dsi->connector.dev)
1236		drm_helper_hpd_irq_event(dsi->connector.dev);
1237
1238	return 0;
1239}
1240
1241/* distinguish between short and long DSI packet types */
1242static bool exynos_dsi_is_short_dsi_type(u8 type)
1243{
1244	return (type & 0x0f) <= 8;
1245}
1246
1247static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1248				        const struct mipi_dsi_msg *msg)
1249{
1250	struct exynos_dsi *dsi = host_to_dsi(host);
1251	struct exynos_dsi_transfer xfer;
1252	int ret;
1253
1254	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1255		ret = exynos_dsi_init(dsi);
1256		if (ret)
1257			return ret;
1258		dsi->state |= DSIM_STATE_INITIALIZED;
1259	}
1260
1261	if (msg->tx_len == 0)
1262		return -EINVAL;
1263
1264	xfer.data_id = msg->type | (msg->channel << 6);
1265
1266	if (exynos_dsi_is_short_dsi_type(msg->type)) {
1267		const char *tx_buf = msg->tx_buf;
1268
1269		if (msg->tx_len > 2)
1270			return -EINVAL;
1271		xfer.tx_len = 0;
1272		xfer.data[0] = tx_buf[0];
1273		xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1274	} else {
1275		xfer.tx_len = msg->tx_len;
1276		xfer.data[0] = msg->tx_len & 0xff;
1277		xfer.data[1] = msg->tx_len >> 8;
1278		xfer.tx_payload = msg->tx_buf;
1279	}
1280
1281	xfer.rx_len = msg->rx_len;
1282	xfer.rx_payload = msg->rx_buf;
1283	xfer.flags = msg->flags;
1284
1285	ret = exynos_dsi_transfer(dsi, &xfer);
1286	return (ret < 0) ? ret : xfer.rx_done;
1287}
1288
1289static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1290	.attach = exynos_dsi_host_attach,
1291	.detach = exynos_dsi_host_detach,
1292	.transfer = exynos_dsi_host_transfer,
1293};
1294
1295static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1296{
1297	int ret;
1298
1299	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1300	if (ret < 0) {
1301		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1302		return ret;
1303	}
1304
1305	ret = clk_prepare_enable(dsi->bus_clk);
1306	if (ret < 0) {
1307		dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1308		goto err_bus_clk;
1309	}
1310
1311	ret = clk_prepare_enable(dsi->pll_clk);
1312	if (ret < 0) {
1313		dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1314		goto err_pll_clk;
1315	}
1316
1317	ret = phy_power_on(dsi->phy);
1318	if (ret < 0) {
1319		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1320		goto err_phy;
1321	}
1322
1323	return 0;
1324
1325err_phy:
1326	clk_disable_unprepare(dsi->pll_clk);
1327err_pll_clk:
1328	clk_disable_unprepare(dsi->bus_clk);
1329err_bus_clk:
1330	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1331
1332	return ret;
1333}
1334
1335static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1336{
1337	int ret;
1338
1339	usleep_range(10000, 20000);
1340
1341	if (dsi->state & DSIM_STATE_INITIALIZED) {
1342		dsi->state &= ~DSIM_STATE_INITIALIZED;
1343
1344		exynos_dsi_disable_clock(dsi);
1345
1346		exynos_dsi_disable_irq(dsi);
1347	}
1348
1349	dsi->state &= ~DSIM_STATE_CMD_LPM;
1350
1351	phy_power_off(dsi->phy);
1352
1353	clk_disable_unprepare(dsi->pll_clk);
1354	clk_disable_unprepare(dsi->bus_clk);
1355
1356	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1357	if (ret < 0)
1358		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1359}
1360
1361static int exynos_dsi_enable(struct exynos_dsi *dsi)
1362{
1363	int ret;
1364
1365	if (dsi->state & DSIM_STATE_ENABLED)
1366		return 0;
1367
1368	ret = exynos_dsi_poweron(dsi);
1369	if (ret < 0)
1370		return ret;
1371
1372	ret = drm_panel_prepare(dsi->panel);
1373	if (ret < 0) {
1374		exynos_dsi_poweroff(dsi);
1375		return ret;
1376	}
1377
1378	exynos_dsi_set_display_mode(dsi);
1379	exynos_dsi_set_display_enable(dsi, true);
1380
1381	dsi->state |= DSIM_STATE_ENABLED;
1382
1383	ret = drm_panel_enable(dsi->panel);
1384	if (ret < 0) {
1385		dsi->state &= ~DSIM_STATE_ENABLED;
1386		exynos_dsi_set_display_enable(dsi, false);
1387		drm_panel_unprepare(dsi->panel);
1388		exynos_dsi_poweroff(dsi);
1389		return ret;
1390	}
1391
1392	return 0;
1393}
1394
1395static void exynos_dsi_disable(struct exynos_dsi *dsi)
1396{
1397	if (!(dsi->state & DSIM_STATE_ENABLED))
1398		return;
1399
1400	drm_panel_disable(dsi->panel);
1401	exynos_dsi_set_display_enable(dsi, false);
1402	drm_panel_unprepare(dsi->panel);
1403	exynos_dsi_poweroff(dsi);
1404
1405	dsi->state &= ~DSIM_STATE_ENABLED;
1406}
1407
1408static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1409{
1410	struct exynos_dsi *dsi = display_to_dsi(display);
1411
1412	if (dsi->panel) {
1413		switch (mode) {
1414		case DRM_MODE_DPMS_ON:
1415			exynos_dsi_enable(dsi);
1416			break;
1417		case DRM_MODE_DPMS_STANDBY:
1418		case DRM_MODE_DPMS_SUSPEND:
1419		case DRM_MODE_DPMS_OFF:
1420			exynos_dsi_disable(dsi);
1421			break;
1422		default:
1423			break;
1424		}
1425	}
1426}
1427
1428static enum drm_connector_status
1429exynos_dsi_detect(struct drm_connector *connector, bool force)
1430{
1431	struct exynos_dsi *dsi = connector_to_dsi(connector);
1432
1433	if (!dsi->panel) {
1434		dsi->panel = of_drm_find_panel(dsi->panel_node);
1435		if (dsi->panel)
1436			drm_panel_attach(dsi->panel, &dsi->connector);
1437	} else if (!dsi->panel_node) {
1438		struct exynos_drm_display *display;
1439
1440		display = platform_get_drvdata(to_platform_device(dsi->dev));
1441		exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1442		drm_panel_detach(dsi->panel);
1443		dsi->panel = NULL;
1444	}
1445
1446	if (dsi->panel)
1447		return connector_status_connected;
1448
1449	return connector_status_disconnected;
1450}
1451
1452static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1453{
1454	drm_connector_unregister(connector);
1455	drm_connector_cleanup(connector);
1456	connector->dev = NULL;
1457}
1458
1459static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1460	.dpms = drm_helper_connector_dpms,
1461	.detect = exynos_dsi_detect,
1462	.fill_modes = drm_helper_probe_single_connector_modes,
1463	.destroy = exynos_dsi_connector_destroy,
1464};
1465
1466static int exynos_dsi_get_modes(struct drm_connector *connector)
1467{
1468	struct exynos_dsi *dsi = connector_to_dsi(connector);
1469
1470	if (dsi->panel)
1471		return dsi->panel->funcs->get_modes(dsi->panel);
1472
1473	return 0;
1474}
1475
1476static struct drm_encoder *
1477exynos_dsi_best_encoder(struct drm_connector *connector)
1478{
1479	struct exynos_dsi *dsi = connector_to_dsi(connector);
1480
1481	return dsi->display.encoder;
1482}
1483
1484static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1485	.get_modes = exynos_dsi_get_modes,
1486	.best_encoder = exynos_dsi_best_encoder,
1487};
1488
1489static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1490				       struct drm_encoder *encoder)
1491{
1492	struct exynos_dsi *dsi = display_to_dsi(display);
1493	struct drm_connector *connector = &dsi->connector;
1494	int ret;
1495
1496	connector->polled = DRM_CONNECTOR_POLL_HPD;
1497
1498	ret = drm_connector_init(encoder->dev, connector,
1499				 &exynos_dsi_connector_funcs,
1500				 DRM_MODE_CONNECTOR_DSI);
1501	if (ret) {
1502		DRM_ERROR("Failed to initialize connector with drm\n");
1503		return ret;
1504	}
1505
1506	drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1507	drm_connector_register(connector);
1508	drm_mode_connector_attach_encoder(connector, encoder);
1509
1510	return 0;
1511}
1512
1513static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1514			 struct drm_display_mode *mode)
1515{
1516	struct exynos_dsi *dsi = display_to_dsi(display);
1517	struct videomode *vm = &dsi->vm;
1518
1519	vm->hactive = mode->hdisplay;
1520	vm->vactive = mode->vdisplay;
1521	vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1522	vm->vback_porch = mode->vtotal - mode->vsync_end;
1523	vm->vsync_len = mode->vsync_end - mode->vsync_start;
1524	vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1525	vm->hback_porch = mode->htotal - mode->hsync_end;
1526	vm->hsync_len = mode->hsync_end - mode->hsync_start;
1527}
1528
1529static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1530	.create_connector = exynos_dsi_create_connector,
1531	.mode_set = exynos_dsi_mode_set,
1532	.dpms = exynos_dsi_dpms
1533};
1534
1535MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1536
1537/* of_* functions will be removed after merge of of_graph patches */
1538static struct device_node *
1539of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1540{
1541	struct device_node *np;
1542
1543	for_each_child_of_node(parent, np) {
1544		u32 r;
1545
1546		if (!np->name || of_node_cmp(np->name, name))
1547			continue;
1548
1549		if (of_property_read_u32(np, "reg", &r) < 0)
1550			r = 0;
1551
1552		if (reg == r)
1553			break;
1554	}
1555
1556	return np;
1557}
1558
1559static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1560						    u32 reg)
1561{
1562	struct device_node *ports, *port;
1563
1564	ports = of_get_child_by_name(parent, "ports");
1565	if (ports)
1566		parent = ports;
1567
1568	port = of_get_child_by_name_reg(parent, "port", reg);
1569
1570	of_node_put(ports);
1571
1572	return port;
1573}
1574
1575static struct device_node *
1576of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1577{
1578	return of_get_child_by_name_reg(port, "endpoint", reg);
1579}
1580
1581static int exynos_dsi_of_read_u32(const struct device_node *np,
1582				  const char *propname, u32 *out_value)
1583{
1584	int ret = of_property_read_u32(np, propname, out_value);
1585
1586	if (ret < 0)
1587		pr_err("%s: failed to get '%s' property\n", np->full_name,
1588		       propname);
1589
1590	return ret;
1591}
1592
1593enum {
1594	DSI_PORT_IN,
1595	DSI_PORT_OUT
1596};
1597
1598static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1599{
1600	struct device *dev = dsi->dev;
1601	struct device_node *node = dev->of_node;
1602	struct device_node *port, *ep;
1603	int ret;
1604
1605	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1606				     &dsi->pll_clk_rate);
1607	if (ret < 0)
1608		return ret;
1609
1610	port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1611	if (!port) {
1612		dev_err(dev, "no output port specified\n");
1613		return -EINVAL;
1614	}
1615
1616	ep = of_graph_get_endpoint_by_reg(port, 0);
1617	of_node_put(port);
1618	if (!ep) {
1619		dev_err(dev, "no endpoint specified in output port\n");
1620		return -EINVAL;
1621	}
1622
1623	ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1624				     &dsi->burst_clk_rate);
1625	if (ret < 0)
1626		goto end;
1627
1628	ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1629				     &dsi->esc_clk_rate);
1630
1631end:
1632	of_node_put(ep);
1633
1634	return ret;
1635}
1636
1637static int exynos_dsi_bind(struct device *dev, struct device *master,
1638				void *data)
1639{
1640	struct exynos_drm_display *display = dev_get_drvdata(dev);
1641	struct exynos_dsi *dsi = display_to_dsi(display);
1642	struct drm_device *drm_dev = data;
1643	int ret;
1644
1645	ret = exynos_drm_create_enc_conn(drm_dev, display);
1646	if (ret) {
1647		DRM_ERROR("Encoder create [%d] failed with %d\n",
1648			  display->type, ret);
1649		return ret;
1650	}
1651
1652	return mipi_dsi_host_register(&dsi->dsi_host);
1653}
1654
1655static void exynos_dsi_unbind(struct device *dev, struct device *master,
1656				void *data)
1657{
1658	struct exynos_drm_display *display = dev_get_drvdata(dev);
1659	struct exynos_dsi *dsi = display_to_dsi(display);
1660
1661	exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1662
1663	mipi_dsi_host_unregister(&dsi->dsi_host);
1664}
1665
1666static const struct component_ops exynos_dsi_component_ops = {
1667	.bind	= exynos_dsi_bind,
1668	.unbind	= exynos_dsi_unbind,
1669};
1670
1671static int exynos_dsi_probe(struct platform_device *pdev)
1672{
1673	struct device *dev = &pdev->dev;
1674	struct resource *res;
1675	struct exynos_dsi *dsi;
1676	int ret;
1677
1678	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1679	if (!dsi)
1680		return -ENOMEM;
1681
1682	dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1683	dsi->display.ops = &exynos_dsi_display_ops;
1684
1685	ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1686				       dsi->display.type);
1687	if (ret)
1688		return ret;
1689
1690	/* To be checked as invalid one */
1691	dsi->te_gpio = -ENOENT;
1692
1693	init_completion(&dsi->completed);
1694	spin_lock_init(&dsi->transfer_lock);
1695	INIT_LIST_HEAD(&dsi->transfer_list);
1696
1697	dsi->dsi_host.ops = &exynos_dsi_ops;
1698	dsi->dsi_host.dev = dev;
1699
1700	dsi->dev = dev;
1701	dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1702
1703	ret = exynos_dsi_parse_dt(dsi);
1704	if (ret)
1705		goto err_del_component;
1706
1707	dsi->supplies[0].supply = "vddcore";
1708	dsi->supplies[1].supply = "vddio";
1709	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1710				      dsi->supplies);
1711	if (ret) {
1712		dev_info(dev, "failed to get regulators: %d\n", ret);
1713		return -EPROBE_DEFER;
1714	}
1715
1716	dsi->pll_clk = devm_clk_get(dev, "pll_clk");
1717	if (IS_ERR(dsi->pll_clk)) {
1718		dev_info(dev, "failed to get dsi pll input clock\n");
1719		ret = PTR_ERR(dsi->pll_clk);
1720		goto err_del_component;
1721	}
1722
1723	dsi->bus_clk = devm_clk_get(dev, "bus_clk");
1724	if (IS_ERR(dsi->bus_clk)) {
1725		dev_info(dev, "failed to get dsi bus clock\n");
1726		ret = PTR_ERR(dsi->bus_clk);
1727		goto err_del_component;
1728	}
1729
1730	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1731	dsi->reg_base = devm_ioremap_resource(dev, res);
1732	if (IS_ERR(dsi->reg_base)) {
1733		dev_err(dev, "failed to remap io region\n");
1734		ret = PTR_ERR(dsi->reg_base);
1735		goto err_del_component;
1736	}
1737
1738	dsi->phy = devm_phy_get(dev, "dsim");
1739	if (IS_ERR(dsi->phy)) {
1740		dev_info(dev, "failed to get dsim phy\n");
1741		ret = PTR_ERR(dsi->phy);
1742		goto err_del_component;
1743	}
1744
1745	dsi->irq = platform_get_irq(pdev, 0);
1746	if (dsi->irq < 0) {
1747		dev_err(dev, "failed to request dsi irq resource\n");
1748		ret = dsi->irq;
1749		goto err_del_component;
1750	}
1751
1752	irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1753	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1754					exynos_dsi_irq, IRQF_ONESHOT,
1755					dev_name(dev), dsi);
1756	if (ret) {
1757		dev_err(dev, "failed to request dsi irq\n");
1758		goto err_del_component;
1759	}
1760
1761	platform_set_drvdata(pdev, &dsi->display);
1762
1763	ret = component_add(dev, &exynos_dsi_component_ops);
1764	if (ret)
1765		goto err_del_component;
1766
1767	return ret;
1768
1769err_del_component:
1770	exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1771	return ret;
1772}
1773
1774static int exynos_dsi_remove(struct platform_device *pdev)
1775{
1776	component_del(&pdev->dev, &exynos_dsi_component_ops);
1777	exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1778
1779	return 0;
1780}
1781
1782struct platform_driver dsi_driver = {
1783	.probe = exynos_dsi_probe,
1784	.remove = exynos_dsi_remove,
1785	.driver = {
1786		   .name = "exynos-dsi",
1787		   .owner = THIS_MODULE,
1788		   .of_match_table = exynos_dsi_of_match,
1789	},
1790};
1791
1792MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1793MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1794MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1795MODULE_LICENSE("GPL v2");
1796