278 	void __iomem *reg_base;  member
365 	writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);  in exynos_dsi_reset()
452 	writel(500, dsi->reg_base + driver_data->plltmr_reg);  in exynos_dsi_set_pll()
474 	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);  in exynos_dsi_set_pll()
482 		reg = readl(dsi->reg_base + DSIM_STATUS_REG);  in exynos_dsi_set_pll()
512 	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);  in exynos_dsi_enable_clock()
522 	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);  in exynos_dsi_enable_clock()
537 	writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);  in exynos_dsi_set_phy_ctrl()
545 	writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);  in exynos_dsi_set_phy_ctrl()
564 	writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);  in exynos_dsi_set_phy_ctrl()
577 	writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);  in exynos_dsi_set_phy_ctrl()
584 	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);  in exynos_dsi_disable_clock()
587 	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);  in exynos_dsi_disable_clock()
589 	reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);  in exynos_dsi_disable_clock()
591 	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);  in exynos_dsi_disable_clock()
602 	reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);  in exynos_dsi_init_link()
604 	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);  in exynos_dsi_init_link()
609 	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);  in exynos_dsi_init_link()
669 	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);  in exynos_dsi_init_link()
672 	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);  in exynos_dsi_init_link()
676 	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);  in exynos_dsi_init_link()
689 		writel(reg, dsi->reg_base + DSIM_CONFIG_REG);  in exynos_dsi_init_link()
700 		reg = readl(dsi->reg_base + DSIM_STATUS_REG);  in exynos_dsi_init_link()
706 	reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);  in exynos_dsi_init_link()
709 	writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);  in exynos_dsi_init_link()
712 	writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);  in exynos_dsi_init_link()
726 		writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);  in exynos_dsi_set_display_mode()
730 		writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);  in exynos_dsi_set_display_mode()
734 		writel(reg, dsi->reg_base + DSIM_MSYNC_REG);  in exynos_dsi_set_display_mode()
738 	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);  in exynos_dsi_set_display_mode()
747 	reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);  in exynos_dsi_set_display_enable()
752 	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);  in exynos_dsi_set_display_enable()
760 		u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);  in exynos_dsi_wait_for_hdr_fifo()
774 	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);  in exynos_dsi_set_cmd_lpm()
781 	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);  in exynos_dsi_set_cmd_lpm()
786 	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);  in exynos_dsi_force_bta()
789 	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);  in exynos_dsi_force_bta()
813 		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);  in exynos_dsi_send_to_fifo()
828 		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);  in exynos_dsi_send_to_fifo()
851 	writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);  in exynos_dsi_send_to_fifo()
867 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);  in exynos_dsi_read_from_fifo()
906 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);  in exynos_dsi_read_from_fifo()
916 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);  in exynos_dsi_read_from_fifo()
935 		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);  in exynos_dsi_read_from_fifo()
1091 	status = readl(dsi->reg_base + DSIM_INTSRC_REG);  in exynos_dsi_irq()
1098 	writel(status, dsi->reg_base + DSIM_INTSRC_REG);  in exynos_dsi_irq()
1102 		writel(mask, dsi->reg_base + DSIM_INTMSK_REG);  in exynos_dsi_irq()
1731 	dsi->reg_base = devm_ioremap_resource(dev, res);  in exynos_dsi_probe()
1732 	if (IS_ERR(dsi->reg_base)) {  in exynos_dsi_probe()
1734 		ret = PTR_ERR(dsi->reg_base);  in exynos_dsi_probe()