| /linux-4.1.27/drivers/clk/ti/ |
| H A D | Makefile | 1 obj-y += clk.o autoidle.o clockdomain.o
2 clk-common = dpll.o composite.o divider.o gate.o \
4 obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
5 obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
6 obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
7 obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
8 clk-3xxx.o
9 obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
10 obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
11 obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
12 clk-dra7-atl.o
13 obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o
16 obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
|
| H A D | autoidle.c | 18 #include <linux/clk-provider.h>
23 #include <linux/clk/ti.h>
37 static void ti_allow_autoidle(struct clk_ti_autoidle *clk) ti_allow_autoidle() argument
41 val = ti_clk_ll_ops->clk_readl(clk->reg); ti_allow_autoidle()
43 if (clk->flags & AUTOIDLE_LOW) ti_allow_autoidle()
44 val &= ~(1 << clk->shift); ti_allow_autoidle()
46 val |= (1 << clk->shift); ti_allow_autoidle()
48 ti_clk_ll_ops->clk_writel(val, clk->reg); ti_allow_autoidle()
51 static void ti_deny_autoidle(struct clk_ti_autoidle *clk) ti_deny_autoidle() argument
55 val = ti_clk_ll_ops->clk_readl(clk->reg); ti_deny_autoidle()
57 if (clk->flags & AUTOIDLE_LOW) ti_deny_autoidle()
58 val |= (1 << clk->shift); ti_deny_autoidle()
60 val &= ~(1 << clk->shift); ti_deny_autoidle()
62 ti_clk_ll_ops->clk_writel(val, clk->reg); ti_deny_autoidle()
107 struct clk_ti_autoidle *clk; of_ti_clk_autoidle_setup() local
113 clk = kzalloc(sizeof(*clk), GFP_KERNEL); of_ti_clk_autoidle_setup()
115 if (!clk) of_ti_clk_autoidle_setup()
118 clk->shift = shift; of_ti_clk_autoidle_setup()
119 clk->name = node->name; of_ti_clk_autoidle_setup()
120 clk->reg = ti_clk_get_reg_addr(node, 0); of_ti_clk_autoidle_setup()
122 if (IS_ERR(clk->reg)) { of_ti_clk_autoidle_setup()
123 kfree(clk); of_ti_clk_autoidle_setup()
128 clk->flags |= AUTOIDLE_LOW; of_ti_clk_autoidle_setup()
130 list_add(&clk->node, &autoidle_clks); of_ti_clk_autoidle_setup()
|
| H A D | clk.c | 18 #include <linux/clk-provider.h>
20 #include <linux/clk/ti.h>
46 struct clk *clk; ti_dt_clocks_register() local
52 clk = of_clk_get_from_provider(&clkspec); ti_dt_clocks_register()
54 if (!IS_ERR(clk)) { ti_dt_clocks_register()
55 c->lk.clk = clk; ti_dt_clocks_register()
124 pr_err("clk-provider not found for %s!\n", node->name); ti_clk_get_reg_addr()
199 struct clk __init *ti_clk_register_clk(struct ti_clk *setup) ti_clk_register_clk()
201 struct clk *clk; ti_clk_register_clk() local
206 if (setup->clk) ti_clk_register_clk()
207 return setup->clk; ti_clk_register_clk()
213 clk = clk_register_fixed_rate(NULL, setup->name, NULL, ti_clk_register_clk()
217 clk = ti_clk_register_mux(setup); ti_clk_register_clk()
220 clk = ti_clk_register_divider(setup); ti_clk_register_clk()
223 clk = ti_clk_register_composite(setup); ti_clk_register_clk()
228 clk = clk_register_fixed_factor(NULL, setup->name, ti_clk_register_clk()
234 clk = ti_clk_register_gate(setup); ti_clk_register_clk()
237 clk = ti_clk_register_dpll(setup); ti_clk_register_clk()
241 clk = ERR_PTR(-EINVAL); ti_clk_register_clk()
244 if (!IS_ERR(clk)) { ti_clk_register_clk()
245 setup->clk = clk; ti_clk_register_clk()
247 if (__clk_get_flags(clk) & CLK_IS_BASIC) { ti_clk_register_clk()
248 pr_warn("can't setup clkdm for basic clk %s\n", ti_clk_register_clk()
251 clk_hw = __clk_get_hw(clk); ti_clk_register_clk()
259 return clk; ti_clk_register_clk()
264 struct clk *clk; ti_clk_register_legacy_clks() local
269 while (clks->clk) { ti_clk_register_legacy_clks()
270 clk = ti_clk_register_clk(clks->clk); ti_clk_register_legacy_clks()
271 if (IS_ERR(clk)) { ti_clk_register_legacy_clks()
272 if (PTR_ERR(clk) == -EAGAIN) { ti_clk_register_legacy_clks()
276 clks->clk->name, PTR_ERR(clk)); ti_clk_register_legacy_clks()
277 return PTR_ERR(clk); ti_clk_register_legacy_clks()
280 clks->lk.clk = clk; ti_clk_register_legacy_clks()
291 pr_debug("retry-init: %s\n", retry_clk->clk->name); ti_clk_register_legacy_clks()
292 clk = ti_clk_register_clk(retry_clk->clk); ti_clk_register_legacy_clks()
293 if (IS_ERR(clk)) { ti_clk_register_legacy_clks()
294 if (PTR_ERR(clk) == -EAGAIN) { ti_clk_register_legacy_clks()
298 retry_clk->clk->name, ti_clk_register_legacy_clks()
299 PTR_ERR(clk)); ti_clk_register_legacy_clks()
300 return PTR_ERR(clk); ti_clk_register_legacy_clks()
304 retry_clk->lk.clk = clk; ti_clk_register_legacy_clks()
|
| H A D | clockdomain.c | 18 #include <linux/clk-provider.h>
22 #include <linux/clk/ti.h>
29 struct clk *clk; of_ti_clockdomain_setup() local
38 clk = of_clk_get(node, i); of_ti_clockdomain_setup()
39 if (IS_ERR(clk)) { of_ti_clockdomain_setup()
41 __func__, node->full_name, i, PTR_ERR(clk)); of_ti_clockdomain_setup()
44 if (__clk_get_flags(clk) & CLK_IS_BASIC) { of_ti_clockdomain_setup()
45 pr_warn("can't setup clkdm for basic clk %s\n", of_ti_clockdomain_setup()
46 __clk_get_name(clk)); of_ti_clockdomain_setup()
49 clk_hw = __clk_get_hw(clk); of_ti_clockdomain_setup()
|
| H A D | apll.c | 18 #include <linux/clk-provider.h>
27 #include <linux/clk/ti.h>
39 struct clk_hw_omap *clk = to_clk_hw_omap(hw); dra7_apll_enable() local
46 ad = clk->dpll_data; dra7_apll_enable()
50 clk_name = __clk_get_name(clk->hw.clk); dra7_apll_enable()
90 struct clk_hw_omap *clk = to_clk_hw_omap(hw); dra7_apll_disable() local
95 ad = clk->dpll_data; dra7_apll_disable()
107 struct clk_hw_omap *clk = to_clk_hw_omap(hw); dra7_apll_is_enabled() local
111 ad = clk->dpll_data; dra7_apll_is_enabled()
138 struct clk *clk; omap_clk_register_apll() local
144 pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", omap_clk_register_apll()
152 clk = clk_register(NULL, &clk_hw->hw); omap_clk_register_apll()
153 if (!IS_ERR(clk)) { omap_clk_register_apll()
154 of_clk_add_provider(node, of_clk_src_simple_get, clk); omap_clk_register_apll()
228 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_is_enabled() local
229 struct dpll_data *ad = clk->dpll_data; omap2_apll_is_enabled()
243 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_recalc() local
246 return clk->fixed_rate; omap2_apll_recalc()
253 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_enable() local
254 struct dpll_data *ad = clk->dpll_data; omap2_apll_enable()
275 __clk_get_name(clk->hw.clk)); omap2_apll_enable()
284 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_disable() local
285 struct dpll_data *ad = clk->dpll_data; omap2_apll_disable()
301 static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val) omap2_apll_set_autoidle() argument
303 struct dpll_data *ad = clk->dpll_data; omap2_apll_set_autoidle()
315 static void omap2_apll_allow_idle(struct clk_hw_omap *clk) omap2_apll_allow_idle() argument
317 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP); omap2_apll_allow_idle()
320 static void omap2_apll_deny_idle(struct clk_hw_omap *clk) omap2_apll_deny_idle() argument
322 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE); omap2_apll_deny_idle()
335 struct clk *clk; of_omap2_apll_setup() local
391 clk = clk_register(NULL, &clk_hw->hw); of_omap2_apll_setup()
392 if (!IS_ERR(clk)) { of_omap2_apll_setup()
393 of_clk_add_provider(node, of_clk_src_simple_get, clk); of_omap2_apll_setup()
|
| /linux-4.1.27/drivers/clk/x86/ |
| H A D | Makefile | 0 clk-x86-lpss-objs := clk-lpt.o
2 obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
|
| H A D | clk-lpt.c | 13 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
18 #include <linux/platform_data/clk-lpss.h>
24 struct clk *clk; lpt_clk_probe() local
32 clk = clk_register_fixed_rate(&pdev->dev, drvdata->name, NULL, lpt_clk_probe()
34 if (IS_ERR(clk)) lpt_clk_probe()
35 return PTR_ERR(clk); lpt_clk_probe()
37 drvdata->clk = clk; lpt_clk_probe()
44 .name = "clk-lpt",
|
| /linux-4.1.27/drivers/clk/ux500/ |
| H A D | u8540_clk.c | 10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-ux500.h>
15 #include "clk.h"
20 struct clk *clk; u8540_clk_init() local
24 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, u8540_clk_init()
26 clk_register_clkdev(clk, "soc0_pll", NULL); u8540_clk_init()
28 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, u8540_clk_init()
30 clk_register_clkdev(clk, "soc1_pll", NULL); u8540_clk_init()
32 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8540_clk_init()
34 clk_register_clkdev(clk, "ddr_pll", NULL); u8540_clk_init()
36 clk = clk_register_fixed_rate(NULL, "rtc32k", NULL, u8540_clk_init()
39 clk_register_clkdev(clk, "clk32k", NULL); u8540_clk_init()
40 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); u8540_clk_init()
42 clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL, u8540_clk_init()
46 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); u8540_clk_init()
47 clk_register_clkdev(clk, NULL, "UART"); u8540_clk_init()
49 /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */ u8540_clk_init()
50 clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1", u8540_clk_init()
52 clk_register_clkdev(clk, NULL, "MSP02"); u8540_clk_init()
54 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); u8540_clk_init()
55 clk_register_clkdev(clk, NULL, "MSP1"); u8540_clk_init()
57 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); u8540_clk_init()
58 clk_register_clkdev(clk, NULL, "I2C"); u8540_clk_init()
60 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); u8540_clk_init()
61 clk_register_clkdev(clk, NULL, "slim"); u8540_clk_init()
63 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); u8540_clk_init()
64 clk_register_clkdev(clk, NULL, "PERIPH1"); u8540_clk_init()
66 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); u8540_clk_init()
67 clk_register_clkdev(clk, NULL, "PERIPH2"); u8540_clk_init()
69 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); u8540_clk_init()
70 clk_register_clkdev(clk, NULL, "PERIPH3"); u8540_clk_init()
72 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); u8540_clk_init()
73 clk_register_clkdev(clk, NULL, "PERIPH5"); u8540_clk_init()
75 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); u8540_clk_init()
76 clk_register_clkdev(clk, NULL, "PERIPH6"); u8540_clk_init()
78 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); u8540_clk_init()
79 clk_register_clkdev(clk, NULL, "PERIPH7"); u8540_clk_init()
81 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, u8540_clk_init()
83 clk_register_clkdev(clk, NULL, "lcd"); u8540_clk_init()
84 clk_register_clkdev(clk, "lcd", "mcde"); u8540_clk_init()
86 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, u8540_clk_init()
88 clk_register_clkdev(clk, NULL, "bml"); u8540_clk_init()
90 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, u8540_clk_init()
93 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, u8540_clk_init()
96 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, u8540_clk_init()
98 clk_register_clkdev(clk, NULL, "hdmi"); u8540_clk_init()
99 clk_register_clkdev(clk, "hdmi", "mcde"); u8540_clk_init()
101 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); u8540_clk_init()
102 clk_register_clkdev(clk, NULL, "apeat"); u8540_clk_init()
104 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, u8540_clk_init()
106 clk_register_clkdev(clk, NULL, "apetrace"); u8540_clk_init()
108 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); u8540_clk_init()
109 clk_register_clkdev(clk, NULL, "mcde"); u8540_clk_init()
110 clk_register_clkdev(clk, "mcde", "mcde"); u8540_clk_init()
111 clk_register_clkdev(clk, NULL, "dsilink.0"); u8540_clk_init()
112 clk_register_clkdev(clk, NULL, "dsilink.1"); u8540_clk_init()
113 clk_register_clkdev(clk, NULL, "dsilink.2"); u8540_clk_init()
115 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, u8540_clk_init()
117 clk_register_clkdev(clk, NULL, "ipi2"); u8540_clk_init()
119 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, u8540_clk_init()
121 clk_register_clkdev(clk, NULL, "dsialt"); u8540_clk_init()
123 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); u8540_clk_init()
124 clk_register_clkdev(clk, NULL, "dma40.0"); u8540_clk_init()
126 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); u8540_clk_init()
127 clk_register_clkdev(clk, NULL, "b2r2"); u8540_clk_init()
128 clk_register_clkdev(clk, NULL, "b2r2_core"); u8540_clk_init()
129 clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); u8540_clk_init()
130 clk_register_clkdev(clk, NULL, "b2r2_1_core"); u8540_clk_init()
132 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, u8540_clk_init()
134 clk_register_clkdev(clk, NULL, "tv"); u8540_clk_init()
135 clk_register_clkdev(clk, "tv", "mcde"); u8540_clk_init()
137 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); u8540_clk_init()
138 clk_register_clkdev(clk, NULL, "SSP"); u8540_clk_init()
140 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); u8540_clk_init()
141 clk_register_clkdev(clk, NULL, "rngclk"); u8540_clk_init()
143 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); u8540_clk_init()
144 clk_register_clkdev(clk, NULL, "uicc"); u8540_clk_init()
146 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); u8540_clk_init()
147 clk_register_clkdev(clk, NULL, "mtu0"); u8540_clk_init()
148 clk_register_clkdev(clk, NULL, "mtu1"); u8540_clk_init()
150 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, u8540_clk_init()
153 clk_register_clkdev(clk, NULL, "sdmmc"); u8540_clk_init()
155 clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL, u8540_clk_init()
158 clk_register_clkdev(clk, NULL, "sdmmchclk"); u8540_clk_init()
160 clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT); u8540_clk_init()
161 clk_register_clkdev(clk, NULL, "hva"); u8540_clk_init()
163 clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT); u8540_clk_init()
164 clk_register_clkdev(clk, NULL, "g1"); u8540_clk_init()
166 clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0, u8540_clk_init()
168 clk_register_clkdev(clk, "dsilcd", "mcde"); u8540_clk_init()
170 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", u8540_clk_init()
172 clk_register_clkdev(clk, "dsihs2", "mcde"); u8540_clk_init()
173 clk_register_clkdev(clk, "hs_clk", "dsilink.2"); u8540_clk_init()
175 clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk", u8540_clk_init()
177 clk_register_clkdev(clk, "dsilcd_pll", "mcde"); u8540_clk_init()
179 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", u8540_clk_init()
181 clk_register_clkdev(clk, "dsihs0", "mcde"); u8540_clk_init()
183 clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll", u8540_clk_init()
185 clk_register_clkdev(clk, "dsihs0", "mcde"); u8540_clk_init()
186 clk_register_clkdev(clk, "hs_clk", "dsilink.0"); u8540_clk_init()
188 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", u8540_clk_init()
190 clk_register_clkdev(clk, "dsihs1", "mcde"); u8540_clk_init()
192 clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll", u8540_clk_init()
194 clk_register_clkdev(clk, "dsihs1", "mcde"); u8540_clk_init()
195 clk_register_clkdev(clk, "hs_clk", "dsilink.1"); u8540_clk_init()
197 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", u8540_clk_init()
199 clk_register_clkdev(clk, "lp_clk", "dsilink.0"); u8540_clk_init()
200 clk_register_clkdev(clk, "dsilp0", "mcde"); u8540_clk_init()
202 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", u8540_clk_init()
204 clk_register_clkdev(clk, "lp_clk", "dsilink.1"); u8540_clk_init()
205 clk_register_clkdev(clk, "dsilp1", "mcde"); u8540_clk_init()
207 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", u8540_clk_init()
209 clk_register_clkdev(clk, "lp_clk", "dsilink.2"); u8540_clk_init()
210 clk_register_clkdev(clk, "dsilp2", "mcde"); u8540_clk_init()
212 clk = clk_reg_prcmu_scalable_rate("armss", NULL, u8540_clk_init()
214 clk_register_clkdev(clk, "armss", NULL); u8540_clk_init()
216 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", u8540_clk_init()
218 clk_register_clkdev(clk, NULL, "smp_twd"); u8540_clk_init()
222 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, u8540_clk_init()
224 clk_register_clkdev(clk, "apb_pclk", "uart0"); u8540_clk_init()
226 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, u8540_clk_init()
228 clk_register_clkdev(clk, "apb_pclk", "uart1"); u8540_clk_init()
230 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, u8540_clk_init()
232 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); u8540_clk_init()
234 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, u8540_clk_init()
236 clk_register_clkdev(clk, "apb_pclk", "msp0"); u8540_clk_init()
237 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0"); u8540_clk_init()
239 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, u8540_clk_init()
241 clk_register_clkdev(clk, "apb_pclk", "msp1"); u8540_clk_init()
242 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1"); u8540_clk_init()
244 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, u8540_clk_init()
246 clk_register_clkdev(clk, "apb_pclk", "sdi0"); u8540_clk_init()
248 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, u8540_clk_init()
250 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); u8540_clk_init()
252 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, u8540_clk_init()
254 clk_register_clkdev(clk, NULL, "spi3"); u8540_clk_init()
256 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, u8540_clk_init()
258 clk_register_clkdev(clk, "apb_pclk", "slimbus0"); u8540_clk_init()
260 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, u8540_clk_init()
262 clk_register_clkdev(clk, NULL, "gpio.0"); u8540_clk_init()
263 clk_register_clkdev(clk, NULL, "gpio.1"); u8540_clk_init()
264 clk_register_clkdev(clk, NULL, "gpioblock0"); u8540_clk_init()
265 clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0"); u8540_clk_init()
267 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, u8540_clk_init()
269 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); u8540_clk_init()
271 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, u8540_clk_init()
273 clk_register_clkdev(clk, "apb_pclk", "msp3"); u8540_clk_init()
274 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3"); u8540_clk_init()
277 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, u8540_clk_init()
279 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); u8540_clk_init()
281 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, u8540_clk_init()
283 clk_register_clkdev(clk, NULL, "spi2"); u8540_clk_init()
285 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, u8540_clk_init()
287 clk_register_clkdev(clk, NULL, "spi1"); u8540_clk_init()
289 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, u8540_clk_init()
291 clk_register_clkdev(clk, NULL, "pwl"); u8540_clk_init()
293 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, u8540_clk_init()
295 clk_register_clkdev(clk, "apb_pclk", "sdi4"); u8540_clk_init()
297 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, u8540_clk_init()
299 clk_register_clkdev(clk, "apb_pclk", "msp2"); u8540_clk_init()
300 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2"); u8540_clk_init()
302 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, u8540_clk_init()
304 clk_register_clkdev(clk, "apb_pclk", "sdi1"); u8540_clk_init()
306 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, u8540_clk_init()
308 clk_register_clkdev(clk, "apb_pclk", "sdi3"); u8540_clk_init()
310 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, u8540_clk_init()
312 clk_register_clkdev(clk, NULL, "spi0"); u8540_clk_init()
314 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, u8540_clk_init()
316 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); u8540_clk_init()
318 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, u8540_clk_init()
320 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); u8540_clk_init()
322 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, u8540_clk_init()
324 clk_register_clkdev(clk, NULL, "gpio.6"); u8540_clk_init()
325 clk_register_clkdev(clk, NULL, "gpio.7"); u8540_clk_init()
326 clk_register_clkdev(clk, NULL, "gpioblock1"); u8540_clk_init()
328 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, u8540_clk_init()
330 clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0"); u8540_clk_init()
333 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, u8540_clk_init()
335 clk_register_clkdev(clk, NULL, "fsmc"); u8540_clk_init()
337 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, u8540_clk_init()
339 clk_register_clkdev(clk, "apb_pclk", "ssp0"); u8540_clk_init()
341 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, u8540_clk_init()
343 clk_register_clkdev(clk, "apb_pclk", "ssp1"); u8540_clk_init()
345 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, u8540_clk_init()
347 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); u8540_clk_init()
349 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, u8540_clk_init()
351 clk_register_clkdev(clk, "apb_pclk", "sdi2"); u8540_clk_init()
353 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, u8540_clk_init()
355 clk_register_clkdev(clk, "apb_pclk", "ske"); u8540_clk_init()
356 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); u8540_clk_init()
358 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, u8540_clk_init()
360 clk_register_clkdev(clk, "apb_pclk", "uart2"); u8540_clk_init()
362 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, u8540_clk_init()
364 clk_register_clkdev(clk, "apb_pclk", "sdi5"); u8540_clk_init()
366 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, u8540_clk_init()
368 clk_register_clkdev(clk, NULL, "gpio.2"); u8540_clk_init()
369 clk_register_clkdev(clk, NULL, "gpio.3"); u8540_clk_init()
370 clk_register_clkdev(clk, NULL, "gpio.4"); u8540_clk_init()
371 clk_register_clkdev(clk, NULL, "gpio.5"); u8540_clk_init()
372 clk_register_clkdev(clk, NULL, "gpioblock2"); u8540_clk_init()
374 clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", clkrst3_base, u8540_clk_init()
376 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5"); u8540_clk_init()
378 clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", clkrst3_base, u8540_clk_init()
380 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6"); u8540_clk_init()
382 clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", clkrst3_base, u8540_clk_init()
384 clk_register_clkdev(clk, "apb_pclk", "uart3"); u8540_clk_init()
386 clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", clkrst3_base, u8540_clk_init()
388 clk_register_clkdev(clk, "apb_pclk", "uart4"); u8540_clk_init()
391 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, u8540_clk_init()
393 clk_register_clkdev(clk, "usb", "musb-ux500.0"); u8540_clk_init()
394 clk_register_clkdev(clk, "usbclk", "ab-iddet.0"); u8540_clk_init()
396 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, u8540_clk_init()
398 clk_register_clkdev(clk, NULL, "gpio.8"); u8540_clk_init()
399 clk_register_clkdev(clk, NULL, "gpioblock3"); u8540_clk_init()
402 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, u8540_clk_init()
404 clk_register_clkdev(clk, "apb_pclk", "rng"); u8540_clk_init()
406 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, u8540_clk_init()
408 clk_register_clkdev(clk, NULL, "cryp0"); u8540_clk_init()
409 clk_register_clkdev(clk, NULL, "cryp1"); u8540_clk_init()
411 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, u8540_clk_init()
413 clk_register_clkdev(clk, NULL, "hash0"); u8540_clk_init()
415 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, u8540_clk_init()
417 clk_register_clkdev(clk, NULL, "pka"); u8540_clk_init()
419 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, u8540_clk_init()
421 clk_register_clkdev(clk, NULL, "db8540-hash1"); u8540_clk_init()
423 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, u8540_clk_init()
425 clk_register_clkdev(clk, NULL, "cfgreg"); u8540_clk_init()
427 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, u8540_clk_init()
429 clk_register_clkdev(clk, "apb_pclk", "mtu0"); u8540_clk_init()
431 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, u8540_clk_init()
433 clk_register_clkdev(clk, "apb_pclk", "mtu1"); u8540_clk_init()
444 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", u8540_clk_init()
446 clk_register_clkdev(clk, NULL, "uart0"); u8540_clk_init()
448 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", u8540_clk_init()
450 clk_register_clkdev(clk, NULL, "uart1"); u8540_clk_init()
452 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", u8540_clk_init()
454 clk_register_clkdev(clk, NULL, "nmk-i2c.1"); u8540_clk_init()
456 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", u8540_clk_init()
458 clk_register_clkdev(clk, NULL, "msp0"); u8540_clk_init()
459 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0"); u8540_clk_init()
461 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", u8540_clk_init()
463 clk_register_clkdev(clk, NULL, "msp1"); u8540_clk_init()
464 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1"); u8540_clk_init()
466 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk", u8540_clk_init()
468 clk_register_clkdev(clk, NULL, "sdi0"); u8540_clk_init()
470 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", u8540_clk_init()
472 clk_register_clkdev(clk, NULL, "nmk-i2c.2"); u8540_clk_init()
474 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", u8540_clk_init()
476 clk_register_clkdev(clk, NULL, "slimbus0"); u8540_clk_init()
478 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", u8540_clk_init()
480 clk_register_clkdev(clk, NULL, "nmk-i2c.4"); u8540_clk_init()
482 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", u8540_clk_init()
484 clk_register_clkdev(clk, NULL, "msp3"); u8540_clk_init()
485 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3"); u8540_clk_init()
488 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", u8540_clk_init()
490 clk_register_clkdev(clk, NULL, "nmk-i2c.3"); u8540_clk_init()
492 clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k", u8540_clk_init()
494 clk_register_clkdev(clk, NULL, "pwl"); u8540_clk_init()
496 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk", u8540_clk_init()
498 clk_register_clkdev(clk, NULL, "sdi4"); u8540_clk_init()
500 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", u8540_clk_init()
502 clk_register_clkdev(clk, NULL, "msp2"); u8540_clk_init()
503 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2"); u8540_clk_init()
505 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk", u8540_clk_init()
507 clk_register_clkdev(clk, NULL, "sdi1"); u8540_clk_init()
509 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", u8540_clk_init()
511 clk_register_clkdev(clk, NULL, "sdi3"); u8540_clk_init()
513 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", u8540_clk_init()
516 clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0"); u8540_clk_init()
518 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", u8540_clk_init()
521 clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0"); u8540_clk_init()
524 clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk", u8540_clk_init()
526 clk_register_clkdev(clk, NULL, "msp4"); u8540_clk_init()
527 clk_register_clkdev(clk, "msp4", "ab85xx-codec.0"); u8540_clk_init()
530 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", u8540_clk_init()
532 clk_register_clkdev(clk, NULL, "ssp0"); u8540_clk_init()
534 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", u8540_clk_init()
536 clk_register_clkdev(clk, NULL, "ssp1"); u8540_clk_init()
538 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", u8540_clk_init()
540 clk_register_clkdev(clk, NULL, "nmk-i2c.0"); u8540_clk_init()
542 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk", u8540_clk_init()
544 clk_register_clkdev(clk, NULL, "sdi2"); u8540_clk_init()
546 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", u8540_clk_init()
548 clk_register_clkdev(clk, NULL, "ske"); u8540_clk_init()
549 clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); u8540_clk_init()
551 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", u8540_clk_init()
553 clk_register_clkdev(clk, NULL, "uart2"); u8540_clk_init()
555 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", u8540_clk_init()
557 clk_register_clkdev(clk, NULL, "sdi5"); u8540_clk_init()
559 clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk", u8540_clk_init()
561 clk_register_clkdev(clk, NULL, "nmk-i2c.5"); u8540_clk_init()
563 clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk", u8540_clk_init()
565 clk_register_clkdev(clk, NULL, "nmk-i2c.6"); u8540_clk_init()
567 clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk", u8540_clk_init()
569 clk_register_clkdev(clk, NULL, "uart3"); u8540_clk_init()
571 clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk", u8540_clk_init()
573 clk_register_clkdev(clk, NULL, "uart4"); u8540_clk_init()
576 clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk", u8540_clk_init()
578 clk_register_clkdev(clk, NULL, "rng"); u8540_clk_init()
|
| H A D | u8500_clk.c | 10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-ux500.h>
15 #include "clk.h"
22 struct clk *clk; u8500_clk_init() local
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, u8500_clk_init()
27 clk_register_clkdev(clk, "soc0_pll", NULL); u8500_clk_init()
29 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, u8500_clk_init()
31 clk_register_clkdev(clk, "soc1_pll", NULL); u8500_clk_init()
33 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8500_clk_init()
35 clk_register_clkdev(clk, "ddr_pll", NULL); u8500_clk_init()
39 clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", u8500_clk_init()
42 clk_register_clkdev(clk, "clk32k", NULL); u8500_clk_init()
43 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); u8500_clk_init()
60 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, u8500_clk_init()
63 clk = clk_reg_prcmu_gate("sgclk", NULL, u8500_clk_init()
65 clk_register_clkdev(clk, NULL, "mali"); u8500_clk_init()
67 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); u8500_clk_init()
68 clk_register_clkdev(clk, NULL, "UART"); u8500_clk_init()
70 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); u8500_clk_init()
71 clk_register_clkdev(clk, NULL, "MSP02"); u8500_clk_init()
73 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); u8500_clk_init()
74 clk_register_clkdev(clk, NULL, "MSP1"); u8500_clk_init()
76 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); u8500_clk_init()
77 clk_register_clkdev(clk, NULL, "I2C"); u8500_clk_init()
79 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); u8500_clk_init()
80 clk_register_clkdev(clk, NULL, "slim"); u8500_clk_init()
82 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); u8500_clk_init()
83 clk_register_clkdev(clk, NULL, "PERIPH1"); u8500_clk_init()
85 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); u8500_clk_init()
86 clk_register_clkdev(clk, NULL, "PERIPH2"); u8500_clk_init()
88 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); u8500_clk_init()
89 clk_register_clkdev(clk, NULL, "PERIPH3"); u8500_clk_init()
91 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); u8500_clk_init()
92 clk_register_clkdev(clk, NULL, "PERIPH5"); u8500_clk_init()
94 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); u8500_clk_init()
95 clk_register_clkdev(clk, NULL, "PERIPH6"); u8500_clk_init()
97 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); u8500_clk_init()
98 clk_register_clkdev(clk, NULL, "PERIPH7"); u8500_clk_init()
100 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, u8500_clk_init()
102 clk_register_clkdev(clk, NULL, "lcd"); u8500_clk_init()
103 clk_register_clkdev(clk, "lcd", "mcde"); u8500_clk_init()
105 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); u8500_clk_init()
106 clk_register_clkdev(clk, NULL, "bml"); u8500_clk_init()
108 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, u8500_clk_init()
111 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, u8500_clk_init()
114 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, u8500_clk_init()
116 clk_register_clkdev(clk, NULL, "hdmi"); u8500_clk_init()
117 clk_register_clkdev(clk, "hdmi", "mcde"); u8500_clk_init()
119 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); u8500_clk_init()
120 clk_register_clkdev(clk, NULL, "apeat"); u8500_clk_init()
122 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, u8500_clk_init()
124 clk_register_clkdev(clk, NULL, "apetrace"); u8500_clk_init()
126 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); u8500_clk_init()
127 clk_register_clkdev(clk, NULL, "mcde"); u8500_clk_init()
128 clk_register_clkdev(clk, "mcde", "mcde"); u8500_clk_init()
129 clk_register_clkdev(clk, "dsisys", "dsilink.0"); u8500_clk_init()
130 clk_register_clkdev(clk, "dsisys", "dsilink.1"); u8500_clk_init()
131 clk_register_clkdev(clk, "dsisys", "dsilink.2"); u8500_clk_init()
133 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, u8500_clk_init()
135 clk_register_clkdev(clk, NULL, "ipi2"); u8500_clk_init()
137 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, u8500_clk_init()
139 clk_register_clkdev(clk, NULL, "dsialt"); u8500_clk_init()
141 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); u8500_clk_init()
142 clk_register_clkdev(clk, NULL, "dma40.0"); u8500_clk_init()
144 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); u8500_clk_init()
145 clk_register_clkdev(clk, NULL, "b2r2"); u8500_clk_init()
146 clk_register_clkdev(clk, NULL, "b2r2_core"); u8500_clk_init()
147 clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); u8500_clk_init()
149 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, u8500_clk_init()
151 clk_register_clkdev(clk, NULL, "tv"); u8500_clk_init()
152 clk_register_clkdev(clk, "tv", "mcde"); u8500_clk_init()
154 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); u8500_clk_init()
155 clk_register_clkdev(clk, NULL, "SSP"); u8500_clk_init()
157 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); u8500_clk_init()
158 clk_register_clkdev(clk, NULL, "rngclk"); u8500_clk_init()
160 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); u8500_clk_init()
161 clk_register_clkdev(clk, NULL, "uicc"); u8500_clk_init()
163 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); u8500_clk_init()
164 clk_register_clkdev(clk, NULL, "mtu0"); u8500_clk_init()
165 clk_register_clkdev(clk, NULL, "mtu1"); u8500_clk_init()
167 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, u8500_clk_init()
170 clk_register_clkdev(clk, NULL, "sdmmc"); u8500_clk_init()
172 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", u8500_clk_init()
174 clk_register_clkdev(clk, "dsihs2", "mcde"); u8500_clk_init()
175 clk_register_clkdev(clk, "dsihs2", "dsilink.2"); u8500_clk_init()
178 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", u8500_clk_init()
180 clk_register_clkdev(clk, "dsihs0", "mcde"); u8500_clk_init()
181 clk_register_clkdev(clk, "dsihs0", "dsilink.0"); u8500_clk_init()
183 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", u8500_clk_init()
185 clk_register_clkdev(clk, "dsihs1", "mcde"); u8500_clk_init()
186 clk_register_clkdev(clk, "dsihs1", "dsilink.1"); u8500_clk_init()
188 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", u8500_clk_init()
190 clk_register_clkdev(clk, "dsilp0", "dsilink.0"); u8500_clk_init()
191 clk_register_clkdev(clk, "dsilp0", "mcde"); u8500_clk_init()
193 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", u8500_clk_init()
195 clk_register_clkdev(clk, "dsilp1", "dsilink.1"); u8500_clk_init()
196 clk_register_clkdev(clk, "dsilp1", "mcde"); u8500_clk_init()
198 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", u8500_clk_init()
200 clk_register_clkdev(clk, "dsilp2", "dsilink.2"); u8500_clk_init()
201 clk_register_clkdev(clk, "dsilp2", "mcde"); u8500_clk_init()
203 clk = clk_reg_prcmu_scalable_rate("armss", NULL, u8500_clk_init()
205 clk_register_clkdev(clk, "armss", NULL); u8500_clk_init()
207 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", u8500_clk_init()
209 clk_register_clkdev(clk, NULL, "smp_twd"); u8500_clk_init()
218 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, u8500_clk_init()
220 clk_register_clkdev(clk, "apb_pclk", "uart0"); u8500_clk_init()
222 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, u8500_clk_init()
224 clk_register_clkdev(clk, "apb_pclk", "uart1"); u8500_clk_init()
226 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, u8500_clk_init()
228 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); u8500_clk_init()
230 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, u8500_clk_init()
232 clk_register_clkdev(clk, "apb_pclk", "msp0"); u8500_clk_init()
233 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0"); u8500_clk_init()
235 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, u8500_clk_init()
237 clk_register_clkdev(clk, "apb_pclk", "msp1"); u8500_clk_init()
238 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1"); u8500_clk_init()
240 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, u8500_clk_init()
242 clk_register_clkdev(clk, "apb_pclk", "sdi0"); u8500_clk_init()
244 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, u8500_clk_init()
246 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); u8500_clk_init()
248 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, u8500_clk_init()
250 clk_register_clkdev(clk, NULL, "spi3"); u8500_clk_init()
252 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, u8500_clk_init()
254 clk_register_clkdev(clk, "apb_pclk", "slimbus0"); u8500_clk_init()
256 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, u8500_clk_init()
258 clk_register_clkdev(clk, NULL, "gpio.0"); u8500_clk_init()
259 clk_register_clkdev(clk, NULL, "gpio.1"); u8500_clk_init()
260 clk_register_clkdev(clk, NULL, "gpioblock0"); u8500_clk_init()
262 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, u8500_clk_init()
264 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); u8500_clk_init()
266 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, u8500_clk_init()
268 clk_register_clkdev(clk, "apb_pclk", "msp3"); u8500_clk_init()
269 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3"); u8500_clk_init()
271 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, u8500_clk_init()
273 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); u8500_clk_init()
275 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, u8500_clk_init()
277 clk_register_clkdev(clk, NULL, "spi2"); u8500_clk_init()
279 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, u8500_clk_init()
281 clk_register_clkdev(clk, NULL, "spi1"); u8500_clk_init()
283 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, u8500_clk_init()
285 clk_register_clkdev(clk, NULL, "pwl"); u8500_clk_init()
287 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, u8500_clk_init()
289 clk_register_clkdev(clk, "apb_pclk", "sdi4"); u8500_clk_init()
291 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, u8500_clk_init()
293 clk_register_clkdev(clk, "apb_pclk", "msp2"); u8500_clk_init()
294 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2"); u8500_clk_init()
296 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, u8500_clk_init()
298 clk_register_clkdev(clk, "apb_pclk", "sdi1"); u8500_clk_init()
300 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, u8500_clk_init()
302 clk_register_clkdev(clk, "apb_pclk", "sdi3"); u8500_clk_init()
304 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, u8500_clk_init()
306 clk_register_clkdev(clk, NULL, "spi0"); u8500_clk_init()
308 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, u8500_clk_init()
310 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); u8500_clk_init()
312 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, u8500_clk_init()
314 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); u8500_clk_init()
316 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, u8500_clk_init()
318 clk_register_clkdev(clk, NULL, "gpio.6"); u8500_clk_init()
319 clk_register_clkdev(clk, NULL, "gpio.7"); u8500_clk_init()
320 clk_register_clkdev(clk, NULL, "gpioblock1"); u8500_clk_init()
322 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, u8500_clk_init()
325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, u8500_clk_init()
327 clk_register_clkdev(clk, "fsmc", NULL); u8500_clk_init()
328 clk_register_clkdev(clk, NULL, "smsc911x.0"); u8500_clk_init()
330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, u8500_clk_init()
332 clk_register_clkdev(clk, "apb_pclk", "ssp0"); u8500_clk_init()
334 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, u8500_clk_init()
336 clk_register_clkdev(clk, "apb_pclk", "ssp1"); u8500_clk_init()
338 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, u8500_clk_init()
340 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); u8500_clk_init()
342 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, u8500_clk_init()
344 clk_register_clkdev(clk, "apb_pclk", "sdi2"); u8500_clk_init()
346 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, u8500_clk_init()
348 clk_register_clkdev(clk, "apb_pclk", "ske"); u8500_clk_init()
349 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); u8500_clk_init()
351 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, u8500_clk_init()
353 clk_register_clkdev(clk, "apb_pclk", "uart2"); u8500_clk_init()
355 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, u8500_clk_init()
357 clk_register_clkdev(clk, "apb_pclk", "sdi5"); u8500_clk_init()
359 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, u8500_clk_init()
361 clk_register_clkdev(clk, NULL, "gpio.2"); u8500_clk_init()
362 clk_register_clkdev(clk, NULL, "gpio.3"); u8500_clk_init()
363 clk_register_clkdev(clk, NULL, "gpio.4"); u8500_clk_init()
364 clk_register_clkdev(clk, NULL, "gpio.5"); u8500_clk_init()
365 clk_register_clkdev(clk, NULL, "gpioblock2"); u8500_clk_init()
367 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, u8500_clk_init()
369 clk_register_clkdev(clk, "usb", "musb-ux500.0"); u8500_clk_init()
371 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, u8500_clk_init()
373 clk_register_clkdev(clk, NULL, "gpio.8"); u8500_clk_init()
374 clk_register_clkdev(clk, NULL, "gpioblock3"); u8500_clk_init()
376 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, u8500_clk_init()
378 clk_register_clkdev(clk, "apb_pclk", "rng"); u8500_clk_init()
380 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, u8500_clk_init()
382 clk_register_clkdev(clk, NULL, "cryp0"); u8500_clk_init()
383 clk_register_clkdev(clk, NULL, "cryp1"); u8500_clk_init()
385 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, u8500_clk_init()
387 clk_register_clkdev(clk, NULL, "hash0"); u8500_clk_init()
389 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, u8500_clk_init()
391 clk_register_clkdev(clk, NULL, "pka"); u8500_clk_init()
393 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, u8500_clk_init()
395 clk_register_clkdev(clk, NULL, "hash1"); u8500_clk_init()
397 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, u8500_clk_init()
399 clk_register_clkdev(clk, NULL, "cfgreg"); u8500_clk_init()
401 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, u8500_clk_init()
403 clk_register_clkdev(clk, "apb_pclk", "mtu0"); u8500_clk_init()
405 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, u8500_clk_init()
407 clk_register_clkdev(clk, "apb_pclk", "mtu1"); u8500_clk_init()
418 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", u8500_clk_init()
420 clk_register_clkdev(clk, NULL, "uart0"); u8500_clk_init()
422 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", u8500_clk_init()
424 clk_register_clkdev(clk, NULL, "uart1"); u8500_clk_init()
426 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", u8500_clk_init()
428 clk_register_clkdev(clk, NULL, "nmk-i2c.1"); u8500_clk_init()
430 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", u8500_clk_init()
432 clk_register_clkdev(clk, NULL, "msp0"); u8500_clk_init()
433 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0"); u8500_clk_init()
435 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", u8500_clk_init()
437 clk_register_clkdev(clk, NULL, "msp1"); u8500_clk_init()
438 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1"); u8500_clk_init()
440 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", u8500_clk_init()
442 clk_register_clkdev(clk, NULL, "sdi0"); u8500_clk_init()
444 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", u8500_clk_init()
446 clk_register_clkdev(clk, NULL, "nmk-i2c.2"); u8500_clk_init()
448 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", u8500_clk_init()
450 clk_register_clkdev(clk, NULL, "slimbus0"); u8500_clk_init()
452 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", u8500_clk_init()
454 clk_register_clkdev(clk, NULL, "nmk-i2c.4"); u8500_clk_init()
456 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", u8500_clk_init()
458 clk_register_clkdev(clk, NULL, "msp3"); u8500_clk_init()
459 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3"); u8500_clk_init()
462 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", u8500_clk_init()
464 clk_register_clkdev(clk, NULL, "nmk-i2c.3"); u8500_clk_init()
466 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", u8500_clk_init()
468 clk_register_clkdev(clk, NULL, "sdi4"); u8500_clk_init()
470 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", u8500_clk_init()
472 clk_register_clkdev(clk, NULL, "msp2"); u8500_clk_init()
473 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2"); u8500_clk_init()
475 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", u8500_clk_init()
477 clk_register_clkdev(clk, NULL, "sdi1"); u8500_clk_init()
479 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", u8500_clk_init()
481 clk_register_clkdev(clk, NULL, "sdi3"); u8500_clk_init()
484 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", u8500_clk_init()
487 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", u8500_clk_init()
492 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", u8500_clk_init()
494 clk_register_clkdev(clk, NULL, "ssp0"); u8500_clk_init()
496 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", u8500_clk_init()
498 clk_register_clkdev(clk, NULL, "ssp1"); u8500_clk_init()
500 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", u8500_clk_init()
502 clk_register_clkdev(clk, NULL, "nmk-i2c.0"); u8500_clk_init()
504 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", u8500_clk_init()
506 clk_register_clkdev(clk, NULL, "sdi2"); u8500_clk_init()
508 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", u8500_clk_init()
510 clk_register_clkdev(clk, NULL, "ske"); u8500_clk_init()
511 clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); u8500_clk_init()
513 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", u8500_clk_init()
515 clk_register_clkdev(clk, NULL, "uart2"); u8500_clk_init()
517 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", u8500_clk_init()
519 clk_register_clkdev(clk, NULL, "sdi5"); u8500_clk_init()
522 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", u8500_clk_init()
524 clk_register_clkdev(clk, NULL, "rng"); u8500_clk_init()
|
| H A D | u8500_of_clk.c | 11 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
15 #include <linux/platform_data/clk-ux500.h>
16 #include "clk.h"
21 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
22 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
23 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
25 #define PRCC_SHOW(clk, base, bit) \
26 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
27 #define PRCC_PCLK_STORE(clk, base, bit) \
28 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29 #define PRCC_KCLK_STORE(clk, base, bit) \
30 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
32 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, ux500_twocell_get()
35 struct clk **clk_data = data; ux500_twocell_get()
64 struct clk *clk, *rtc_clk, *twd_clk; u8500_of_clk_init() local
74 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, u8500_of_clk_init()
76 prcmu_clk[PRCMU_PLLSOC0] = clk; u8500_of_clk_init()
78 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, u8500_of_clk_init()
80 prcmu_clk[PRCMU_PLLSOC1] = clk; u8500_of_clk_init()
82 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8500_of_clk_init()
84 prcmu_clk[PRCMU_PLLDDR] = clk; u8500_of_clk_init()
107 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, u8500_of_clk_init()
110 clk = clk_reg_prcmu_gate("sgclk", NULL, u8500_of_clk_init()
112 prcmu_clk[PRCMU_SGACLK] = clk; u8500_of_clk_init()
114 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); u8500_of_clk_init()
115 prcmu_clk[PRCMU_UARTCLK] = clk; u8500_of_clk_init()
117 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); u8500_of_clk_init()
118 prcmu_clk[PRCMU_MSP02CLK] = clk; u8500_of_clk_init()
120 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); u8500_of_clk_init()
121 prcmu_clk[PRCMU_MSP1CLK] = clk; u8500_of_clk_init()
123 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); u8500_of_clk_init()
124 prcmu_clk[PRCMU_I2CCLK] = clk; u8500_of_clk_init()
126 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); u8500_of_clk_init()
127 prcmu_clk[PRCMU_SLIMCLK] = clk; u8500_of_clk_init()
129 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); u8500_of_clk_init()
130 prcmu_clk[PRCMU_PER1CLK] = clk; u8500_of_clk_init()
132 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); u8500_of_clk_init()
133 prcmu_clk[PRCMU_PER2CLK] = clk; u8500_of_clk_init()
135 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); u8500_of_clk_init()
136 prcmu_clk[PRCMU_PER3CLK] = clk; u8500_of_clk_init()
138 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); u8500_of_clk_init()
139 prcmu_clk[PRCMU_PER5CLK] = clk; u8500_of_clk_init()
141 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); u8500_of_clk_init()
142 prcmu_clk[PRCMU_PER6CLK] = clk; u8500_of_clk_init()
144 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); u8500_of_clk_init()
145 prcmu_clk[PRCMU_PER7CLK] = clk; u8500_of_clk_init()
147 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, u8500_of_clk_init()
149 prcmu_clk[PRCMU_LCDCLK] = clk; u8500_of_clk_init()
151 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); u8500_of_clk_init()
152 prcmu_clk[PRCMU_BMLCLK] = clk; u8500_of_clk_init()
154 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, u8500_of_clk_init()
156 prcmu_clk[PRCMU_HSITXCLK] = clk; u8500_of_clk_init()
158 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, u8500_of_clk_init()
160 prcmu_clk[PRCMU_HSIRXCLK] = clk; u8500_of_clk_init()
162 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, u8500_of_clk_init()
164 prcmu_clk[PRCMU_HDMICLK] = clk; u8500_of_clk_init()
166 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); u8500_of_clk_init()
167 prcmu_clk[PRCMU_APEATCLK] = clk; u8500_of_clk_init()
169 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, u8500_of_clk_init()
171 prcmu_clk[PRCMU_APETRACECLK] = clk; u8500_of_clk_init()
173 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); u8500_of_clk_init()
174 prcmu_clk[PRCMU_MCDECLK] = clk; u8500_of_clk_init()
176 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, u8500_of_clk_init()
178 prcmu_clk[PRCMU_IPI2CCLK] = clk; u8500_of_clk_init()
180 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, u8500_of_clk_init()
182 prcmu_clk[PRCMU_DSIALTCLK] = clk; u8500_of_clk_init()
184 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); u8500_of_clk_init()
185 prcmu_clk[PRCMU_DMACLK] = clk; u8500_of_clk_init()
187 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); u8500_of_clk_init()
188 prcmu_clk[PRCMU_B2R2CLK] = clk; u8500_of_clk_init()
190 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, u8500_of_clk_init()
192 prcmu_clk[PRCMU_TVCLK] = clk; u8500_of_clk_init()
194 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); u8500_of_clk_init()
195 prcmu_clk[PRCMU_SSPCLK] = clk; u8500_of_clk_init()
197 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); u8500_of_clk_init()
198 prcmu_clk[PRCMU_RNGCLK] = clk; u8500_of_clk_init()
200 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); u8500_of_clk_init()
201 prcmu_clk[PRCMU_UICCCLK] = clk; u8500_of_clk_init()
203 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); u8500_of_clk_init()
204 prcmu_clk[PRCMU_TIMCLK] = clk; u8500_of_clk_init()
206 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, u8500_of_clk_init()
209 prcmu_clk[PRCMU_SDMMCCLK] = clk; u8500_of_clk_init()
211 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", u8500_of_clk_init()
213 prcmu_clk[PRCMU_PLLDSI] = clk; u8500_of_clk_init()
215 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", u8500_of_clk_init()
217 prcmu_clk[PRCMU_DSI0CLK] = clk; u8500_of_clk_init()
219 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", u8500_of_clk_init()
221 prcmu_clk[PRCMU_DSI1CLK] = clk; u8500_of_clk_init()
223 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", u8500_of_clk_init()
225 prcmu_clk[PRCMU_DSI0ESCCLK] = clk; u8500_of_clk_init()
227 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", u8500_of_clk_init()
229 prcmu_clk[PRCMU_DSI1ESCCLK] = clk; u8500_of_clk_init()
231 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", u8500_of_clk_init()
233 prcmu_clk[PRCMU_DSI2ESCCLK] = clk; u8500_of_clk_init()
235 clk = clk_reg_prcmu_scalable_rate("armss", NULL, u8500_of_clk_init()
237 prcmu_clk[PRCMU_ARMSS] = clk; u8500_of_clk_init()
249 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, u8500_of_clk_init()
251 PRCC_PCLK_STORE(clk, 1, 0); u8500_of_clk_init()
253 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, u8500_of_clk_init()
255 PRCC_PCLK_STORE(clk, 1, 1); u8500_of_clk_init()
257 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, u8500_of_clk_init()
259 PRCC_PCLK_STORE(clk, 1, 2); u8500_of_clk_init()
261 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, u8500_of_clk_init()
263 PRCC_PCLK_STORE(clk, 1, 3); u8500_of_clk_init()
265 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, u8500_of_clk_init()
267 PRCC_PCLK_STORE(clk, 1, 4); u8500_of_clk_init()
269 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, u8500_of_clk_init()
271 PRCC_PCLK_STORE(clk, 1, 5); u8500_of_clk_init()
273 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, u8500_of_clk_init()
275 PRCC_PCLK_STORE(clk, 1, 6); u8500_of_clk_init()
277 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, u8500_of_clk_init()
279 PRCC_PCLK_STORE(clk, 1, 7); u8500_of_clk_init()
281 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, u8500_of_clk_init()
283 PRCC_PCLK_STORE(clk, 1, 8); u8500_of_clk_init()
285 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, u8500_of_clk_init()
287 PRCC_PCLK_STORE(clk, 1, 9); u8500_of_clk_init()
289 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, u8500_of_clk_init()
291 PRCC_PCLK_STORE(clk, 1, 10); u8500_of_clk_init()
293 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, u8500_of_clk_init()
295 PRCC_PCLK_STORE(clk, 1, 11); u8500_of_clk_init()
297 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, u8500_of_clk_init()
299 PRCC_PCLK_STORE(clk, 2, 0); u8500_of_clk_init()
301 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, u8500_of_clk_init()
303 PRCC_PCLK_STORE(clk, 2, 1); u8500_of_clk_init()
305 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, u8500_of_clk_init()
307 PRCC_PCLK_STORE(clk, 2, 2); u8500_of_clk_init()
309 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, u8500_of_clk_init()
311 PRCC_PCLK_STORE(clk, 2, 3); u8500_of_clk_init()
313 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, u8500_of_clk_init()
315 PRCC_PCLK_STORE(clk, 2, 4); u8500_of_clk_init()
317 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, u8500_of_clk_init()
319 PRCC_PCLK_STORE(clk, 2, 5); u8500_of_clk_init()
321 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, u8500_of_clk_init()
323 PRCC_PCLK_STORE(clk, 2, 6); u8500_of_clk_init()
325 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, u8500_of_clk_init()
327 PRCC_PCLK_STORE(clk, 2, 7); u8500_of_clk_init()
329 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, u8500_of_clk_init()
331 PRCC_PCLK_STORE(clk, 2, 8); u8500_of_clk_init()
333 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, u8500_of_clk_init()
335 PRCC_PCLK_STORE(clk, 2, 9); u8500_of_clk_init()
337 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, u8500_of_clk_init()
339 PRCC_PCLK_STORE(clk, 2, 10); u8500_of_clk_init()
341 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, u8500_of_clk_init()
343 PRCC_PCLK_STORE(clk, 2, 11); u8500_of_clk_init()
345 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, u8500_of_clk_init()
347 PRCC_PCLK_STORE(clk, 2, 12); u8500_of_clk_init()
349 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, u8500_of_clk_init()
351 PRCC_PCLK_STORE(clk, 3, 0); u8500_of_clk_init()
353 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, u8500_of_clk_init()
355 PRCC_PCLK_STORE(clk, 3, 1); u8500_of_clk_init()
357 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, u8500_of_clk_init()
359 PRCC_PCLK_STORE(clk, 3, 2); u8500_of_clk_init()
361 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, u8500_of_clk_init()
363 PRCC_PCLK_STORE(clk, 3, 3); u8500_of_clk_init()
365 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, u8500_of_clk_init()
367 PRCC_PCLK_STORE(clk, 3, 4); u8500_of_clk_init()
369 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, u8500_of_clk_init()
371 PRCC_PCLK_STORE(clk, 3, 5); u8500_of_clk_init()
373 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, u8500_of_clk_init()
375 PRCC_PCLK_STORE(clk, 3, 6); u8500_of_clk_init()
377 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, u8500_of_clk_init()
379 PRCC_PCLK_STORE(clk, 3, 7); u8500_of_clk_init()
381 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, u8500_of_clk_init()
383 PRCC_PCLK_STORE(clk, 3, 8); u8500_of_clk_init()
385 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, u8500_of_clk_init()
387 PRCC_PCLK_STORE(clk, 5, 0); u8500_of_clk_init()
389 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, u8500_of_clk_init()
391 PRCC_PCLK_STORE(clk, 5, 1); u8500_of_clk_init()
393 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, u8500_of_clk_init()
395 PRCC_PCLK_STORE(clk, 6, 0); u8500_of_clk_init()
397 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, u8500_of_clk_init()
399 PRCC_PCLK_STORE(clk, 6, 1); u8500_of_clk_init()
401 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, u8500_of_clk_init()
403 PRCC_PCLK_STORE(clk, 6, 2); u8500_of_clk_init()
405 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, u8500_of_clk_init()
407 PRCC_PCLK_STORE(clk, 6, 3); u8500_of_clk_init()
409 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, u8500_of_clk_init()
411 PRCC_PCLK_STORE(clk, 6, 4); u8500_of_clk_init()
413 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, u8500_of_clk_init()
415 PRCC_PCLK_STORE(clk, 6, 5); u8500_of_clk_init()
417 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, u8500_of_clk_init()
419 PRCC_PCLK_STORE(clk, 6, 6); u8500_of_clk_init()
421 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, u8500_of_clk_init()
423 PRCC_PCLK_STORE(clk, 6, 7); u8500_of_clk_init()
434 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", u8500_of_clk_init()
436 PRCC_KCLK_STORE(clk, 1, 0); u8500_of_clk_init()
438 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", u8500_of_clk_init()
440 PRCC_KCLK_STORE(clk, 1, 1); u8500_of_clk_init()
442 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", u8500_of_clk_init()
444 PRCC_KCLK_STORE(clk, 1, 2); u8500_of_clk_init()
446 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", u8500_of_clk_init()
448 PRCC_KCLK_STORE(clk, 1, 3); u8500_of_clk_init()
450 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", u8500_of_clk_init()
452 PRCC_KCLK_STORE(clk, 1, 4); u8500_of_clk_init()
454 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", u8500_of_clk_init()
456 PRCC_KCLK_STORE(clk, 1, 5); u8500_of_clk_init()
458 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", u8500_of_clk_init()
460 PRCC_KCLK_STORE(clk, 1, 6); u8500_of_clk_init()
462 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", u8500_of_clk_init()
464 PRCC_KCLK_STORE(clk, 1, 8); u8500_of_clk_init()
466 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", u8500_of_clk_init()
468 PRCC_KCLK_STORE(clk, 1, 9); u8500_of_clk_init()
470 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", u8500_of_clk_init()
472 PRCC_KCLK_STORE(clk, 1, 10); u8500_of_clk_init()
475 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", u8500_of_clk_init()
477 PRCC_KCLK_STORE(clk, 2, 0); u8500_of_clk_init()
479 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", u8500_of_clk_init()
481 PRCC_KCLK_STORE(clk, 2, 2); u8500_of_clk_init()
483 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", u8500_of_clk_init()
485 PRCC_KCLK_STORE(clk, 2, 3); u8500_of_clk_init()
487 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", u8500_of_clk_init()
489 PRCC_KCLK_STORE(clk, 2, 4); u8500_of_clk_init()
491 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", u8500_of_clk_init()
493 PRCC_KCLK_STORE(clk, 2, 5); u8500_of_clk_init()
496 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", u8500_of_clk_init()
499 PRCC_KCLK_STORE(clk, 2, 6); u8500_of_clk_init()
501 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", u8500_of_clk_init()
504 PRCC_KCLK_STORE(clk, 2, 7); u8500_of_clk_init()
507 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", u8500_of_clk_init()
509 PRCC_KCLK_STORE(clk, 3, 1); u8500_of_clk_init()
511 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", u8500_of_clk_init()
513 PRCC_KCLK_STORE(clk, 3, 2); u8500_of_clk_init()
515 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", u8500_of_clk_init()
517 PRCC_KCLK_STORE(clk, 3, 3); u8500_of_clk_init()
519 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", u8500_of_clk_init()
521 PRCC_KCLK_STORE(clk, 3, 4); u8500_of_clk_init()
523 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", u8500_of_clk_init()
525 PRCC_KCLK_STORE(clk, 3, 5); u8500_of_clk_init()
527 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", u8500_of_clk_init()
529 PRCC_KCLK_STORE(clk, 3, 6); u8500_of_clk_init()
531 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", u8500_of_clk_init()
533 PRCC_KCLK_STORE(clk, 3, 7); u8500_of_clk_init()
536 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", u8500_of_clk_init()
538 PRCC_KCLK_STORE(clk, 6, 0); u8500_of_clk_init()
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| H A D | clk-prcc.c | 10 #include <linux/clk-provider.h>
16 #include "clk.h"
38 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_pclk_enable() local
40 writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); clk_prcc_pclk_enable()
41 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) clk_prcc_pclk_enable()
44 clk->is_enabled = 1; clk_prcc_pclk_enable()
50 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_pclk_disable() local
52 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); clk_prcc_pclk_disable()
53 clk->is_enabled = 0; clk_prcc_pclk_disable()
58 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_kclk_enable() local
60 writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); clk_prcc_kclk_enable()
61 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) clk_prcc_kclk_enable()
64 clk->is_enabled = 1; clk_prcc_kclk_enable()
70 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_kclk_disable() local
72 writel(clk->cg_sel, (clk->base + PRCC_KCKDIS)); clk_prcc_kclk_disable()
73 clk->is_enabled = 0; clk_prcc_kclk_disable()
78 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_is_enabled() local
79 return clk->is_enabled; clk_prcc_is_enabled()
94 static struct clk *clk_reg_prcc(const char *name, clk_reg_prcc()
101 struct clk_prcc *clk; clk_reg_prcc() local
103 struct clk *clk_reg; clk_reg_prcc()
110 clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL); clk_reg_prcc()
111 if (!clk) { clk_reg_prcc()
112 pr_err("clk_prcc: %s could not allocate clk\n", __func__); clk_reg_prcc()
116 clk->base = ioremap(phy_base, SZ_4K); clk_reg_prcc()
117 if (!clk->base) clk_reg_prcc()
120 clk->cg_sel = cg_sel; clk_reg_prcc()
121 clk->is_enabled = 1; clk_reg_prcc()
128 clk->hw.init = &clk_prcc_init; clk_reg_prcc()
130 clk_reg = clk_register(NULL, &clk->hw); clk_reg_prcc()
137 iounmap(clk->base); clk_reg_prcc()
139 kfree(clk); clk_reg_prcc()
140 pr_err("clk_prcc: %s failed to register clk\n", __func__); clk_reg_prcc()
144 struct clk *clk_reg_prcc_pclk(const char *name, clk_reg_prcc_pclk()
154 struct clk *clk_reg_prcc_kclk(const char *name, clk_reg_prcc_kclk()
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| H A D | clk-sysctrl.c | 10 #include <linux/clk-provider.h>
17 #include "clk.h"
39 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_prepare() local
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], clk_sysctrl_prepare()
42 clk->reg_bits[0]); clk_sysctrl_prepare()
44 if (!ret && clk->enable_delay_us) clk_sysctrl_prepare()
45 usleep_range(clk->enable_delay_us, clk->enable_delay_us); clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) clk_sysctrl_unprepare()
54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", clk_sysctrl_unprepare()
55 __func__, __clk_get_name(hw->clk)); clk_sysctrl_unprepare()
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_recalc_rate() local
62 return clk->rate; clk_sysctrl_recalc_rate()
67 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_set_parent() local
68 u8 old_index = clk->parent_index; clk_sysctrl_set_parent()
71 if (clk->reg_sel[old_index]) { clk_sysctrl_set_parent()
72 ret = ab8500_sysctrl_clear(clk->reg_sel[old_index], clk_sysctrl_set_parent()
73 clk->reg_mask[old_index]); clk_sysctrl_set_parent()
78 if (clk->reg_sel[index]) { clk_sysctrl_set_parent()
79 ret = ab8500_sysctrl_write(clk->reg_sel[index], clk_sysctrl_set_parent()
80 clk->reg_mask[index], clk_sysctrl_set_parent()
81 clk->reg_bits[index]); clk_sysctrl_set_parent()
83 if (clk->reg_sel[old_index]) clk_sysctrl_set_parent()
84 ab8500_sysctrl_write(clk->reg_sel[old_index], clk_sysctrl_set_parent()
85 clk->reg_mask[old_index], clk_sysctrl_set_parent()
86 clk->reg_bits[old_index]); clk_sysctrl_set_parent()
90 clk->parent_index = index; clk_sysctrl_set_parent()
97 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_get_parent() local
98 return clk->parent_index; clk_sysctrl_get_parent()
117 static struct clk *clk_reg_sysctrl(struct device *dev, clk_reg_sysctrl()
129 struct clk_sysctrl *clk; clk_reg_sysctrl() local
131 struct clk *clk_reg; clk_reg_sysctrl()
142 clk = devm_kzalloc(dev, sizeof(struct clk_sysctrl), GFP_KERNEL); clk_reg_sysctrl()
143 if (!clk) { clk_reg_sysctrl()
144 dev_err(dev, "clk_sysctrl: could not allocate clk\n"); clk_reg_sysctrl()
149 clk->reg_sel[0] = reg_sel[0]; clk_reg_sysctrl()
150 clk->reg_bits[0] = reg_bits[0]; clk_reg_sysctrl()
151 clk->reg_mask[0] = reg_mask[0]; clk_reg_sysctrl()
155 clk->reg_sel[i] = reg_sel[i]; clk_reg_sysctrl()
156 clk->reg_bits[i] = reg_bits[i]; clk_reg_sysctrl()
157 clk->reg_mask[i] = reg_mask[i]; clk_reg_sysctrl()
160 clk->parent_index = 0; clk_reg_sysctrl()
161 clk->rate = rate; clk_reg_sysctrl()
162 clk->enable_delay_us = enable_delay_us; clk_reg_sysctrl()
163 clk->dev = dev; clk_reg_sysctrl()
170 clk->hw.init = &clk_sysctrl_init; clk_reg_sysctrl()
172 clk_reg = devm_clk_register(clk->dev, &clk->hw); clk_reg_sysctrl()
179 struct clk *clk_reg_sysctrl_gate(struct device *dev, clk_reg_sysctrl_gate()
196 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, clk_reg_sysctrl_gate_fixed_rate()
215 struct clk *clk_reg_sysctrl_set_parent(struct device *dev, clk_reg_sysctrl_set_parent()
|
| H A D | abx500-clk.c | 16 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
20 #include "clk.h"
26 struct clk *clk; ab8500_reg_clks() local
44 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, ab8500_reg_clks()
46 clk_register_clkdev(clk, "sysclk", "ab8500-usb.0"); ab8500_reg_clks()
47 clk_register_clkdev(clk, "sysclk", "ab-iddet.0"); ab8500_reg_clks()
48 clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0"); ab8500_reg_clks()
49 clk_register_clkdev(clk, "sysclk", "shrm_bus"); ab8500_reg_clks()
52 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk", ab8500_reg_clks()
55 clk_register_clkdev(clk, "sysclk", "0-0070"); ab8500_reg_clks()
58 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk", ab8500_reg_clks()
61 clk_register_clkdev(clk, "sysclk", "cg1960_core.0"); ab8500_reg_clks()
64 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk", ab8500_reg_clks()
69 clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL, ab8500_reg_clks()
73 clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0"); ab8500_reg_clks()
76 clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2, ab8500_reg_clks()
78 clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0"); ab8500_reg_clks()
79 clk_register_clkdev(clk, NULL, "ab8500-pwm.1"); ab8500_reg_clks()
82 clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk", ab8500_reg_clks()
85 clk_register_clkdev(clk, "audioclk", "ab8500-codec.0"); ab8500_reg_clks()
123 .name = "abx500-clk",
136 MODULE_DESCRIPTION("ABX500 clk driver");
|
| H A D | clk-prcmu.c | 10 #include <linux/clk-provider.h>
15 #include "clk.h"
32 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_prepare() local
34 ret = prcmu_request_clock(clk->cg_sel, true); clk_prcmu_prepare()
36 clk->is_prepared = 1; clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) clk_prcmu_unprepare()
46 __clk_get_name(hw->clk)); clk_prcmu_unprepare()
48 clk->is_prepared = 0; clk_prcmu_unprepare()
53 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_is_prepared() local
54 return clk->is_prepared; clk_prcmu_is_prepared()
59 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_enable() local
60 clk->is_enabled = 1; clk_prcmu_enable()
66 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_disable() local
67 clk->is_enabled = 0; clk_prcmu_disable()
72 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_is_enabled() local
73 return clk->is_enabled; clk_prcmu_is_enabled()
79 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_recalc_rate() local
80 return prcmu_clock_rate(clk->cg_sel); clk_prcmu_recalc_rate()
86 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_round_rate() local
87 return prcmu_round_clock_rate(clk->cg_sel, rate); clk_prcmu_round_rate()
93 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_set_rate() local
94 return prcmu_set_clock_rate(clk->cg_sel, rate); clk_prcmu_set_rate()
100 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_prepare() local
102 if (!clk->opp_requested) { clk_prcmu_opp_prepare()
104 (char *)__clk_get_name(hw->clk), clk_prcmu_opp_prepare()
108 __func__, __clk_get_name(hw->clk)); clk_prcmu_opp_prepare()
111 clk->opp_requested = 1; clk_prcmu_opp_prepare()
114 err = prcmu_request_clock(clk->cg_sel, true); clk_prcmu_opp_prepare()
117 (char *)__clk_get_name(hw->clk)); clk_prcmu_opp_prepare()
118 clk->opp_requested = 0; clk_prcmu_opp_prepare()
122 clk->is_prepared = 1; clk_prcmu_opp_prepare()
128 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_unprepare() local
130 if (prcmu_request_clock(clk->cg_sel, false)) { clk_prcmu_opp_unprepare()
132 __clk_get_name(hw->clk)); clk_prcmu_opp_unprepare()
136 if (clk->opp_requested) { clk_prcmu_opp_unprepare()
138 (char *)__clk_get_name(hw->clk)); clk_prcmu_opp_unprepare()
139 clk->opp_requested = 0; clk_prcmu_opp_unprepare()
142 clk->is_prepared = 0; clk_prcmu_opp_unprepare()
148 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_volt_prepare() local
150 if (!clk->opp_requested) { clk_prcmu_opp_volt_prepare()
154 __func__, __clk_get_name(hw->clk)); clk_prcmu_opp_volt_prepare()
157 clk->opp_requested = 1; clk_prcmu_opp_volt_prepare()
160 err = prcmu_request_clock(clk->cg_sel, true); clk_prcmu_opp_volt_prepare()
163 clk->opp_requested = 0; clk_prcmu_opp_volt_prepare()
167 clk->is_prepared = 1; clk_prcmu_opp_volt_prepare()
173 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_volt_unprepare() local
175 if (prcmu_request_clock(clk->cg_sel, false)) { clk_prcmu_opp_volt_unprepare()
177 __clk_get_name(hw->clk)); clk_prcmu_opp_volt_unprepare()
181 if (clk->opp_requested) { clk_prcmu_opp_volt_unprepare()
183 clk->opp_requested = 0; clk_prcmu_opp_volt_unprepare()
186 clk->is_prepared = 0; clk_prcmu_opp_volt_unprepare()
245 static struct clk *clk_reg_prcmu(const char *name, clk_reg_prcmu()
252 struct clk_prcmu *clk; clk_reg_prcmu() local
254 struct clk *clk_reg; clk_reg_prcmu()
261 clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL); clk_reg_prcmu()
262 if (!clk) { clk_reg_prcmu()
263 pr_err("clk_prcmu: %s could not allocate clk\n", __func__); clk_reg_prcmu()
267 clk->cg_sel = cg_sel; clk_reg_prcmu()
268 clk->is_prepared = 1; clk_reg_prcmu()
269 clk->is_enabled = 1; clk_reg_prcmu()
270 clk->opp_requested = 0; clk_reg_prcmu()
280 clk->hw.init = &clk_prcmu_init; clk_reg_prcmu()
282 clk_reg = clk_register(NULL, &clk->hw); clk_reg_prcmu()
289 kfree(clk); clk_reg_prcmu()
290 pr_err("clk_prcmu: %s failed to register clk\n", __func__); clk_reg_prcmu()
294 struct clk *clk_reg_prcmu_scalable(const char *name, clk_reg_prcmu_scalable()
304 struct clk *clk_reg_prcmu_gate(const char *name, clk_reg_prcmu_gate()
313 struct clk *clk_reg_prcmu_scalable_rate(const char *name, clk_reg_prcmu_scalable_rate()
323 struct clk *clk_reg_prcmu_rate(const char *name, clk_reg_prcmu_rate()
332 struct clk *clk_reg_prcmu_opp_gate(const char *name, clk_reg_prcmu_opp_gate()
341 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, clk_reg_prcmu_opp_volt_scalable()
|
| H A D | u9540_clk.c | 10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-ux500.h>
15 #include "clk.h"
|
| H A D | clk.h | 13 #include <linux/clk.h>
17 struct clk *clk_reg_prcc_pclk(const char *name,
23 struct clk *clk_reg_prcc_kclk(const char *name,
29 struct clk *clk_reg_prcmu_scalable(const char *name,
35 struct clk *clk_reg_prcmu_gate(const char *name,
40 struct clk *clk_reg_prcmu_scalable_rate(const char *name,
46 struct clk *clk_reg_prcmu_rate(const char *name,
51 struct clk *clk_reg_prcmu_opp_gate(const char *name,
56 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
62 struct clk *clk_reg_sysctrl_gate(struct device *dev,
71 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
81 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
|
| /linux-4.1.27/arch/m68k/coldfire/ |
| H A D | clk.c | 4 * clk.c -- general ColdFire CPU kernel clk handling
15 #include <linux/clk.h>
30 void __clk_init_enabled(struct clk *clk) __clk_init_enabled() argument
32 clk->enabled = 1; __clk_init_enabled()
33 clk->clk_ops->enable(clk); __clk_init_enabled()
36 void __clk_init_disabled(struct clk *clk) __clk_init_disabled() argument
38 clk->enabled = 0; __clk_init_disabled()
39 clk->clk_ops->disable(clk); __clk_init_disabled()
42 static void __clk_enable0(struct clk *clk) __clk_enable0() argument
44 __raw_writeb(clk->slot, MCFPM_PPMCR0); __clk_enable0()
47 static void __clk_disable0(struct clk *clk) __clk_disable0() argument
49 __raw_writeb(clk->slot, MCFPM_PPMSR0); __clk_disable0()
58 static void __clk_enable1(struct clk *clk) __clk_enable1() argument
60 __raw_writeb(clk->slot, MCFPM_PPMCR1); __clk_enable1()
63 static void __clk_disable1(struct clk *clk) __clk_disable1() argument
65 __raw_writeb(clk->slot, MCFPM_PPMSR1); __clk_disable1()
75 struct clk *clk_get(struct device *dev, const char *id) clk_get()
78 struct clk *clk; clk_get() local
81 for (i = 0; (clk = mcf_clks[i]) != NULL; ++i) clk_get()
82 if (!strcmp(clk->name, clk_name)) clk_get()
83 return clk; clk_get()
89 int clk_enable(struct clk *clk) clk_enable() argument
93 if ((clk->enabled++ == 0) && clk->clk_ops) clk_enable()
94 clk->clk_ops->enable(clk); clk_enable()
101 void clk_disable(struct clk *clk) clk_disable() argument
105 if ((--clk->enabled == 0) && clk->clk_ops) clk_disable()
106 clk->clk_ops->disable(clk); clk_disable()
111 void clk_put(struct clk *clk) clk_put() argument
113 if (clk->enabled != 0) clk_put()
114 pr_warn("clk_put %s still enabled\n", clk->name); clk_put()
118 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
120 return clk->rate; clk_get_rate()
|
| /linux-4.1.27/arch/mips/lantiq/ |
| H A D | clk.c | 14 #include <linux/clk.h>
25 #include "clk.h"
29 static struct clk cpu_clk_generic[4];
40 struct clk *clk_get_cpu(void) clk_get_cpu()
45 struct clk *clk_get_fpi(void) clk_get_fpi()
51 struct clk *clk_get_io(void) clk_get_io()
56 struct clk *clk_get_ppe(void) clk_get_ppe()
62 static inline int clk_good(struct clk *clk) clk_good() argument
64 return clk && !IS_ERR(clk); clk_good()
67 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
69 if (unlikely(!clk_good(clk))) clk_get_rate()
72 if (clk->rate != 0) clk_get_rate()
73 return clk->rate; clk_get_rate()
75 if (clk->get_rate != NULL) clk_get_rate()
76 return clk->get_rate(); clk_get_rate()
82 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
84 if (unlikely(!clk_good(clk))) clk_set_rate()
86 if (clk->rates && *clk->rates) { clk_set_rate()
87 unsigned long *r = clk->rates; clk_set_rate()
92 pr_err("clk %s.%s: trying to set invalid rate %ld\n", clk_set_rate()
93 clk->cl.dev_id, clk->cl.con_id, rate); clk_set_rate()
97 clk->rate = rate; clk_set_rate()
102 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
104 if (unlikely(!clk_good(clk))) clk_round_rate()
106 if (clk->rates && *clk->rates) { clk_round_rate()
107 unsigned long *r = clk->rates; clk_round_rate()
112 return clk->rate; clk_round_rate()
119 int clk_enable(struct clk *clk) clk_enable() argument
121 if (unlikely(!clk_good(clk))) clk_enable()
124 if (clk->enable) clk_enable()
125 return clk->enable(clk); clk_enable()
131 void clk_disable(struct clk *clk) clk_disable() argument
133 if (unlikely(!clk_good(clk))) clk_disable()
136 if (clk->disable) clk_disable()
137 clk->disable(clk); clk_disable()
141 int clk_activate(struct clk *clk) clk_activate() argument
143 if (unlikely(!clk_good(clk))) clk_activate()
146 if (clk->activate) clk_activate()
147 return clk->activate(clk); clk_activate()
153 void clk_deactivate(struct clk *clk) clk_deactivate() argument
155 if (unlikely(!clk_good(clk))) clk_deactivate()
158 if (clk->deactivate) clk_deactivate()
159 clk->deactivate(clk); clk_deactivate()
163 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) of_clk_get_from_provider()
186 struct clk *clk; plat_time_init() local
190 clk = clk_get_cpu(); plat_time_init()
191 mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution(); plat_time_init()
193 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); plat_time_init()
194 clk_put(clk); plat_time_init()
|
| H A D | clk.h | 55 struct clk { struct
62 int (*enable) (struct clk *clk);
63 void (*disable) (struct clk *clk);
64 int (*activate) (struct clk *clk);
65 void (*deactivate) (struct clk *clk);
66 void (*reboot) (struct clk *clk);
|
| /linux-4.1.27/arch/arm/mach-mmp/ |
| H A D | clock.c | 13 #include <linux/clk.h>
19 static void apbc_clk_enable(struct clk *clk) apbc_clk_enable() argument
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); apbc_clk_enable()
24 __raw_writel(clk_rst, clk->clk_rst); apbc_clk_enable()
27 static void apbc_clk_disable(struct clk *clk) apbc_clk_disable() argument
29 __raw_writel(0, clk->clk_rst); apbc_clk_disable()
37 static void apmu_clk_enable(struct clk *clk) apmu_clk_enable() argument
39 __raw_writel(clk->enable_val, clk->clk_rst); apmu_clk_enable()
42 static void apmu_clk_disable(struct clk *clk) apmu_clk_disable() argument
44 __raw_writel(0, clk->clk_rst); apmu_clk_disable()
54 int clk_enable(struct clk *clk) clk_enable() argument
59 if (clk->enabled++ == 0) clk_enable()
60 clk->ops->enable(clk); clk_enable()
66 void clk_disable(struct clk *clk) clk_disable() argument
70 WARN_ON(clk->enabled == 0); clk_disable()
73 if (--clk->enabled == 0) clk_disable()
74 clk->ops->disable(clk); clk_disable()
79 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
83 if (clk->ops->getrate) clk_get_rate()
84 rate = clk->ops->getrate(clk); clk_get_rate()
86 rate = clk->rate; clk_get_rate()
92 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
97 if (clk->ops->setrate) { clk_set_rate()
99 ret = clk->ops->setrate(clk, rate); clk_set_rate()
|
| H A D | clock.h | 12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
14 unsigned long (*getrate)(struct clk *);
15 int (*setrate)(struct clk *, unsigned long);
18 struct clk { struct
32 struct clk clk_##_name = { \
40 struct clk clk_##_name = { \
48 struct clk clk_##_name = { \
56 struct clk clk_##_name = { \
65 .clk = _clk, \
70 extern struct clk clk_pxa168_gpio;
71 extern struct clk clk_pxa168_timers;
|
| /linux-4.1.27/arch/blackfin/mach-common/ |
| H A D | clock.h | 4 #include <linux/clk.h>
7 unsigned long (*get_rate)(struct clk *clk);
8 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
9 int (*set_rate)(struct clk *clk, unsigned long rate);
10 int (*enable)(struct clk *clk);
11 int (*disable)(struct clk *clk);
14 struct clk { struct
|
| /linux-4.1.27/arch/mips/include/asm/ |
| H A D | clock.h | 7 #include <linux/clk.h>
9 struct clk;
12 void (*init) (struct clk *clk);
13 void (*enable) (struct clk *clk);
14 void (*disable) (struct clk *clk);
15 void (*recalc) (struct clk *clk);
16 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
17 long (*round_rate) (struct clk *clk, unsigned long rate);
20 struct clk { struct
26 struct clk *parent;
40 int __clk_enable(struct clk *);
41 void __clk_disable(struct clk *);
43 void clk_recalc_rate(struct clk *);
45 int clk_register(struct clk *);
46 void clk_unregister(struct clk *);
|
| H A D | clkdev.h | 10 * Helper for the clk API to assist looking up a struct clk.
18 #define __clk_get(clk) ({ 1; })
19 #define __clk_put(clk) do { } while (0)
|
| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | clk-imx27.c | 1 #include <linux/clk.h>
2 #include <linux/clk-provider.h>
9 #include "clk.h"
42 static struct clk *clk[IMX27_CLK_MAX]; variable in typeref:struct:clk
49 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); _mx27_clocks_init()
50 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); _mx27_clocks_init()
51 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); _mx27_clocks_init()
52 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); _mx27_clocks_init()
53 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); _mx27_clocks_init()
54 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); _mx27_clocks_init()
55 clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); _mx27_clocks_init()
56 clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); _mx27_clocks_init()
57 clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); _mx27_clocks_init()
58 clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0); _mx27_clocks_init()
59 clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); _mx27_clocks_init()
60 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); _mx27_clocks_init()
63 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); _mx27_clocks_init()
64 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); _mx27_clocks_init()
66 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); _mx27_clocks_init()
67 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); _mx27_clocks_init()
70 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); _mx27_clocks_init()
71 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); _mx27_clocks_init()
72 clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); _mx27_clocks_init()
73 clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); _mx27_clocks_init()
74 clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); _mx27_clocks_init()
75 clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); _mx27_clocks_init()
76 clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); _mx27_clocks_init()
77 clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); _mx27_clocks_init()
78 clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); _mx27_clocks_init()
79 clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); _mx27_clocks_init()
80 clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); _mx27_clocks_init()
83 clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); _mx27_clocks_init()
85 clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); _mx27_clocks_init()
87 clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); _mx27_clocks_init()
88 clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx27_clocks_init()
89 clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx27_clocks_init()
90 clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); _mx27_clocks_init()
91 clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); _mx27_clocks_init()
92 clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); _mx27_clocks_init()
93 clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); _mx27_clocks_init()
94 clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); _mx27_clocks_init()
95 clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); _mx27_clocks_init()
96 clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); _mx27_clocks_init()
97 clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); _mx27_clocks_init()
98 clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); _mx27_clocks_init()
99 clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); _mx27_clocks_init()
100 clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); _mx27_clocks_init()
101 clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); _mx27_clocks_init()
102 clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); _mx27_clocks_init()
103 clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); _mx27_clocks_init()
104 clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); _mx27_clocks_init()
105 clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); _mx27_clocks_init()
106 clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); _mx27_clocks_init()
107 clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); _mx27_clocks_init()
108 clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); _mx27_clocks_init()
109 clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); _mx27_clocks_init()
110 clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); _mx27_clocks_init()
111 clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); _mx27_clocks_init()
112 clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); _mx27_clocks_init()
113 clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); _mx27_clocks_init()
114 clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); _mx27_clocks_init()
115 clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); _mx27_clocks_init()
116 clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); _mx27_clocks_init()
117 clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); _mx27_clocks_init()
118 clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); _mx27_clocks_init()
119 clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); _mx27_clocks_init()
120 clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); _mx27_clocks_init()
121 clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); _mx27_clocks_init()
122 clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); _mx27_clocks_init()
123 clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); _mx27_clocks_init()
124 clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); _mx27_clocks_init()
125 clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); _mx27_clocks_init()
126 clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); _mx27_clocks_init()
127 clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); _mx27_clocks_init()
128 clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); _mx27_clocks_init()
129 clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); _mx27_clocks_init()
130 clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); _mx27_clocks_init()
131 clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); _mx27_clocks_init()
132 clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); _mx27_clocks_init()
133 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); _mx27_clocks_init()
134 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); _mx27_clocks_init()
135 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); _mx27_clocks_init()
136 clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); _mx27_clocks_init()
137 clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); _mx27_clocks_init()
138 clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); _mx27_clocks_init()
139 clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); _mx27_clocks_init()
140 clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); _mx27_clocks_init()
141 clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); _mx27_clocks_init()
142 clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); _mx27_clocks_init()
143 clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); _mx27_clocks_init()
144 clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); _mx27_clocks_init()
145 clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); _mx27_clocks_init()
146 clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); _mx27_clocks_init()
147 clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); _mx27_clocks_init()
148 clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); _mx27_clocks_init()
149 clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); _mx27_clocks_init()
150 clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); _mx27_clocks_init()
151 clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); _mx27_clocks_init()
152 clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); _mx27_clocks_init()
153 clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); _mx27_clocks_init()
155 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx27_clocks_init()
157 clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); _mx27_clocks_init()
159 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); _mx27_clocks_init()
170 clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx27_clocks_init()
171 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); mx27_clocks_init()
172 clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx27_clocks_init()
173 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); mx27_clocks_init()
174 clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx27_clocks_init()
175 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); mx27_clocks_init()
176 clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx27_clocks_init()
177 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); mx27_clocks_init()
178 clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); mx27_clocks_init()
179 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); mx27_clocks_init()
180 clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); mx27_clocks_init()
181 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); mx27_clocks_init()
182 clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); mx27_clocks_init()
183 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); mx27_clocks_init()
184 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); mx27_clocks_init()
185 clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); mx27_clocks_init()
186 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); mx27_clocks_init()
187 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); mx27_clocks_init()
188 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); mx27_clocks_init()
189 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); mx27_clocks_init()
190 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); mx27_clocks_init()
191 clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); mx27_clocks_init()
192 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); mx27_clocks_init()
193 clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); mx27_clocks_init()
194 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); mx27_clocks_init()
195 clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); mx27_clocks_init()
196 clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); mx27_clocks_init()
197 clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx27_clocks_init()
198 clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); mx27_clocks_init()
199 clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); mx27_clocks_init()
200 clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); mx27_clocks_init()
201 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); mx27_clocks_init()
202 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); mx27_clocks_init()
203 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); mx27_clocks_init()
204 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); mx27_clocks_init()
205 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); mx27_clocks_init()
206 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); mx27_clocks_init()
207 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); mx27_clocks_init()
208 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); mx27_clocks_init()
209 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); mx27_clocks_init()
210 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); mx27_clocks_init()
211 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); mx27_clocks_init()
212 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); mx27_clocks_init()
213 clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); mx27_clocks_init()
214 clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); mx27_clocks_init()
215 clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); mx27_clocks_init()
216 clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); mx27_clocks_init()
217 clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); mx27_clocks_init()
218 clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); mx27_clocks_init()
219 clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); mx27_clocks_init()
220 clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); mx27_clocks_init()
221 clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); mx27_clocks_init()
222 clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); mx27_clocks_init()
223 clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); mx27_clocks_init()
224 clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); mx27_clocks_init()
225 clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); mx27_clocks_init()
226 clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); mx27_clocks_init()
227 clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); mx27_clocks_init()
228 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); mx27_clocks_init()
229 clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); mx27_clocks_init()
230 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); mx27_clocks_init()
254 clk_data.clks = clk; mx27_clocks_init_dt()
255 clk_data.clk_num = ARRAY_SIZE(clk); mx27_clocks_init_dt()
|
| H A D | clk-imx51-imx53.c | 11 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
21 #include "clk.h"
131 static struct clk *clk[IMX5_CLK_END]; variable in typeref:struct:clk
138 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); mx5_clocks_common_init()
139 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); mx5_clocks_common_init()
140 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); mx5_clocks_common_init()
141 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); mx5_clocks_common_init()
142 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); mx5_clocks_common_init()
144 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, mx5_clocks_common_init()
146 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, mx5_clocks_common_init()
148 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, mx5_clocks_common_init()
150 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); mx5_clocks_common_init()
151 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); mx5_clocks_common_init()
152 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); mx5_clocks_common_init()
153 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, mx5_clocks_common_init()
155 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); mx5_clocks_common_init()
156 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); mx5_clocks_common_init()
157 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); mx5_clocks_common_init()
158 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); mx5_clocks_common_init()
159 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); mx5_clocks_common_init()
160 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); mx5_clocks_common_init()
161 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); mx5_clocks_common_init()
162 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); mx5_clocks_common_init()
163 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); mx5_clocks_common_init()
164 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); mx5_clocks_common_init()
165 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); mx5_clocks_common_init()
166 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, mx5_clocks_common_init()
168 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); mx5_clocks_common_init()
169 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); mx5_clocks_common_init()
171 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, mx5_clocks_common_init()
173 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, mx5_clocks_common_init()
175 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); mx5_clocks_common_init()
176 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); mx5_clocks_common_init()
177 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); mx5_clocks_common_init()
178 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); mx5_clocks_common_init()
179 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); mx5_clocks_common_init()
180 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); mx5_clocks_common_init()
182 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, mx5_clocks_common_init()
184 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); mx5_clocks_common_init()
185 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); mx5_clocks_common_init()
186 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, mx5_clocks_common_init()
188 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); mx5_clocks_common_init()
189 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); mx5_clocks_common_init()
190 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, mx5_clocks_common_init()
192 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); mx5_clocks_common_init()
193 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); mx5_clocks_common_init()
194 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); mx5_clocks_common_init()
195 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); mx5_clocks_common_init()
196 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, mx5_clocks_common_init()
198 clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels)); mx5_clocks_common_init()
199 clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels)); mx5_clocks_common_init()
200 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3); mx5_clocks_common_init()
201 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); mx5_clocks_common_init()
202 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); mx5_clocks_common_init()
203 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); mx5_clocks_common_init()
204 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); mx5_clocks_common_init()
205 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); mx5_clocks_common_init()
206 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); mx5_clocks_common_init()
207 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); mx5_clocks_common_init()
208 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); mx5_clocks_common_init()
209 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); mx5_clocks_common_init()
210 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); mx5_clocks_common_init()
211 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); mx5_clocks_common_init()
212 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); mx5_clocks_common_init()
213 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); mx5_clocks_common_init()
214 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); mx5_clocks_common_init()
215 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); mx5_clocks_common_init()
216 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); mx5_clocks_common_init()
217 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); mx5_clocks_common_init()
218 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); mx5_clocks_common_init()
219 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); mx5_clocks_common_init()
220 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); mx5_clocks_common_init()
221 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); mx5_clocks_common_init()
222 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); mx5_clocks_common_init()
223 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); mx5_clocks_common_init()
224 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); mx5_clocks_common_init()
225 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); mx5_clocks_common_init()
226 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); mx5_clocks_common_init()
227 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); mx5_clocks_common_init()
228 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); mx5_clocks_common_init()
229 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); mx5_clocks_common_init()
230 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); mx5_clocks_common_init()
231 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); mx5_clocks_common_init()
232 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); mx5_clocks_common_init()
233 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); mx5_clocks_common_init()
234 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); mx5_clocks_common_init()
235 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); mx5_clocks_common_init()
236 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); mx5_clocks_common_init()
237 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); mx5_clocks_common_init()
238 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); mx5_clocks_common_init()
239 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); mx5_clocks_common_init()
240 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); mx5_clocks_common_init()
241 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); mx5_clocks_common_init()
242 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); mx5_clocks_common_init()
243 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); mx5_clocks_common_init()
244 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); mx5_clocks_common_init()
245 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); mx5_clocks_common_init()
246 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); mx5_clocks_common_init()
247 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); mx5_clocks_common_init()
248 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); mx5_clocks_common_init()
249 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); mx5_clocks_common_init()
250 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); mx5_clocks_common_init()
251 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); mx5_clocks_common_init()
252 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); mx5_clocks_common_init()
254 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); mx5_clocks_common_init()
255 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
256 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
257 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); mx5_clocks_common_init()
258 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
259 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
260 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); mx5_clocks_common_init()
261 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); mx5_clocks_common_init()
262 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); mx5_clocks_common_init()
263 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); mx5_clocks_common_init()
264 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); mx5_clocks_common_init()
265 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); mx5_clocks_common_init()
266 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); mx5_clocks_common_init()
267 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); mx5_clocks_common_init()
268 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); mx5_clocks_common_init()
269 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); mx5_clocks_common_init()
270 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); mx5_clocks_common_init()
271 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); mx5_clocks_common_init()
272 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); mx5_clocks_common_init()
273 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); mx5_clocks_common_init()
274 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); mx5_clocks_common_init()
275 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); mx5_clocks_common_init()
276 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); mx5_clocks_common_init()
277 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); mx5_clocks_common_init()
278 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); mx5_clocks_common_init()
279 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); mx5_clocks_common_init()
280 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); mx5_clocks_common_init()
281 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); mx5_clocks_common_init()
282 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); mx5_clocks_common_init()
283 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); mx5_clocks_common_init()
284 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); mx5_clocks_common_init()
285 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, mx5_clocks_common_init()
287 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); mx5_clocks_common_init()
288 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); mx5_clocks_common_init()
289 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); mx5_clocks_common_init()
290 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); mx5_clocks_common_init()
292 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); mx5_clocks_common_init()
293 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); mx5_clocks_common_init()
296 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); mx5_clocks_common_init()
297 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); mx5_clocks_common_init()
299 /* move usb phy clk to 24MHz */ mx5_clocks_common_init()
300 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); mx5_clocks_common_init()
302 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); mx5_clocks_common_init()
303 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ mx5_clocks_common_init()
304 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); mx5_clocks_common_init()
305 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ mx5_clocks_common_init()
306 clk_prepare_enable(clk[IMX5_CLK_SPBA]); mx5_clocks_common_init()
307 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ mx5_clocks_common_init()
308 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ mx5_clocks_common_init()
309 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); mx5_clocks_common_init()
310 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); mx5_clocks_common_init()
311 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); mx5_clocks_common_init()
312 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); mx5_clocks_common_init()
313 clk_prepare_enable(clk[IMX5_CLK_TMAX1]); mx5_clocks_common_init()
314 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ mx5_clocks_common_init()
315 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ mx5_clocks_common_init()
326 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx50_clocks_init()
330 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx50_clocks_init()
334 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx50_clocks_init()
341 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, mx50_clocks_init()
343 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); mx50_clocks_init()
344 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); mx50_clocks_init()
345 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); mx50_clocks_init()
346 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); mx50_clocks_init()
347 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); mx50_clocks_init()
348 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); mx50_clocks_init()
349 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); mx50_clocks_init()
351 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, mx50_clocks_init()
353 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); mx50_clocks_init()
354 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); mx50_clocks_init()
356 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, mx50_clocks_init()
358 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); mx50_clocks_init()
359 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); mx50_clocks_init()
361 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx50_clocks_init()
363 clk_data.clks = clk; mx50_clocks_init()
364 clk_data.clk_num = ARRAY_SIZE(clk); mx50_clocks_init()
368 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); mx50_clocks_init()
369 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); mx50_clocks_init()
371 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); mx50_clocks_init()
373 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); mx50_clocks_init()
375 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); mx50_clocks_init()
376 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mx50_clocks_init()
388 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx51_clocks_init()
392 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx51_clocks_init()
396 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx51_clocks_init()
403 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, mx51_clocks_init()
405 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, mx51_clocks_init()
407 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, mx51_clocks_init()
409 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, mx51_clocks_init()
411 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, mx51_clocks_init()
413 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); mx51_clocks_init()
414 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); mx51_clocks_init()
415 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); mx51_clocks_init()
416 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); mx51_clocks_init()
417 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); mx51_clocks_init()
418 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); mx51_clocks_init()
419 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); mx51_clocks_init()
420 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); mx51_clocks_init()
421 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); mx51_clocks_init()
422 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); mx51_clocks_init()
423 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); mx51_clocks_init()
424 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); mx51_clocks_init()
425 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, mx51_clocks_init()
427 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, mx51_clocks_init()
429 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); mx51_clocks_init()
430 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); mx51_clocks_init()
431 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, mx51_clocks_init()
433 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); mx51_clocks_init()
435 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx51_clocks_init()
437 clk_data.clks = clk; mx51_clocks_init()
438 clk_data.clk_num = ARRAY_SIZE(clk); mx51_clocks_init()
442 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); mx51_clocks_init()
445 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); mx51_clocks_init()
446 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); mx51_clocks_init()
448 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); mx51_clocks_init()
450 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); mx51_clocks_init()
477 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx53_clocks_init()
481 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx53_clocks_init()
485 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx53_clocks_init()
489 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base); mx53_clocks_init()
496 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, mx53_clocks_init()
498 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); mx53_clocks_init()
499 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); mx53_clocks_init()
500 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, mx53_clocks_init()
502 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); mx53_clocks_init()
503 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); mx53_clocks_init()
504 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); mx53_clocks_init()
505 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, mx53_clocks_init()
507 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); mx53_clocks_init()
508 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); mx53_clocks_init()
509 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, mx53_clocks_init()
511 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, mx53_clocks_init()
513 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, mx53_clocks_init()
515 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); mx53_clocks_init()
516 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); mx53_clocks_init()
517 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); mx53_clocks_init()
518 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); mx53_clocks_init()
519 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); mx53_clocks_init()
520 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); mx53_clocks_init()
521 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); mx53_clocks_init()
522 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); mx53_clocks_init()
523 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, mx53_clocks_init()
525 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); mx53_clocks_init()
526 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); mx53_clocks_init()
527 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); mx53_clocks_init()
528 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); mx53_clocks_init()
529 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); mx53_clocks_init()
530 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); mx53_clocks_init()
531 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); mx53_clocks_init()
533 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, mx53_clocks_init()
535 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); mx53_clocks_init()
536 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); mx53_clocks_init()
538 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, mx53_clocks_init()
540 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); mx53_clocks_init()
541 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); mx53_clocks_init()
542 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, mx53_clocks_init()
544 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf", mx53_clocks_init()
545 clk[IMX5_CLK_CPU_PODF], mx53_clocks_init()
546 clk[IMX5_CLK_CPU_PODF_SEL], mx53_clocks_init()
547 clk[IMX5_CLK_PLL1_SW], mx53_clocks_init()
548 clk[IMX5_CLK_STEP_SEL]); mx53_clocks_init()
550 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx53_clocks_init()
552 clk_data.clks = clk; mx53_clocks_init()
553 clk_data.clk_num = ARRAY_SIZE(clk); mx53_clocks_init()
557 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); mx53_clocks_init()
558 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); mx53_clocks_init()
560 /* move can bus clk to 24MHz */ mx53_clocks_init()
561 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); mx53_clocks_init()
564 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); mx53_clocks_init()
566 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); mx53_clocks_init()
568 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); mx53_clocks_init()
570 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); mx53_clocks_init()
571 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mx53_clocks_init()
|
| H A D | clk-imx21.c | 12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
19 #include "clk.h"
39 static struct clk *clk[IMX21_CLK_MAX]; variable in typeref:struct:clk
46 clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); _mx21_clocks_init()
47 clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); _mx21_clocks_init()
48 clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); _mx21_clocks_init()
49 clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); _mx21_clocks_init()
50 clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); _mx21_clocks_init()
52 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); _mx21_clocks_init()
53 clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); _mx21_clocks_init()
54 clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); _mx21_clocks_init()
55 clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); _mx21_clocks_init()
56 clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); _mx21_clocks_init()
57 clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); _mx21_clocks_init()
58 clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); _mx21_clocks_init()
59 clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); _mx21_clocks_init()
60 clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks)); _mx21_clocks_init()
61 clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx21_clocks_init()
62 clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx21_clocks_init()
63 clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3); _mx21_clocks_init()
64 clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); _mx21_clocks_init()
66 clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); _mx21_clocks_init()
68 clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0); _mx21_clocks_init()
70 clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); _mx21_clocks_init()
71 clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); _mx21_clocks_init()
72 clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); _mx21_clocks_init()
74 clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6); _mx21_clocks_init()
75 clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6); _mx21_clocks_init()
76 clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6); _mx21_clocks_init()
77 clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6); _mx21_clocks_init()
79 clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); _mx21_clocks_init()
80 clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); _mx21_clocks_init()
81 clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); _mx21_clocks_init()
82 clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); _mx21_clocks_init()
83 clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); _mx21_clocks_init()
84 clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); _mx21_clocks_init()
85 clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); _mx21_clocks_init()
86 clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); _mx21_clocks_init()
87 clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); _mx21_clocks_init()
88 clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); _mx21_clocks_init()
89 clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); _mx21_clocks_init()
90 clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); _mx21_clocks_init()
91 clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); _mx21_clocks_init()
92 clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); _mx21_clocks_init()
93 clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); _mx21_clocks_init()
94 clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16); _mx21_clocks_init()
95 clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17); _mx21_clocks_init()
96 clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); _mx21_clocks_init()
97 clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); _mx21_clocks_init()
98 clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); _mx21_clocks_init()
99 clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); _mx21_clocks_init()
100 clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23); _mx21_clocks_init()
101 clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); _mx21_clocks_init()
102 clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25); _mx21_clocks_init()
103 clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); _mx21_clocks_init()
104 clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); _mx21_clocks_init()
105 clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); _mx21_clocks_init()
106 clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); _mx21_clocks_init()
107 clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); _mx21_clocks_init()
109 clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); _mx21_clocks_init()
110 clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); _mx21_clocks_init()
111 clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); _mx21_clocks_init()
112 clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); _mx21_clocks_init()
113 clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); _mx21_clocks_init()
114 clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); _mx21_clocks_init()
115 clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); _mx21_clocks_init()
116 clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); _mx21_clocks_init()
117 clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); _mx21_clocks_init()
119 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx21_clocks_init()
128 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0"); mx21_clocks_init()
129 clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx21_clocks_init()
130 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1"); mx21_clocks_init()
131 clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx21_clocks_init()
132 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2"); mx21_clocks_init()
133 clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx21_clocks_init()
134 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3"); mx21_clocks_init()
135 clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx21_clocks_init()
136 clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); mx21_clocks_init()
137 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0"); mx21_clocks_init()
138 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0"); mx21_clocks_init()
139 clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); mx21_clocks_init()
140 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1"); mx21_clocks_init()
141 clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); mx21_clocks_init()
142 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2"); mx21_clocks_init()
143 clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); mx21_clocks_init()
144 clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0"); mx21_clocks_init()
145 clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx21_clocks_init()
146 clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0"); mx21_clocks_init()
147 clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0"); mx21_clocks_init()
148 clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0"); mx21_clocks_init()
149 clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0"); mx21_clocks_init()
150 clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma"); mx21_clocks_init()
151 clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); mx21_clocks_init()
152 clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0"); mx21_clocks_init()
153 clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); mx21_clocks_init()
154 clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); mx21_clocks_init()
167 clk_data.clks = clk; mx21_clocks_init_dt()
168 clk_data.clk_num = ARRAY_SIZE(clk); mx21_clocks_init_dt()
|
| H A D | clk-imx31.c | 19 #include <linux/clk.h>
25 #include "clk.h"
48 static struct clk *clk[clk_max]; variable in typeref:struct:clk
56 clk[dummy] = imx_clk_fixed("dummy", 0); mx31_clocks_init()
57 clk[ckih] = imx_clk_fixed("ckih", fref); mx31_clocks_init()
58 clk[ckil] = imx_clk_fixed("ckil", 32768); mx31_clocks_init()
59 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); mx31_clocks_init()
60 clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL); mx31_clocks_init()
61 clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL); mx31_clocks_init()
62 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); mx31_clocks_init()
63 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); mx31_clocks_init()
64 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); mx31_clocks_init()
65 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); mx31_clocks_init()
66 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); mx31_clocks_init()
67 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); mx31_clocks_init()
68 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); mx31_clocks_init()
69 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); mx31_clocks_init()
70 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); mx31_clocks_init()
71 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); mx31_clocks_init()
72 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); mx31_clocks_init()
73 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); mx31_clocks_init()
74 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); mx31_clocks_init()
75 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); mx31_clocks_init()
76 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); mx31_clocks_init()
77 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); mx31_clocks_init()
78 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); mx31_clocks_init()
79 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); mx31_clocks_init()
80 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); mx31_clocks_init()
81 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); mx31_clocks_init()
82 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); mx31_clocks_init()
83 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); mx31_clocks_init()
84 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); mx31_clocks_init()
85 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); mx31_clocks_init()
86 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); mx31_clocks_init()
87 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); mx31_clocks_init()
88 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); mx31_clocks_init()
89 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); mx31_clocks_init()
90 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); mx31_clocks_init()
91 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); mx31_clocks_init()
92 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); mx31_clocks_init()
93 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); mx31_clocks_init()
94 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); mx31_clocks_init()
95 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); mx31_clocks_init()
96 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); mx31_clocks_init()
97 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); mx31_clocks_init()
98 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); mx31_clocks_init()
99 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); mx31_clocks_init()
100 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); mx31_clocks_init()
101 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); mx31_clocks_init()
102 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); mx31_clocks_init()
103 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); mx31_clocks_init()
104 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); mx31_clocks_init()
105 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); mx31_clocks_init()
106 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); mx31_clocks_init()
107 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); mx31_clocks_init()
108 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); mx31_clocks_init()
109 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); mx31_clocks_init()
110 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); mx31_clocks_init()
111 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); mx31_clocks_init()
112 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); mx31_clocks_init()
113 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); mx31_clocks_init()
114 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); mx31_clocks_init()
116 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx31_clocks_init()
121 clk_data.clks = clk; mx31_clocks_init()
122 clk_data.clk_num = ARRAY_SIZE(clk); mx31_clocks_init()
126 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); mx31_clocks_init()
127 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); mx31_clocks_init()
128 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); mx31_clocks_init()
129 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); mx31_clocks_init()
130 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); mx31_clocks_init()
131 clk_register_clkdev(clk[pwm_gate], "pwm", NULL); mx31_clocks_init()
132 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); mx31_clocks_init()
133 clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc"); mx31_clocks_init()
134 clk_register_clkdev(clk[epit1_gate], "epit", NULL); mx31_clocks_init()
135 clk_register_clkdev(clk[epit2_gate], "epit", NULL); mx31_clocks_init()
136 clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); mx31_clocks_init()
137 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); mx31_clocks_init()
138 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); mx31_clocks_init()
139 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); mx31_clocks_init()
140 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); mx31_clocks_init()
141 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); mx31_clocks_init()
142 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); mx31_clocks_init()
143 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); mx31_clocks_init()
144 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); mx31_clocks_init()
145 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); mx31_clocks_init()
146 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); mx31_clocks_init()
147 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); mx31_clocks_init()
148 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); mx31_clocks_init()
149 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); mx31_clocks_init()
150 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); mx31_clocks_init()
151 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); mx31_clocks_init()
152 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); mx31_clocks_init()
154 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); mx31_clocks_init()
155 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx31_clocks_init()
156 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); mx31_clocks_init()
157 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx31_clocks_init()
158 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); mx31_clocks_init()
159 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx31_clocks_init()
160 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); mx31_clocks_init()
161 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); mx31_clocks_init()
162 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); mx31_clocks_init()
163 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); mx31_clocks_init()
164 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); mx31_clocks_init()
165 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); mx31_clocks_init()
166 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); mx31_clocks_init()
167 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); mx31_clocks_init()
168 clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); mx31_clocks_init()
169 clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); mx31_clocks_init()
170 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); mx31_clocks_init()
171 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); mx31_clocks_init()
172 clk_register_clkdev(clk[firi_gate], "firi", NULL); mx31_clocks_init()
173 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); mx31_clocks_init()
174 clk_register_clkdev(clk[rtic_gate], "rtic", NULL); mx31_clocks_init()
175 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); mx31_clocks_init()
176 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); mx31_clocks_init()
177 clk_register_clkdev(clk[iim_gate], "iim", NULL); mx31_clocks_init()
179 clk_set_parent(clk[csi], clk[upll]); mx31_clocks_init()
180 clk_prepare_enable(clk[emi_gate]); mx31_clocks_init()
181 clk_prepare_enable(clk[iim_gate]); mx31_clocks_init()
183 clk_disable_unprepare(clk[iim_gate]); mx31_clocks_init()
|
| H A D | clk-vf610.c | 12 #include <linux/clk.h>
15 #include "clk.h"
115 static struct clk *clk[VF610_CLK_END]; variable in typeref:struct:clk
123 static struct clk * __init vf610_get_fixed_clock( vf610_get_fixed_clock()
126 struct clk *clk = of_clk_get_by_name(ccm_node, name); vf610_get_fixed_clock() local
129 if (IS_ERR(clk)) vf610_get_fixed_clock()
130 clk = imx_obtain_fixed_clock(name, 0); vf610_get_fixed_clock()
131 return clk; vf610_get_fixed_clock()
139 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); vf610_clocks_init()
140 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); vf610_clocks_init()
141 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); vf610_clocks_init()
142 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); vf610_clocks_init()
144 clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc"); vf610_clocks_init()
145 clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc"); vf610_clocks_init()
146 clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext"); vf610_clocks_init()
147 clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext"); vf610_clocks_init()
150 clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1"); vf610_clocks_init()
152 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); vf610_clocks_init()
162 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); vf610_clocks_init()
163 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); vf610_clocks_init()
165 clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
166 clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
167 clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
168 clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
169 clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
170 clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
171 clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
173 clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); vf610_clocks_init()
174 clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); vf610_clocks_init()
175 clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2); vf610_clocks_init()
176 clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); vf610_clocks_init()
177 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); vf610_clocks_init()
178 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); vf610_clocks_init()
179 clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2); vf610_clocks_init()
181 clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
182 clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
183 clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
184 clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
185 clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
186 clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
187 clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
190 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); vf610_clocks_init()
191 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); vf610_clocks_init()
192 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); vf610_clocks_init()
193 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); vf610_clocks_init()
194 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); vf610_clocks_init()
195 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); vf610_clocks_init()
196 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); vf610_clocks_init()
198 clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13); vf610_clocks_init()
199 clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13); vf610_clocks_init()
200 clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13); vf610_clocks_init()
201 clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13); vf610_clocks_init()
202 clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13); vf610_clocks_init()
203 clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13); vf610_clocks_init()
204 clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13); vf610_clocks_init()
206 clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); vf610_clocks_init()
208 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0); vf610_clocks_init()
209 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1); vf610_clocks_init()
210 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2); vf610_clocks_init()
211 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3); vf610_clocks_init()
213 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0); vf610_clocks_init()
214 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1); vf610_clocks_init()
215 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2); vf610_clocks_init()
216 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3); vf610_clocks_init()
218 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0); vf610_clocks_init()
219 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1); vf610_clocks_init()
220 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2); vf610_clocks_init()
221 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3); vf610_clocks_init()
223 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); vf610_clocks_init()
224 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); vf610_clocks_init()
225 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); vf610_clocks_init()
226 clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); vf610_clocks_init()
227 clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3); vf610_clocks_init()
228 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); vf610_clocks_init()
229 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); vf610_clocks_init()
231 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1); vf610_clocks_init()
232 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); vf610_clocks_init()
233 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1); vf610_clocks_init()
235 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6); vf610_clocks_init()
236 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6); vf610_clocks_init()
238 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); vf610_clocks_init()
239 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); vf610_clocks_init()
241 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); vf610_clocks_init()
242 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); vf610_clocks_init()
243 clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2); vf610_clocks_init()
244 clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); vf610_clocks_init()
245 clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); vf610_clocks_init()
246 clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4)); vf610_clocks_init()
248 clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4); vf610_clocks_init()
249 clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12); vf610_clocks_init()
250 clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2); vf610_clocks_init()
251 clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); vf610_clocks_init()
252 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); vf610_clocks_init()
253 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); vf610_clocks_init()
255 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10); vf610_clocks_init()
256 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20); vf610_clocks_init()
257 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); vf610_clocks_init()
258 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); vf610_clocks_init()
259 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); vf610_clocks_init()
260 clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); vf610_clocks_init()
261 clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0)); vf610_clocks_init()
262 clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1)); vf610_clocks_init()
264 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); vf610_clocks_init()
266 clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); vf610_clocks_init()
267 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); vf610_clocks_init()
268 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); vf610_clocks_init()
269 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); vf610_clocks_init()
270 clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9)); vf610_clocks_init()
271 clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10)); vf610_clocks_init()
273 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); vf610_clocks_init()
274 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); vf610_clocks_init()
276 clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); vf610_clocks_init()
277 clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); vf610_clocks_init()
278 clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); vf610_clocks_init()
279 clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); vf610_clocks_init()
281 clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); vf610_clocks_init()
283 clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); vf610_clocks_init()
284 clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28); vf610_clocks_init()
285 clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4); vf610_clocks_init()
286 clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); vf610_clocks_init()
288 clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4); vf610_clocks_init()
289 clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29); vf610_clocks_init()
290 clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4); vf610_clocks_init()
291 clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); vf610_clocks_init()
299 clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); vf610_clocks_init()
300 clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); vf610_clocks_init()
301 clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25); vf610_clocks_init()
302 clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); vf610_clocks_init()
303 clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); vf610_clocks_init()
304 clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26); vf610_clocks_init()
305 clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); vf610_clocks_init()
306 clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); vf610_clocks_init()
307 clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27); vf610_clocks_init()
308 clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); vf610_clocks_init()
309 clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); vf610_clocks_init()
310 clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28); vf610_clocks_init()
313 clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); vf610_clocks_init()
314 clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); vf610_clocks_init()
315 clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); vf610_clocks_init()
316 clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); vf610_clocks_init()
318 clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); vf610_clocks_init()
319 clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); vf610_clocks_init()
320 clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); vf610_clocks_init()
321 clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); vf610_clocks_init()
322 clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); vf610_clocks_init()
323 clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); vf610_clocks_init()
324 clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); vf610_clocks_init()
325 clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); vf610_clocks_init()
327 clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); vf610_clocks_init()
328 clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); vf610_clocks_init()
329 clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); vf610_clocks_init()
330 clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); vf610_clocks_init()
332 clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); vf610_clocks_init()
333 clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); vf610_clocks_init()
334 clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); vf610_clocks_init()
335 clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); vf610_clocks_init()
337 clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); vf610_clocks_init()
338 clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); vf610_clocks_init()
339 clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); vf610_clocks_init()
340 clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); vf610_clocks_init()
342 clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); vf610_clocks_init()
343 clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); vf610_clocks_init()
344 clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); vf610_clocks_init()
345 clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); vf610_clocks_init()
347 clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); vf610_clocks_init()
348 clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); vf610_clocks_init()
349 clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); vf610_clocks_init()
350 clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); vf610_clocks_init()
352 clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); vf610_clocks_init()
353 clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9); vf610_clocks_init()
354 clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3); vf610_clocks_init()
355 clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); vf610_clocks_init()
356 clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); vf610_clocks_init()
358 clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2); vf610_clocks_init()
359 clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10); vf610_clocks_init()
360 clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15)); vf610_clocks_init()
362 clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3); vf610_clocks_init()
363 clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22); vf610_clocks_init()
364 clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2); vf610_clocks_init()
365 clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); vf610_clocks_init()
366 clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); vf610_clocks_init()
368 clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); vf610_clocks_init()
369 clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); vf610_clocks_init()
370 clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); vf610_clocks_init()
371 clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); vf610_clocks_init()
373 clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); vf610_clocks_init()
375 clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11); vf610_clocks_init()
376 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0)); vf610_clocks_init()
377 clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12); vf610_clocks_init()
378 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4)); vf610_clocks_init()
380 clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); vf610_clocks_init()
381 clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); vf610_clocks_init()
382 clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); vf610_clocks_init()
383 clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); vf610_clocks_init()
385 clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); vf610_clocks_init()
387 imx_check_clocks(clk, ARRAY_SIZE(clk)); vf610_clocks_init()
389 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); vf610_clocks_init()
390 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); vf610_clocks_init()
391 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); vf610_clocks_init()
392 clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); vf610_clocks_init()
394 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); vf610_clocks_init()
395 clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); vf610_clocks_init()
396 clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); vf610_clocks_init()
397 clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); vf610_clocks_init()
399 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
400 clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
401 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
402 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
405 clk_prepare_enable(clk[clks_init_on[i]]); vf610_clocks_init()
408 clk_data.clks = clk; vf610_clocks_init()
409 clk_data.clk_num = ARRAY_SIZE(clk); vf610_clocks_init()
|
| H A D | clk-imx35.c | 11 #include <linux/clk.h>
18 #include "clk.h"
70 static struct clk *clk[clk_max]; variable in typeref:struct:clk
83 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); mx35_clocks_init()
91 clk[ckih] = imx_clk_fixed("ckih", 24000000); mx35_clocks_init()
92 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); mx35_clocks_init()
93 clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); mx35_clocks_init()
95 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); mx35_clocks_init()
98 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); mx35_clocks_init()
100 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); mx35_clocks_init()
102 if (clk_get_rate(clk[arm]) > 400000000) mx35_clocks_init()
109 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); mx35_clocks_init()
113 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); mx35_clocks_init()
115 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); mx35_clocks_init()
116 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); mx35_clocks_init()
118 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); mx35_clocks_init()
119 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); mx35_clocks_init()
120 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); mx35_clocks_init()
122 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); mx35_clocks_init()
123 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); mx35_clocks_init()
125 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); mx35_clocks_init()
126 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); mx35_clocks_init()
127 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); mx35_clocks_init()
128 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); mx35_clocks_init()
130 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); mx35_clocks_init()
131 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ mx35_clocks_init()
132 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); mx35_clocks_init()
134 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); mx35_clocks_init()
135 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); mx35_clocks_init()
136 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); mx35_clocks_init()
137 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); mx35_clocks_init()
138 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); mx35_clocks_init()
140 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); mx35_clocks_init()
141 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); mx35_clocks_init()
143 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); mx35_clocks_init()
145 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); mx35_clocks_init()
146 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); mx35_clocks_init()
148 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); mx35_clocks_init()
149 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); mx35_clocks_init()
150 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); mx35_clocks_init()
151 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); mx35_clocks_init()
152 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); mx35_clocks_init()
153 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); mx35_clocks_init()
154 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); mx35_clocks_init()
155 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); mx35_clocks_init()
156 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); mx35_clocks_init()
157 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); mx35_clocks_init()
158 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); mx35_clocks_init()
159 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); mx35_clocks_init()
160 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); mx35_clocks_init()
161 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); mx35_clocks_init()
162 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); mx35_clocks_init()
163 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); mx35_clocks_init()
165 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); mx35_clocks_init()
166 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); mx35_clocks_init()
167 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); mx35_clocks_init()
168 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); mx35_clocks_init()
169 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); mx35_clocks_init()
170 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); mx35_clocks_init()
171 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); mx35_clocks_init()
172 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); mx35_clocks_init()
173 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); mx35_clocks_init()
174 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); mx35_clocks_init()
175 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); mx35_clocks_init()
176 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); mx35_clocks_init()
177 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); mx35_clocks_init()
178 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); mx35_clocks_init()
179 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); mx35_clocks_init()
180 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); mx35_clocks_init()
182 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); mx35_clocks_init()
183 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); mx35_clocks_init()
184 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); mx35_clocks_init()
185 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); mx35_clocks_init()
186 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); mx35_clocks_init()
187 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); mx35_clocks_init()
188 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); mx35_clocks_init()
189 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); mx35_clocks_init()
190 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); mx35_clocks_init()
191 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); mx35_clocks_init()
192 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); mx35_clocks_init()
193 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); mx35_clocks_init()
194 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); mx35_clocks_init()
195 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); mx35_clocks_init()
196 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); mx35_clocks_init()
198 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); mx35_clocks_init()
199 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); mx35_clocks_init()
200 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); mx35_clocks_init()
202 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx35_clocks_init()
204 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); mx35_clocks_init()
205 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); mx35_clocks_init()
206 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); mx35_clocks_init()
207 clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); mx35_clocks_init()
208 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); mx35_clocks_init()
209 clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); mx35_clocks_init()
210 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); mx35_clocks_init()
211 clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); mx35_clocks_init()
212 clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); mx35_clocks_init()
213 clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
214 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
215 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
216 clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
217 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
218 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
219 clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
220 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
221 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
223 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); mx35_clocks_init()
224 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); mx35_clocks_init()
225 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); mx35_clocks_init()
226 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); mx35_clocks_init()
227 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); mx35_clocks_init()
228 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); mx35_clocks_init()
229 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); mx35_clocks_init()
230 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); mx35_clocks_init()
231 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); mx35_clocks_init()
232 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); mx35_clocks_init()
233 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); mx35_clocks_init()
234 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); mx35_clocks_init()
235 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); mx35_clocks_init()
237 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); mx35_clocks_init()
238 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx35_clocks_init()
239 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); mx35_clocks_init()
240 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx35_clocks_init()
241 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); mx35_clocks_init()
242 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx35_clocks_init()
243 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); mx35_clocks_init()
244 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); mx35_clocks_init()
245 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); mx35_clocks_init()
246 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); mx35_clocks_init()
247 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); mx35_clocks_init()
248 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); mx35_clocks_init()
249 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); mx35_clocks_init()
250 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); mx35_clocks_init()
251 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); mx35_clocks_init()
252 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); mx35_clocks_init()
253 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); mx35_clocks_init()
254 clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); mx35_clocks_init()
255 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); mx35_clocks_init()
256 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); mx35_clocks_init()
257 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); mx35_clocks_init()
258 clk_register_clkdev(clk[admux_gate], "audmux", NULL); mx35_clocks_init()
260 clk_prepare_enable(clk[spba_gate]); mx35_clocks_init()
261 clk_prepare_enable(clk[gpio1_gate]); mx35_clocks_init()
262 clk_prepare_enable(clk[gpio2_gate]); mx35_clocks_init()
263 clk_prepare_enable(clk[gpio3_gate]); mx35_clocks_init()
264 clk_prepare_enable(clk[iim_gate]); mx35_clocks_init()
265 clk_prepare_enable(clk[emi_gate]); mx35_clocks_init()
266 clk_prepare_enable(clk[max_gate]); mx35_clocks_init()
267 clk_prepare_enable(clk[iomuxc_gate]); mx35_clocks_init()
271 * before conversion to common clk also enabled UART1 (which isn't mx35_clocks_init()
275 clk_prepare_enable(clk[scc_gate]); mx35_clocks_init()
290 clk_data.clks = clk; mx35_clocks_init_dt()
291 clk_data.clk_num = ARRAY_SIZE(clk); mx35_clocks_init_dt()
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| H A D | clk-imx1.c | 18 #include <linux/clk.h>
20 #include <linux/clk-provider.h>
27 #include "clk.h"
35 static struct clk *clk[IMX1_CLK_MAX]; variable in typeref:struct:clk
47 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); _mx1_clocks_init()
48 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); _mx1_clocks_init()
49 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); _mx1_clocks_init()
50 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); _mx1_clocks_init()
51 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); _mx1_clocks_init()
52 clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)); _mx1_clocks_init()
53 clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); _mx1_clocks_init()
54 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); _mx1_clocks_init()
55 clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); _mx1_clocks_init()
56 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); _mx1_clocks_init()
57 clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); _mx1_clocks_init()
58 clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); _mx1_clocks_init()
59 clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); _mx1_clocks_init()
60 clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3); _mx1_clocks_init()
61 clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4); _mx1_clocks_init()
62 clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4); _mx1_clocks_init()
63 clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7); _mx1_clocks_init()
64 clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); _mx1_clocks_init()
65 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); _mx1_clocks_init()
66 clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); _mx1_clocks_init()
67 clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); _mx1_clocks_init()
68 clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); _mx1_clocks_init()
69 clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); _mx1_clocks_init()
70 clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); _mx1_clocks_init()
71 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); _mx1_clocks_init()
73 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx1_clocks_init()
82 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0"); mx1_clocks_init()
83 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0"); mx1_clocks_init()
84 clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma"); mx1_clocks_init()
85 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma"); mx1_clocks_init()
86 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0"); mx1_clocks_init()
87 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0"); mx1_clocks_init()
88 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1"); mx1_clocks_init()
89 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1"); mx1_clocks_init()
90 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2"); mx1_clocks_init()
91 clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2"); mx1_clocks_init()
92 clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0"); mx1_clocks_init()
93 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0"); mx1_clocks_init()
94 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0"); mx1_clocks_init()
95 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1"); mx1_clocks_init()
96 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1"); mx1_clocks_init()
97 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0"); mx1_clocks_init()
98 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); mx1_clocks_init()
99 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0"); mx1_clocks_init()
113 clk_data.clks = clk; mx1_clocks_init_dt()
114 clk_data.clk_num = ARRAY_SIZE(clk); mx1_clocks_init_dt()
|
| H A D | clk-imx6q.c | 15 #include <linux/clk.h>
24 #include "clk.h"
85 static struct clk *clk[IMX6QDL_CLK_END]; variable in typeref:struct:clk
131 clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); imx6q_clocks_init()
132 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); imx6q_clocks_init()
133 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); imx6q_clocks_init()
134 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); imx6q_clocks_init()
136 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); imx6q_clocks_init()
137 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); imx6q_clocks_init()
151 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
152 clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
153 clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
154 clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
155 clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
156 clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
157 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
160 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); imx6q_clocks_init()
161 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); imx6q_clocks_init()
162 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); imx6q_clocks_init()
163 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); imx6q_clocks_init()
164 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); imx6q_clocks_init()
165 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); imx6q_clocks_init()
166 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); imx6q_clocks_init()
168 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
169 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
170 clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
171 clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
172 clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
173 clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
174 clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
177 clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); imx6q_clocks_init()
178 clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); imx6q_clocks_init()
179 clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); imx6q_clocks_init()
180 clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); imx6q_clocks_init()
181 clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); imx6q_clocks_init()
182 clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); imx6q_clocks_init()
183 clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); imx6q_clocks_init()
185 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); imx6q_clocks_init()
186 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); imx6q_clocks_init()
187 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); imx6q_clocks_init()
188 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); imx6q_clocks_init()
189 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); imx6q_clocks_init()
190 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); imx6q_clocks_init()
191 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); imx6q_clocks_init()
197 * the clk framework may need to enable/disable usbphy's parent imx6q_clocks_init()
199 clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); imx6q_clocks_init()
200 clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); imx6q_clocks_init()
206 clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); imx6q_clocks_init()
207 clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); imx6q_clocks_init()
209 clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); imx6q_clocks_init()
210 clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); imx6q_clocks_init()
212 clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); imx6q_clocks_init()
213 clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); imx6q_clocks_init()
215 clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, imx6q_clocks_init()
219 clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6q_clocks_init()
220 clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6q_clocks_init()
228 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); imx6q_clocks_init()
229 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); imx6q_clocks_init()
231 clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); imx6q_clocks_init()
232 clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); imx6q_clocks_init()
235 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); imx6q_clocks_init()
236 clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); imx6q_clocks_init()
237 clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); imx6q_clocks_init()
238 clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); imx6q_clocks_init()
239 clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); imx6q_clocks_init()
240 clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); imx6q_clocks_init()
241 clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); imx6q_clocks_init()
244 clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); imx6q_clocks_init()
245 clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); imx6q_clocks_init()
246 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); imx6q_clocks_init()
247 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); imx6q_clocks_init()
248 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); imx6q_clocks_init()
249 clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); imx6q_clocks_init()
250 clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); imx6q_clocks_init()
252 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); imx6q_clocks_init()
253 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); imx6q_clocks_init()
256 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
257 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6q_clocks_init()
258 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
259 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6q_clocks_init()
268 clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); imx6q_clocks_init()
269 clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); imx6q_clocks_init()
270 clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6q_clocks_init()
271 clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6q_clocks_init()
272 clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); imx6q_clocks_init()
273 clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); imx6q_clocks_init()
274 clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); imx6q_clocks_init()
275 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
276 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
277 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
279 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6q_clocks_init()
280 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6q_clocks_init()
282 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); imx6q_clocks_init()
283 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); imx6q_clocks_init()
284 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); imx6q_clocks_init()
285 clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); imx6q_clocks_init()
286 clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); imx6q_clocks_init()
287 clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
288 clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
289 clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
290 clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
291 clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
292 clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
293 clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
294 clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
295 clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
296 clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
297 clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); imx6q_clocks_init()
298 clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); imx6q_clocks_init()
299 clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
300 clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
301 clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
302 clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
303 clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
304 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
305 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
306 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); imx6q_clocks_init()
307 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); imx6q_clocks_init()
308 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); imx6q_clocks_init()
309 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); imx6q_clocks_init()
310 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); imx6q_clocks_init()
311 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); imx6q_clocks_init()
312 clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); imx6q_clocks_init()
313 clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); imx6q_clocks_init()
316 clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); imx6q_clocks_init()
317 clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); imx6q_clocks_init()
320 clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); imx6q_clocks_init()
321 clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); imx6q_clocks_init()
322 clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6q_clocks_init()
323 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); imx6q_clocks_init()
324 clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); imx6q_clocks_init()
325 clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); imx6q_clocks_init()
326 clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); imx6q_clocks_init()
327 clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); imx6q_clocks_init()
328 clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); imx6q_clocks_init()
329 clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); imx6q_clocks_init()
330 clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); imx6q_clocks_init()
331 clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); imx6q_clocks_init()
332 clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); imx6q_clocks_init()
333 clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); imx6q_clocks_init()
334 clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); imx6q_clocks_init()
335 clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); imx6q_clocks_init()
336 clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); imx6q_clocks_init()
337 clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); imx6q_clocks_init()
338 clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); imx6q_clocks_init()
339 clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); imx6q_clocks_init()
340 clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); imx6q_clocks_init()
341 clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); imx6q_clocks_init()
342 clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); imx6q_clocks_init()
343 clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); imx6q_clocks_init()
344 clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); imx6q_clocks_init()
345 clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); imx6q_clocks_init()
346 clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); imx6q_clocks_init()
347 clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); imx6q_clocks_init()
348 clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); imx6q_clocks_init()
349 clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); imx6q_clocks_init()
350 clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); imx6q_clocks_init()
351 clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); imx6q_clocks_init()
352 clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); imx6q_clocks_init()
353 clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); imx6q_clocks_init()
354 clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); imx6q_clocks_init()
355 clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); imx6q_clocks_init()
356 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); imx6q_clocks_init()
357 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); imx6q_clocks_init()
358 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); imx6q_clocks_init()
359 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); imx6q_clocks_init()
360 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); imx6q_clocks_init()
361 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); imx6q_clocks_init()
362 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); imx6q_clocks_init()
363 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); imx6q_clocks_init()
366 clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); imx6q_clocks_init()
367 clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); imx6q_clocks_init()
368 clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); imx6q_clocks_init()
369 clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); imx6q_clocks_init()
370 clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); imx6q_clocks_init()
373 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); imx6q_clocks_init()
374 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
375 clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
376 clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
377 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6q_clocks_init()
378 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); imx6q_clocks_init()
379 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6q_clocks_init()
380 clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); imx6q_clocks_init()
381 clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); imx6q_clocks_init()
382 clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); imx6q_clocks_init()
383 clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); imx6q_clocks_init()
384 clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); imx6q_clocks_init()
386 clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); imx6q_clocks_init()
388 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); imx6q_clocks_init()
389 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); imx6q_clocks_init()
390 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
391 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
392 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
393 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); imx6q_clocks_init()
394 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); imx6q_clocks_init()
400 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); imx6q_clocks_init()
402 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); imx6q_clocks_init()
403 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); imx6q_clocks_init()
404 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); imx6q_clocks_init()
405 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); imx6q_clocks_init()
406 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); imx6q_clocks_init()
407 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); imx6q_clocks_init()
408 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); imx6q_clocks_init()
409 clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); imx6q_clocks_init()
410 clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); imx6q_clocks_init()
411 clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); imx6q_clocks_init()
412 clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); imx6q_clocks_init()
413 clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); imx6q_clocks_init()
414 clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); imx6q_clocks_init()
415 clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); imx6q_clocks_init()
416 clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); imx6q_clocks_init()
417 clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); imx6q_clocks_init()
418 clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); imx6q_clocks_init()
419 clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); imx6q_clocks_init()
420 clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
421 clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
422 clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
428 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); imx6q_clocks_init()
430 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); imx6q_clocks_init()
431 clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); imx6q_clocks_init()
432 clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); imx6q_clocks_init()
433 clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); imx6q_clocks_init()
434 clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); imx6q_clocks_init()
435 clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); imx6q_clocks_init()
436 clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); imx6q_clocks_init()
437 clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); imx6q_clocks_init()
438 clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); imx6q_clocks_init()
439 clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); imx6q_clocks_init()
440 clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); imx6q_clocks_init()
441 clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); imx6q_clocks_init()
442 clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); imx6q_clocks_init()
443 clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); imx6q_clocks_init()
444 clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); imx6q_clocks_init()
445 clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); imx6q_clocks_init()
446 clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); imx6q_clocks_init()
447 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); imx6q_clocks_init()
448 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6q_clocks_init()
449 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); imx6q_clocks_init()
450 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
451 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
452 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
453 clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
454 clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
455 clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
456 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); imx6q_clocks_init()
457 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); imx6q_clocks_init()
458 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6q_clocks_init()
459 clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); imx6q_clocks_init()
460 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); imx6q_clocks_init()
461 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); imx6q_clocks_init()
462 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); imx6q_clocks_init()
463 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); imx6q_clocks_init()
464 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); imx6q_clocks_init()
465 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); imx6q_clocks_init()
466 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); imx6q_clocks_init()
467 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); imx6q_clocks_init()
474 clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; imx6q_clocks_init()
476 imx_check_clocks(clk, ARRAY_SIZE(clk)); imx6q_clocks_init()
478 clk_data.clks = clk; imx6q_clocks_init()
479 clk_data.clk_num = ARRAY_SIZE(clk); imx6q_clocks_init()
482 clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); imx6q_clocks_init()
486 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
487 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
490 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
491 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
492 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
493 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
494 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); imx6q_clocks_init()
495 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); imx6q_clocks_init()
496 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); imx6q_clocks_init()
497 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); imx6q_clocks_init()
504 clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); imx6q_clocks_init()
507 clk_prepare_enable(clk[clks_init_on[i]]); imx6q_clocks_init()
510 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); imx6q_clocks_init()
511 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); imx6q_clocks_init()
518 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); imx6q_clocks_init()
520 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); imx6q_clocks_init()
525 clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); imx6q_clocks_init()
529 clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); imx6q_clocks_init()
|
| H A D | clk-imx25.c | 22 #include <linux/clk.h>
30 #include "clk.h"
89 static struct clk *clk[clk_max]; variable in typeref:struct:clk
96 clk[dummy] = imx_clk_fixed("dummy", 0); __mx25_clocks_init()
97 clk[osc] = imx_clk_fixed("osc", osc_rate); __mx25_clocks_init()
98 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); __mx25_clocks_init()
99 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); __mx25_clocks_init()
100 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); __mx25_clocks_init()
101 clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); __mx25_clocks_init()
102 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); __mx25_clocks_init()
103 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); __mx25_clocks_init()
104 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); __mx25_clocks_init()
105 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); __mx25_clocks_init()
106 clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
107 clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
108 clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
109 clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
110 clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
111 clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
112 clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
113 clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
114 clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
115 clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
116 clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
117 clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
118 clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
119 clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
120 clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
121 clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
122 clk[cko_div] = imx_clk_divider("cko_div", "cko_sel", ccm(CCM_MCR), 24, 6); __mx25_clocks_init()
123 clk[cko_sel] = imx_clk_mux("cko_sel", ccm(CCM_MCR), 20, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks)); __mx25_clocks_init()
124 clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30); __mx25_clocks_init()
125 clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6); __mx25_clocks_init()
126 clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6); __mx25_clocks_init()
127 clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6); __mx25_clocks_init()
128 clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6); __mx25_clocks_init()
129 clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6); __mx25_clocks_init()
130 clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6); __mx25_clocks_init()
131 clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6); __mx25_clocks_init()
132 clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6); __mx25_clocks_init()
133 clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6); __mx25_clocks_init()
134 clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6); __mx25_clocks_init()
135 clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6); __mx25_clocks_init()
136 clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6); __mx25_clocks_init()
137 clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6); __mx25_clocks_init()
138 clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6); __mx25_clocks_init()
139 clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6); __mx25_clocks_init()
140 clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6); __mx25_clocks_init()
141 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0); __mx25_clocks_init()
142 clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1); __mx25_clocks_init()
143 clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2); __mx25_clocks_init()
144 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3); __mx25_clocks_init()
145 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); __mx25_clocks_init()
146 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); __mx25_clocks_init()
147 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); __mx25_clocks_init()
148 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); __mx25_clocks_init()
149 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); __mx25_clocks_init()
150 clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9); __mx25_clocks_init()
151 clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10); __mx25_clocks_init()
152 clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11); __mx25_clocks_init()
153 clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12); __mx25_clocks_init()
154 clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13); __mx25_clocks_init()
155 clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14); __mx25_clocks_init()
156 clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15); __mx25_clocks_init()
157 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); __mx25_clocks_init()
159 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); __mx25_clocks_init()
160 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); __mx25_clocks_init()
161 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); __mx25_clocks_init()
162 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); __mx25_clocks_init()
163 clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22); __mx25_clocks_init()
164 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23); __mx25_clocks_init()
165 clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24); __mx25_clocks_init()
166 clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25); __mx25_clocks_init()
167 clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26); __mx25_clocks_init()
168 clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27); __mx25_clocks_init()
169 clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28); __mx25_clocks_init()
172 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); __mx25_clocks_init()
173 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); __mx25_clocks_init()
174 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); __mx25_clocks_init()
175 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5); __mx25_clocks_init()
176 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); __mx25_clocks_init()
177 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); __mx25_clocks_init()
178 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); __mx25_clocks_init()
179 clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9); __mx25_clocks_init()
180 clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10); __mx25_clocks_init()
181 clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11); __mx25_clocks_init()
183 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); __mx25_clocks_init()
184 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); __mx25_clocks_init()
185 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); __mx25_clocks_init()
189 clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19); __mx25_clocks_init()
190 clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20); __mx25_clocks_init()
191 clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21); __mx25_clocks_init()
192 clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22); __mx25_clocks_init()
196 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); __mx25_clocks_init()
199 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); __mx25_clocks_init()
200 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); __mx25_clocks_init()
202 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); __mx25_clocks_init()
203 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0); __mx25_clocks_init()
204 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1); __mx25_clocks_init()
205 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2); __mx25_clocks_init()
206 clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3); __mx25_clocks_init()
208 clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5); __mx25_clocks_init()
209 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6); __mx25_clocks_init()
210 clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7); __mx25_clocks_init()
211 clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8); __mx25_clocks_init()
212 clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9); __mx25_clocks_init()
213 clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10); __mx25_clocks_init()
214 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11); __mx25_clocks_init()
215 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12); __mx25_clocks_init()
216 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13); __mx25_clocks_init()
217 clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14); __mx25_clocks_init()
218 clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15); __mx25_clocks_init()
219 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16); __mx25_clocks_init()
220 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17); __mx25_clocks_init()
221 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18); __mx25_clocks_init()
223 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); __mx25_clocks_init()
225 imx_check_clocks(clk, ARRAY_SIZE(clk)); __mx25_clocks_init()
227 clk_prepare_enable(clk[emi_ahb]); __mx25_clocks_init()
230 clk_set_parent(clk[per5_sel], clk[ahb]); __mx25_clocks_init()
236 clk_set_parent(clk[cko_sel], clk[ipg]); __mx25_clocks_init()
260 clk_data.clks = clk; mx25_clocks_init_dt()
261 clk_data.clk_num = ARRAY_SIZE(clk); mx25_clocks_init_dt()
|
| H A D | clk.c | 1 #include <linux/clk.h>
6 #include "clk.h"
10 void __init imx_check_clocks(struct clk *clks[], unsigned int count) imx_check_clocks()
16 pr_err("i.MX clk %u: register failed with %ld\n", imx_check_clocks()
20 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) imx_obtain_fixed_clock_from_dt()
23 struct clk *clk = ERR_PTR(-ENODEV); imx_obtain_fixed_clock_from_dt() local
34 clk = of_clk_get_from_provider(&phandle); imx_obtain_fixed_clock_from_dt()
37 return clk; imx_obtain_fixed_clock_from_dt()
40 struct clk * __init imx_obtain_fixed_clock( imx_obtain_fixed_clock()
43 struct clk *clk; imx_obtain_fixed_clock() local
45 clk = imx_obtain_fixed_clock_from_dt(name); imx_obtain_fixed_clock()
46 if (IS_ERR(clk)) imx_obtain_fixed_clock()
47 clk = imx_clk_fixed(name, rate); imx_obtain_fixed_clock()
48 return clk; imx_obtain_fixed_clock()
|
| H A D | Makefile | 3 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
4 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
6 obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
9 obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
11 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
12 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
15 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
17 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o \
19 clk-fixup-div.o clk-fixup-mux.o \
20 clk-gate-exclusive.o
90 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
91 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
92 obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
104 obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
|
| H A D | clk-cpu.c | 12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
18 struct clk *div;
19 struct clk *mux;
20 struct clk *pll;
21 struct clk *step;
77 struct clk *imx_clk_cpu(const char *name, const char *parent_name, imx_clk_cpu()
78 struct clk *div, struct clk *mux, struct clk *pll, imx_clk_cpu()
79 struct clk *step) imx_clk_cpu()
82 struct clk *clk; imx_clk_cpu() local
102 clk = clk_register(NULL, &cpu->hw); imx_clk_cpu()
103 if (IS_ERR(clk)) imx_clk_cpu()
106 return clk; imx_clk_cpu()
|
| H A D | clk.h | 5 #include <linux/clk-provider.h>
9 void imx_check_clocks(struct clk *clks[], unsigned int count);
13 struct clk *imx_clk_pllv1(const char *name, const char *parent,
16 struct clk *imx_clk_pllv2(const char *name, const char *parent,
28 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
31 struct clk *clk_register_gate2(struct device *dev, const char *name,
37 struct clk * imx_obtain_fixed_clock(
40 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
43 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, imx_clk_gate2()
50 static inline struct clk *imx_clk_gate2_shared(const char *name, imx_clk_gate2_shared()
58 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
61 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
65 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
69 struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
73 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
77 static inline struct clk *imx_clk_fixed(const char *name, int rate) imx_clk_fixed()
82 static inline struct clk *imx_clk_divider(const char *name, const char *parent, imx_clk_divider()
89 static inline struct clk *imx_clk_divider_flags(const char *name, imx_clk_divider_flags()
97 static inline struct clk *imx_clk_gate(const char *name, const char *parent, imx_clk_gate()
104 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, imx_clk_gate_dis()
111 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, imx_clk_mux()
119 static inline struct clk *imx_clk_mux_flags(const char *name, imx_clk_mux_flags()
128 static inline struct clk *imx_clk_fixed_factor(const char *name, imx_clk_fixed_factor()
135 struct clk *imx_clk_cpu(const char *name, const char *parent_name,
136 struct clk *div, struct clk *mux, struct clk *pll,
137 struct clk *step);
|
| H A D | clk-pllv1.c | 1 #include <linux/clk.h>
2 #include <linux/clk-provider.h>
8 #include "clk.h"
31 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
100 struct clk *imx_clk_pllv1(const char *name, const char *parent, imx_clk_pllv1()
104 struct clk *clk; imx_clk_pllv1() local
121 clk = clk_register(NULL, &pll->hw); imx_clk_pllv1()
122 if (IS_ERR(clk)) imx_clk_pllv1()
125 return clk; imx_clk_pllv1()
|
| /linux-4.1.27/drivers/clk/mmp/ |
| H A D | clk-mmp2.c | 21 #include "clk.h"
80 struct clk *clk; mmp2_clk_init() local
81 struct clk *vctcxo; mmp2_clk_init()
104 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); mmp2_clk_init()
105 clk_register_clkdev(clk, "clk32", NULL); mmp2_clk_init()
111 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, mmp2_clk_init()
113 clk_register_clkdev(clk, "pll1", NULL); mmp2_clk_init()
115 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT, mmp2_clk_init()
117 clk_register_clkdev(clk, "usb_pll", NULL); mmp2_clk_init()
119 clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, mmp2_clk_init()
121 clk_register_clkdev(clk, "pll2", NULL); mmp2_clk_init()
123 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", mmp2_clk_init()
125 clk_register_clkdev(clk, "pll1_2", NULL); mmp2_clk_init()
127 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", mmp2_clk_init()
129 clk_register_clkdev(clk, "pll1_4", NULL); mmp2_clk_init()
131 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", mmp2_clk_init()
133 clk_register_clkdev(clk, "pll1_8", NULL); mmp2_clk_init()
135 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", mmp2_clk_init()
137 clk_register_clkdev(clk, "pll1_16", NULL); mmp2_clk_init()
139 clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4", mmp2_clk_init()
141 clk_register_clkdev(clk, "pll1_20", NULL); mmp2_clk_init()
143 clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", mmp2_clk_init()
145 clk_register_clkdev(clk, "pll1_3", NULL); mmp2_clk_init()
147 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3", mmp2_clk_init()
149 clk_register_clkdev(clk, "pll1_6", NULL); mmp2_clk_init()
151 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", mmp2_clk_init()
153 clk_register_clkdev(clk, "pll1_12", NULL); mmp2_clk_init()
155 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", mmp2_clk_init()
157 clk_register_clkdev(clk, "pll2_2", NULL); mmp2_clk_init()
159 clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2", mmp2_clk_init()
161 clk_register_clkdev(clk, "pll2_4", NULL); mmp2_clk_init()
163 clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4", mmp2_clk_init()
165 clk_register_clkdev(clk, "pll2_8", NULL); mmp2_clk_init()
167 clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8", mmp2_clk_init()
169 clk_register_clkdev(clk, "pll2_16", NULL); mmp2_clk_init()
171 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", mmp2_clk_init()
173 clk_register_clkdev(clk, "pll2_3", NULL); mmp2_clk_init()
175 clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3", mmp2_clk_init()
177 clk_register_clkdev(clk, "pll2_6", NULL); mmp2_clk_init()
179 clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6", mmp2_clk_init()
181 clk_register_clkdev(clk, "pll2_12", NULL); mmp2_clk_init()
183 clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo", mmp2_clk_init()
185 clk_register_clkdev(clk, "vctcxo_2", NULL); mmp2_clk_init()
187 clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2", mmp2_clk_init()
189 clk_register_clkdev(clk, "vctcxo_4", NULL); mmp2_clk_init()
191 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, mmp2_clk_init()
195 clk_set_rate(clk, 14745600); mmp2_clk_init()
196 clk_register_clkdev(clk, "uart_pll", NULL); mmp2_clk_init()
198 clk = mmp_clk_register_apbc("twsi0", "vctcxo", mmp2_clk_init()
200 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); mmp2_clk_init()
202 clk = mmp_clk_register_apbc("twsi1", "vctcxo", mmp2_clk_init()
204 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); mmp2_clk_init()
206 clk = mmp_clk_register_apbc("twsi2", "vctcxo", mmp2_clk_init()
208 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); mmp2_clk_init()
210 clk = mmp_clk_register_apbc("twsi3", "vctcxo", mmp2_clk_init()
212 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); mmp2_clk_init()
214 clk = mmp_clk_register_apbc("twsi4", "vctcxo", mmp2_clk_init()
216 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); mmp2_clk_init()
218 clk = mmp_clk_register_apbc("twsi5", "vctcxo", mmp2_clk_init()
220 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); mmp2_clk_init()
222 clk = mmp_clk_register_apbc("gpio", "vctcxo", mmp2_clk_init()
224 clk_register_clkdev(clk, NULL, "mmp2-gpio"); mmp2_clk_init()
226 clk = mmp_clk_register_apbc("kpc", "clk32", mmp2_clk_init()
228 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); mmp2_clk_init()
230 clk = mmp_clk_register_apbc("rtc", "clk32", mmp2_clk_init()
232 clk_register_clkdev(clk, NULL, "mmp-rtc"); mmp2_clk_init()
234 clk = mmp_clk_register_apbc("pwm0", "vctcxo", mmp2_clk_init()
236 clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); mmp2_clk_init()
238 clk = mmp_clk_register_apbc("pwm1", "vctcxo", mmp2_clk_init()
240 clk_register_clkdev(clk, NULL, "mmp2-pwm.1"); mmp2_clk_init()
242 clk = mmp_clk_register_apbc("pwm2", "vctcxo", mmp2_clk_init()
244 clk_register_clkdev(clk, NULL, "mmp2-pwm.2"); mmp2_clk_init()
246 clk = mmp_clk_register_apbc("pwm3", "vctcxo", mmp2_clk_init()
248 clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); mmp2_clk_init()
250 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, mmp2_clk_init()
254 clk_set_parent(clk, vctcxo); mmp2_clk_init()
255 clk_register_clkdev(clk, "uart_mux.0", NULL); mmp2_clk_init()
257 clk = mmp_clk_register_apbc("uart0", "uart0_mux", mmp2_clk_init()
259 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); mmp2_clk_init()
261 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, mmp2_clk_init()
265 clk_set_parent(clk, vctcxo); mmp2_clk_init()
266 clk_register_clkdev(clk, "uart_mux.1", NULL); mmp2_clk_init()
268 clk = mmp_clk_register_apbc("uart1", "uart1_mux", mmp2_clk_init()
270 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); mmp2_clk_init()
272 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, mmp2_clk_init()
276 clk_set_parent(clk, vctcxo); mmp2_clk_init()
277 clk_register_clkdev(clk, "uart_mux.2", NULL); mmp2_clk_init()
279 clk = mmp_clk_register_apbc("uart2", "uart2_mux", mmp2_clk_init()
281 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); mmp2_clk_init()
283 clk = clk_register_mux(NULL, "uart3_mux", uart_parent, mmp2_clk_init()
287 clk_set_parent(clk, vctcxo); mmp2_clk_init()
288 clk_register_clkdev(clk, "uart_mux.3", NULL); mmp2_clk_init()
290 clk = mmp_clk_register_apbc("uart3", "uart3_mux", mmp2_clk_init()
292 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); mmp2_clk_init()
294 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, mmp2_clk_init()
298 clk_register_clkdev(clk, "uart_mux.0", NULL); mmp2_clk_init()
300 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", mmp2_clk_init()
302 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); mmp2_clk_init()
304 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, mmp2_clk_init()
308 clk_register_clkdev(clk, "ssp_mux.1", NULL); mmp2_clk_init()
310 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", mmp2_clk_init()
312 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); mmp2_clk_init()
314 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, mmp2_clk_init()
318 clk_register_clkdev(clk, "ssp_mux.2", NULL); mmp2_clk_init()
320 clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", mmp2_clk_init()
322 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); mmp2_clk_init()
324 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, mmp2_clk_init()
328 clk_register_clkdev(clk, "ssp_mux.3", NULL); mmp2_clk_init()
330 clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", mmp2_clk_init()
332 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); mmp2_clk_init()
334 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, mmp2_clk_init()
338 clk_register_clkdev(clk, "sdh_mux", NULL); mmp2_clk_init()
340 clk = clk_register_divider(NULL, "sdh_div", "sdh_mux", mmp2_clk_init()
343 clk_register_clkdev(clk, "sdh_div", NULL); mmp2_clk_init()
345 clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, mmp2_clk_init()
347 clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); mmp2_clk_init()
349 clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, mmp2_clk_init()
351 clk_register_clkdev(clk, NULL, "sdhci-pxav3.1"); mmp2_clk_init()
353 clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2, mmp2_clk_init()
355 clk_register_clkdev(clk, NULL, "sdhci-pxav3.2"); mmp2_clk_init()
357 clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3, mmp2_clk_init()
359 clk_register_clkdev(clk, NULL, "sdhci-pxav3.3"); mmp2_clk_init()
361 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, mmp2_clk_init()
363 clk_register_clkdev(clk, "usb_clk", NULL); mmp2_clk_init()
365 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, mmp2_clk_init()
369 clk_register_clkdev(clk, "disp_mux.0", NULL); mmp2_clk_init()
371 clk = clk_register_divider(NULL, "disp0_div", "disp0_mux", mmp2_clk_init()
374 clk_register_clkdev(clk, "disp_div.0", NULL); mmp2_clk_init()
376 clk = mmp_clk_register_apmu("disp0", "disp0_div", mmp2_clk_init()
378 clk_register_clkdev(clk, NULL, "mmp-disp.0"); mmp2_clk_init()
380 clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, mmp2_clk_init()
382 clk_register_clkdev(clk, "disp_sphy_div.0", NULL); mmp2_clk_init()
384 clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div", mmp2_clk_init()
386 clk_register_clkdev(clk, "disp_sphy.0", NULL); mmp2_clk_init()
388 clk = clk_register_mux(NULL, "disp1_mux", disp_parent, mmp2_clk_init()
392 clk_register_clkdev(clk, "disp_mux.1", NULL); mmp2_clk_init()
394 clk = clk_register_divider(NULL, "disp1_div", "disp1_mux", mmp2_clk_init()
397 clk_register_clkdev(clk, "disp_div.1", NULL); mmp2_clk_init()
399 clk = mmp_clk_register_apmu("disp1", "disp1_div", mmp2_clk_init()
401 clk_register_clkdev(clk, NULL, "mmp-disp.1"); mmp2_clk_init()
403 clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo", mmp2_clk_init()
405 clk_register_clkdev(clk, "ccic_arbiter", NULL); mmp2_clk_init()
407 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, mmp2_clk_init()
411 clk_register_clkdev(clk, "ccic_mux.0", NULL); mmp2_clk_init()
413 clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux", mmp2_clk_init()
416 clk_register_clkdev(clk, "ccic_div.0", NULL); mmp2_clk_init()
418 clk = mmp_clk_register_apmu("ccic0", "ccic0_div", mmp2_clk_init()
420 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); mmp2_clk_init()
422 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div", mmp2_clk_init()
424 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); mmp2_clk_init()
426 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div", mmp2_clk_init()
429 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); mmp2_clk_init()
431 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", mmp2_clk_init()
433 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); mmp2_clk_init()
435 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, mmp2_clk_init()
439 clk_register_clkdev(clk, "ccic_mux.1", NULL); mmp2_clk_init()
441 clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux", mmp2_clk_init()
444 clk_register_clkdev(clk, "ccic_div.1", NULL); mmp2_clk_init()
446 clk = mmp_clk_register_apmu("ccic1", "ccic1_div", mmp2_clk_init()
448 clk_register_clkdev(clk, "fnclk", "mmp-ccic.1"); mmp2_clk_init()
450 clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div", mmp2_clk_init()
452 clk_register_clkdev(clk, "phyclk", "mmp-ccic.1"); mmp2_clk_init()
454 clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div", mmp2_clk_init()
457 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1"); mmp2_clk_init()
459 clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div", mmp2_clk_init()
461 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1"); mmp2_clk_init()
|
| H A D | clk-pxa168.c | 21 #include "clk.h"
71 struct clk *clk; pxa168_clk_init() local
72 struct clk *uart_pll; pxa168_clk_init()
95 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); pxa168_clk_init()
96 clk_register_clkdev(clk, "clk32", NULL); pxa168_clk_init()
98 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, pxa168_clk_init()
100 clk_register_clkdev(clk, "vctcxo", NULL); pxa168_clk_init()
102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, pxa168_clk_init()
104 clk_register_clkdev(clk, "pll1", NULL); pxa168_clk_init()
106 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", pxa168_clk_init()
108 clk_register_clkdev(clk, "pll1_2", NULL); pxa168_clk_init()
110 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", pxa168_clk_init()
112 clk_register_clkdev(clk, "pll1_4", NULL); pxa168_clk_init()
114 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", pxa168_clk_init()
116 clk_register_clkdev(clk, "pll1_8", NULL); pxa168_clk_init()
118 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", pxa168_clk_init()
120 clk_register_clkdev(clk, "pll1_16", NULL); pxa168_clk_init()
122 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", pxa168_clk_init()
124 clk_register_clkdev(clk, "pll1_6", NULL); pxa168_clk_init()
126 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", pxa168_clk_init()
128 clk_register_clkdev(clk, "pll1_12", NULL); pxa168_clk_init()
130 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", pxa168_clk_init()
132 clk_register_clkdev(clk, "pll1_24", NULL); pxa168_clk_init()
134 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", pxa168_clk_init()
136 clk_register_clkdev(clk, "pll1_48", NULL); pxa168_clk_init()
138 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", pxa168_clk_init()
140 clk_register_clkdev(clk, "pll1_96", NULL); pxa168_clk_init()
142 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", pxa168_clk_init()
144 clk_register_clkdev(clk, "pll1_13", NULL); pxa168_clk_init()
146 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", pxa168_clk_init()
148 clk_register_clkdev(clk, "pll1_13_1_5", NULL); pxa168_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", pxa168_clk_init()
152 clk_register_clkdev(clk, "pll1_2_1_5", NULL); pxa168_clk_init()
154 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", pxa168_clk_init()
156 clk_register_clkdev(clk, "pll1_3_16", NULL); pxa168_clk_init()
165 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", pxa168_clk_init()
167 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); pxa168_clk_init()
169 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", pxa168_clk_init()
171 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); pxa168_clk_init()
173 clk = mmp_clk_register_apbc("gpio", "vctcxo", pxa168_clk_init()
175 clk_register_clkdev(clk, NULL, "mmp-gpio"); pxa168_clk_init()
177 clk = mmp_clk_register_apbc("kpc", "clk32", pxa168_clk_init()
179 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); pxa168_clk_init()
181 clk = mmp_clk_register_apbc("rtc", "clk32", pxa168_clk_init()
183 clk_register_clkdev(clk, NULL, "sa1100-rtc"); pxa168_clk_init()
185 clk = mmp_clk_register_apbc("pwm0", "pll1_48", pxa168_clk_init()
187 clk_register_clkdev(clk, NULL, "pxa168-pwm.0"); pxa168_clk_init()
189 clk = mmp_clk_register_apbc("pwm1", "pll1_48", pxa168_clk_init()
191 clk_register_clkdev(clk, NULL, "pxa168-pwm.1"); pxa168_clk_init()
193 clk = mmp_clk_register_apbc("pwm2", "pll1_48", pxa168_clk_init()
195 clk_register_clkdev(clk, NULL, "pxa168-pwm.2"); pxa168_clk_init()
197 clk = mmp_clk_register_apbc("pwm3", "pll1_48", pxa168_clk_init()
199 clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); pxa168_clk_init()
201 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, pxa168_clk_init()
205 clk_set_parent(clk, uart_pll); pxa168_clk_init()
206 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa168_clk_init()
208 clk = mmp_clk_register_apbc("uart0", "uart0_mux", pxa168_clk_init()
210 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); pxa168_clk_init()
212 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, pxa168_clk_init()
216 clk_set_parent(clk, uart_pll); pxa168_clk_init()
217 clk_register_clkdev(clk, "uart_mux.1", NULL); pxa168_clk_init()
219 clk = mmp_clk_register_apbc("uart1", "uart1_mux", pxa168_clk_init()
221 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); pxa168_clk_init()
223 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, pxa168_clk_init()
227 clk_set_parent(clk, uart_pll); pxa168_clk_init()
228 clk_register_clkdev(clk, "uart_mux.2", NULL); pxa168_clk_init()
230 clk = mmp_clk_register_apbc("uart2", "uart2_mux", pxa168_clk_init()
232 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); pxa168_clk_init()
234 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, pxa168_clk_init()
238 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa168_clk_init()
240 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, pxa168_clk_init()
242 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); pxa168_clk_init()
244 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, pxa168_clk_init()
248 clk_register_clkdev(clk, "ssp_mux.1", NULL); pxa168_clk_init()
250 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, pxa168_clk_init()
252 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); pxa168_clk_init()
254 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, pxa168_clk_init()
258 clk_register_clkdev(clk, "ssp_mux.2", NULL); pxa168_clk_init()
260 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, pxa168_clk_init()
262 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); pxa168_clk_init()
264 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, pxa168_clk_init()
268 clk_register_clkdev(clk, "ssp_mux.3", NULL); pxa168_clk_init()
270 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, pxa168_clk_init()
272 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); pxa168_clk_init()
274 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, pxa168_clk_init()
278 clk_register_clkdev(clk, "ssp_mux.4", NULL); pxa168_clk_init()
280 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, pxa168_clk_init()
282 clk_register_clkdev(clk, NULL, "mmp-ssp.4"); pxa168_clk_init()
284 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, pxa168_clk_init()
286 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); pxa168_clk_init()
288 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, pxa168_clk_init()
292 clk_register_clkdev(clk, "sdh0_mux", NULL); pxa168_clk_init()
294 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, pxa168_clk_init()
296 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); pxa168_clk_init()
298 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, pxa168_clk_init()
302 clk_register_clkdev(clk, "sdh1_mux", NULL); pxa168_clk_init()
304 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, pxa168_clk_init()
306 clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); pxa168_clk_init()
308 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, pxa168_clk_init()
310 clk_register_clkdev(clk, "usb_clk", NULL); pxa168_clk_init()
312 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, pxa168_clk_init()
314 clk_register_clkdev(clk, "sph_clk", NULL); pxa168_clk_init()
316 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, pxa168_clk_init()
320 clk_register_clkdev(clk, "disp_mux.0", NULL); pxa168_clk_init()
322 clk = mmp_clk_register_apmu("disp0", "disp0_mux", pxa168_clk_init()
324 clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); pxa168_clk_init()
326 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", pxa168_clk_init()
328 clk_register_clkdev(clk, "hclk", "mmp-disp.0"); pxa168_clk_init()
330 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, pxa168_clk_init()
334 clk_register_clkdev(clk, "ccic_mux.0", NULL); pxa168_clk_init()
336 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", pxa168_clk_init()
338 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); pxa168_clk_init()
340 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, pxa168_clk_init()
344 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); pxa168_clk_init()
346 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", pxa168_clk_init()
348 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); pxa168_clk_init()
350 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", pxa168_clk_init()
353 clk_register_clkdev(clk, "sphyclk_div", NULL); pxa168_clk_init()
355 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", pxa168_clk_init()
357 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); pxa168_clk_init()
|
| H A D | clk-pxa910.c | 21 #include "clk.h"
69 struct clk *clk; pxa910_clk_init() local
70 struct clk *uart_pll; pxa910_clk_init()
100 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); pxa910_clk_init()
101 clk_register_clkdev(clk, "clk32", NULL); pxa910_clk_init()
103 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, pxa910_clk_init()
105 clk_register_clkdev(clk, "vctcxo", NULL); pxa910_clk_init()
107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, pxa910_clk_init()
109 clk_register_clkdev(clk, "pll1", NULL); pxa910_clk_init()
111 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", pxa910_clk_init()
113 clk_register_clkdev(clk, "pll1_2", NULL); pxa910_clk_init()
115 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", pxa910_clk_init()
117 clk_register_clkdev(clk, "pll1_4", NULL); pxa910_clk_init()
119 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", pxa910_clk_init()
121 clk_register_clkdev(clk, "pll1_8", NULL); pxa910_clk_init()
123 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", pxa910_clk_init()
125 clk_register_clkdev(clk, "pll1_16", NULL); pxa910_clk_init()
127 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", pxa910_clk_init()
129 clk_register_clkdev(clk, "pll1_6", NULL); pxa910_clk_init()
131 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", pxa910_clk_init()
133 clk_register_clkdev(clk, "pll1_12", NULL); pxa910_clk_init()
135 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", pxa910_clk_init()
137 clk_register_clkdev(clk, "pll1_24", NULL); pxa910_clk_init()
139 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", pxa910_clk_init()
141 clk_register_clkdev(clk, "pll1_48", NULL); pxa910_clk_init()
143 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", pxa910_clk_init()
145 clk_register_clkdev(clk, "pll1_96", NULL); pxa910_clk_init()
147 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", pxa910_clk_init()
149 clk_register_clkdev(clk, "pll1_13", NULL); pxa910_clk_init()
151 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", pxa910_clk_init()
153 clk_register_clkdev(clk, "pll1_13_1_5", NULL); pxa910_clk_init()
155 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", pxa910_clk_init()
157 clk_register_clkdev(clk, "pll1_2_1_5", NULL); pxa910_clk_init()
159 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", pxa910_clk_init()
161 clk_register_clkdev(clk, "pll1_3_16", NULL); pxa910_clk_init()
170 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", pxa910_clk_init()
172 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); pxa910_clk_init()
174 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", pxa910_clk_init()
176 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); pxa910_clk_init()
178 clk = mmp_clk_register_apbc("gpio", "vctcxo", pxa910_clk_init()
180 clk_register_clkdev(clk, NULL, "mmp-gpio"); pxa910_clk_init()
182 clk = mmp_clk_register_apbc("kpc", "clk32", pxa910_clk_init()
184 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); pxa910_clk_init()
186 clk = mmp_clk_register_apbc("rtc", "clk32", pxa910_clk_init()
188 clk_register_clkdev(clk, NULL, "sa1100-rtc"); pxa910_clk_init()
190 clk = mmp_clk_register_apbc("pwm0", "pll1_48", pxa910_clk_init()
192 clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); pxa910_clk_init()
194 clk = mmp_clk_register_apbc("pwm1", "pll1_48", pxa910_clk_init()
196 clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); pxa910_clk_init()
198 clk = mmp_clk_register_apbc("pwm2", "pll1_48", pxa910_clk_init()
200 clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); pxa910_clk_init()
202 clk = mmp_clk_register_apbc("pwm3", "pll1_48", pxa910_clk_init()
204 clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); pxa910_clk_init()
206 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, pxa910_clk_init()
210 clk_set_parent(clk, uart_pll); pxa910_clk_init()
211 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa910_clk_init()
213 clk = mmp_clk_register_apbc("uart0", "uart0_mux", pxa910_clk_init()
215 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); pxa910_clk_init()
217 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, pxa910_clk_init()
221 clk_set_parent(clk, uart_pll); pxa910_clk_init()
222 clk_register_clkdev(clk, "uart_mux.1", NULL); pxa910_clk_init()
224 clk = mmp_clk_register_apbc("uart1", "uart1_mux", pxa910_clk_init()
226 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); pxa910_clk_init()
228 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, pxa910_clk_init()
232 clk_set_parent(clk, uart_pll); pxa910_clk_init()
233 clk_register_clkdev(clk, "uart_mux.2", NULL); pxa910_clk_init()
235 clk = mmp_clk_register_apbc("uart2", "uart2_mux", pxa910_clk_init()
237 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); pxa910_clk_init()
239 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, pxa910_clk_init()
243 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa910_clk_init()
245 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", pxa910_clk_init()
247 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); pxa910_clk_init()
249 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, pxa910_clk_init()
253 clk_register_clkdev(clk, "ssp_mux.1", NULL); pxa910_clk_init()
255 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", pxa910_clk_init()
257 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); pxa910_clk_init()
259 clk = mmp_clk_register_apmu("dfc", "pll1_4", pxa910_clk_init()
261 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); pxa910_clk_init()
263 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, pxa910_clk_init()
267 clk_register_clkdev(clk, "sdh0_mux", NULL); pxa910_clk_init()
269 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", pxa910_clk_init()
271 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); pxa910_clk_init()
273 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, pxa910_clk_init()
277 clk_register_clkdev(clk, "sdh1_mux", NULL); pxa910_clk_init()
279 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", pxa910_clk_init()
281 clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); pxa910_clk_init()
283 clk = mmp_clk_register_apmu("usb", "usb_pll", pxa910_clk_init()
285 clk_register_clkdev(clk, "usb_clk", NULL); pxa910_clk_init()
287 clk = mmp_clk_register_apmu("sph", "usb_pll", pxa910_clk_init()
289 clk_register_clkdev(clk, "sph_clk", NULL); pxa910_clk_init()
291 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, pxa910_clk_init()
295 clk_register_clkdev(clk, "disp_mux.0", NULL); pxa910_clk_init()
297 clk = mmp_clk_register_apmu("disp0", "disp0_mux", pxa910_clk_init()
299 clk_register_clkdev(clk, NULL, "mmp-disp.0"); pxa910_clk_init()
301 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, pxa910_clk_init()
305 clk_register_clkdev(clk, "ccic_mux.0", NULL); pxa910_clk_init()
307 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", pxa910_clk_init()
309 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); pxa910_clk_init()
311 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, pxa910_clk_init()
315 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); pxa910_clk_init()
317 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", pxa910_clk_init()
319 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); pxa910_clk_init()
321 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", pxa910_clk_init()
324 clk_register_clkdev(clk, "sphyclk_div", NULL); pxa910_clk_init()
326 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", pxa910_clk_init()
328 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); pxa910_clk_init()
|
| H A D | clk.c | 2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
8 #include "clk.h"
13 static struct clk **clk_table; mmp_clk_init()
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); mmp_clk_init()
31 struct clk *clk; mmp_register_fixed_rate_clks() local
34 clk = clk_register_fixed_rate(NULL, clks[i].name, mmp_register_fixed_rate_clks()
38 if (IS_ERR(clk)) { mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; mmp_register_fixed_rate_clks()
52 struct clk *clk; mmp_register_fixed_factor_clks() local
56 clk = clk_register_fixed_factor(NULL, clks[i].name, mmp_register_fixed_factor_clks()
60 if (IS_ERR(clk)) { mmp_register_fixed_factor_clks()
66 unit->clk_table[clks[i].id] = clk; mmp_register_fixed_factor_clks()
74 struct clk *clk; mmp_register_general_gate_clks() local
78 clk = clk_register_gate(NULL, clks[i].name, mmp_register_general_gate_clks()
86 if (IS_ERR(clk)) { mmp_register_general_gate_clks()
92 unit->clk_table[clks[i].id] = clk; mmp_register_general_gate_clks()
100 struct clk *clk; mmp_register_gate_clks() local
104 clk = mmp_clk_register_gate(NULL, clks[i].name, mmp_register_gate_clks()
114 if (IS_ERR(clk)) { mmp_register_gate_clks()
120 unit->clk_table[clks[i].id] = clk; mmp_register_gate_clks()
128 struct clk *clk; mmp_register_mux_clks() local
132 clk = clk_register_mux(NULL, clks[i].name, mmp_register_mux_clks()
142 if (IS_ERR(clk)) { mmp_register_mux_clks()
148 unit->clk_table[clks[i].id] = clk; mmp_register_mux_clks()
156 struct clk *clk; mmp_register_div_clks() local
160 clk = clk_register_divider(NULL, clks[i].name, mmp_register_div_clks()
169 if (IS_ERR(clk)) { mmp_register_div_clks()
175 unit->clk_table[clks[i].id] = clk; mmp_register_div_clks()
180 struct clk *clk) mmp_clk_add()
182 if (IS_ERR_OR_NULL(clk)) { mmp_clk_add()
183 pr_err("CLK %d has invalid pointer %p\n", id, clk); mmp_clk_add()
191 unit->clk_table[id] = clk; mmp_clk_add()
179 mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, struct clk *clk) mmp_clk_add() argument
|
| H A D | clk-apmu.c | 13 #include <linux/clk.h>
19 #include "clk.h"
21 #define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
69 struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, mmp_clk_register_apmu()
73 struct clk *clk; mmp_clk_register_apmu() local
91 clk = clk_register(NULL, &apmu->hw); mmp_clk_register_apmu()
93 if (IS_ERR(clk)) mmp_clk_register_apmu()
96 return clk; mmp_clk_register_apmu()
|
| /linux-4.1.27/arch/c6x/include/asm/ |
| H A D | clkdev.h | 6 struct clk;
8 static inline int __clk_get(struct clk *clk) __clk_get() argument
13 static inline void __clk_put(struct clk *clk) __clk_put() argument
|
| H A D | clock.h | 82 struct clk { struct
89 struct clk *parent;
94 unsigned long (*recalc) (struct clk *);
95 int (*set_rate) (struct clk *clk, unsigned long rate);
96 int (*round_rate) (struct clk *clk, unsigned long rate);
116 struct clk sysclks[MAX_PLL_SYSCLKS + 1];
128 .clk = ck, \
132 extern int clk_register(struct clk *clk);
133 extern void clk_unregister(struct clk *clk);
138 extern struct clk clkin1;
139 extern struct clk c6x_core_clk;
140 extern struct clk c6x_i2c_clk;
141 extern struct clk c6x_watchdog_clk;
142 extern struct clk c6x_mcbsp1_clk;
143 extern struct clk c6x_mcbsp2_clk;
144 extern struct clk c6x_mdio_clk;
|
| /linux-4.1.27/arch/arm/plat-versatile/ |
| H A D | clock.c | 14 #include <linux/clk.h>
21 int clk_enable(struct clk *clk) clk_enable() argument
27 void clk_disable(struct clk *clk) clk_disable() argument
32 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
34 return clk->rate; clk_get_rate()
38 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
41 if (clk->ops && clk->ops->round) clk_round_rate()
42 ret = clk->ops->round(clk, rate); clk_round_rate()
47 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
50 if (clk->ops && clk->ops->set) clk_set_rate()
51 ret = clk->ops->set(clk, rate); clk_set_rate()
56 long icst_clk_round(struct clk *clk, unsigned long rate) icst_clk_round() argument
59 vco = icst_hz_to_vco(clk->params, rate); icst_clk_round()
60 return icst_hz(clk->params, vco); icst_clk_round()
64 int icst_clk_set(struct clk *clk, unsigned long rate) icst_clk_set() argument
68 vco = icst_hz_to_vco(clk->params, rate); icst_clk_set()
69 clk->rate = icst_hz(clk->params, vco); icst_clk_set()
70 clk->ops->setvco(clk, vco); icst_clk_set()
|
| /linux-4.1.27/arch/c6x/platforms/ |
| H A D | pll.c | 20 #include <linux/clk.h>
31 static void __clk_enable(struct clk *clk) __clk_enable() argument
33 if (clk->parent) __clk_enable()
34 __clk_enable(clk->parent); __clk_enable()
35 clk->usecount++; __clk_enable()
38 static void __clk_disable(struct clk *clk) __clk_disable() argument
40 if (WARN_ON(clk->usecount == 0)) __clk_disable()
42 --clk->usecount; __clk_disable()
44 if (clk->parent) __clk_disable()
45 __clk_disable(clk->parent); __clk_disable()
48 int clk_enable(struct clk *clk) clk_enable() argument
52 if (clk == NULL || IS_ERR(clk)) clk_enable()
56 __clk_enable(clk); clk_enable()
63 void clk_disable(struct clk *clk) clk_disable() argument
67 if (clk == NULL || IS_ERR(clk)) clk_disable()
71 __clk_disable(clk); clk_disable()
76 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
78 if (clk == NULL || IS_ERR(clk)) clk_get_rate()
81 return clk->rate; clk_get_rate()
85 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
87 if (clk == NULL || IS_ERR(clk)) clk_round_rate()
90 if (clk->round_rate) clk_round_rate()
91 return clk->round_rate(clk, rate); clk_round_rate()
93 return clk->rate; clk_round_rate()
98 static void propagate_rate(struct clk *root) propagate_rate()
100 struct clk *clk; propagate_rate() local
102 list_for_each_entry(clk, &root->children, childnode) { propagate_rate()
103 if (clk->recalc) propagate_rate()
104 clk->rate = clk->recalc(clk); propagate_rate()
105 propagate_rate(clk); propagate_rate()
109 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
114 if (clk == NULL || IS_ERR(clk)) clk_set_rate()
117 if (clk->set_rate) clk_set_rate()
118 ret = clk->set_rate(clk, rate); clk_set_rate()
122 if (clk->recalc) clk_set_rate()
123 clk->rate = clk->recalc(clk); clk_set_rate()
124 propagate_rate(clk); clk_set_rate()
132 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
136 if (clk == NULL || IS_ERR(clk)) clk_set_parent()
140 if (WARN_ON(clk->usecount)) clk_set_parent()
144 clk->parent = parent; clk_set_parent()
145 list_del_init(&clk->childnode); clk_set_parent()
146 list_add(&clk->childnode, &clk->parent->children); clk_set_parent()
150 if (clk->recalc) clk_set_parent()
151 clk->rate = clk->recalc(clk); clk_set_parent()
152 propagate_rate(clk); clk_set_parent()
159 int clk_register(struct clk *clk) clk_register() argument
161 if (clk == NULL || IS_ERR(clk)) clk_register()
164 if (WARN(clk->parent && !clk->parent->rate, clk_register()
166 clk->name, clk->parent->name)) clk_register()
170 list_add_tail(&clk->node, &clocks); clk_register()
171 if (clk->parent) clk_register()
172 list_add_tail(&clk->childnode, &clk->parent->children); clk_register()
176 if (clk->rate) clk_register()
180 if (clk->recalc) clk_register()
181 clk->rate = clk->recalc(clk); clk_register()
184 else if (clk->parent) clk_register()
185 clk->rate = clk->parent->rate; clk_register()
191 void clk_unregister(struct clk *clk) clk_unregister() argument
193 if (clk == NULL || IS_ERR(clk)) clk_unregister()
197 list_del(&clk->node); clk_unregister()
198 list_del(&clk->childnode); clk_unregister()
209 static unsigned long clk_sysclk_recalc(struct clk *clk) clk_sysclk_recalc() argument
213 unsigned long rate = clk->rate; clk_sysclk_recalc()
215 if (WARN_ON(!clk->parent)) clk_sysclk_recalc()
218 rate = clk->parent->rate; clk_sysclk_recalc()
221 if (WARN_ON(!clk->parent->pll_data)) clk_sysclk_recalc()
224 pll = clk->parent->pll_data; clk_sysclk_recalc()
227 if (clk->flags & PRE_PLL) clk_sysclk_recalc()
230 if (!clk->div) { clk_sysclk_recalc()
232 clk->name, rate / 1000); clk_sysclk_recalc()
236 if (clk->flags & FIXED_DIV_PLL) { clk_sysclk_recalc()
237 rate /= clk->div; clk_sysclk_recalc()
239 clk->name, clk->div, rate / 1000); clk_sysclk_recalc()
243 v = pll_read(pll, clk->div); clk_sysclk_recalc()
253 clk->name, plldiv, rate / 1000); clk_sysclk_recalc()
258 static unsigned long clk_leafclk_recalc(struct clk *clk) clk_leafclk_recalc() argument
260 if (WARN_ON(!clk->parent)) clk_leafclk_recalc()
261 return clk->rate; clk_leafclk_recalc()
264 clk->name, clk->parent->name, clk->parent->rate / 1000); clk_leafclk_recalc()
266 return clk->parent->rate; clk_leafclk_recalc()
269 static unsigned long clk_pllclk_recalc(struct clk *clk) clk_pllclk_recalc() argument
273 struct pll_data *pll = clk->pll_data; clk_pllclk_recalc()
274 unsigned long rate = clk->rate; clk_pllclk_recalc()
276 if (clk->flags & FIXED_RATE_PLL) clk_pllclk_recalc()
280 rate = pll->input_rate = clk->parent->rate; clk_pllclk_recalc()
316 pll->num, clk->parent->rate / 1000000, clk_pllclk_recalc()
320 pll->num, clk->parent->rate / 1000000); clk_pllclk_recalc()
326 static void __init __init_clk(struct clk *clk) __init_clk() argument
328 INIT_LIST_HEAD(&clk->node); __init_clk()
329 INIT_LIST_HEAD(&clk->children); __init_clk()
330 INIT_LIST_HEAD(&clk->childnode); __init_clk()
332 if (!clk->recalc) { __init_clk()
335 if (clk->pll_data) __init_clk()
336 clk->recalc = clk_pllclk_recalc; __init_clk()
339 else if (clk->flags & CLK_PLL) __init_clk()
340 clk->recalc = clk_sysclk_recalc; __init_clk()
343 else if (clk->parent) __init_clk()
344 clk->recalc = clk_leafclk_recalc; __init_clk()
351 struct clk *clk; c6x_clks_init() local
354 for (c = clocks; c->clk; c++) { c6x_clks_init()
355 clk = c->clk; c6x_clks_init()
357 __init_clk(clk); c6x_clks_init()
358 clk_register(clk); c6x_clks_init()
362 if (clk->flags & ALWAYS_ENABLED) c6x_clks_init()
363 clk_enable(clk); c6x_clks_init()
379 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) dump_clock()
383 struct clk *clk; dump_clock() local
403 list_for_each_entry(clk, &parent->children, childnode) { dump_clock()
404 dump_clock(s, nest + NEST_DELTA, clk); dump_clock()
410 struct clk *clk; c6x_ck_show() local
416 list_for_each_entry(clk, &clocks, node) c6x_ck_show()
417 if (!clk->parent) c6x_ck_show()
418 dump_clock(m, 0, clk); c6x_ck_show()
|
| /linux-4.1.27/arch/arm/mach-pxa/ |
| H A D | clock.c | 6 #include <linux/clk.h>
15 int clk_enable(struct clk *clk) clk_enable() argument
20 if (clk->enabled++ == 0) clk_enable()
21 clk->ops->enable(clk); clk_enable()
24 if (clk->delay) clk_enable()
25 udelay(clk->delay); clk_enable()
31 void clk_disable(struct clk *clk) clk_disable() argument
35 WARN_ON(clk->enabled == 0); clk_disable()
38 if (--clk->enabled == 0) clk_disable()
39 clk->ops->disable(clk); clk_disable()
44 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
48 rate = clk->rate; clk_get_rate()
49 if (clk->ops->getrate) clk_get_rate()
50 rate = clk->ops->getrate(clk); clk_get_rate()
56 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
61 if (clk->ops->setrate) { clk_set_rate()
63 ret = clk->ops->setrate(clk, rate); clk_set_rate()
71 void clk_dummy_enable(struct clk *clk) clk_dummy_enable() argument
75 void clk_dummy_disable(struct clk *clk) clk_dummy_disable() argument
84 struct clk clk_dummy = {
|
| H A D | clock.h | 5 void (*enable)(struct clk *);
6 void (*disable)(struct clk *);
7 unsigned long (*getrate)(struct clk *);
8 int (*setrate)(struct clk *, unsigned long);
11 struct clk { struct
19 void clk_dummy_enable(struct clk *);
20 void clk_dummy_disable(struct clk *);
23 extern struct clk clk_dummy;
27 .clk = _clk, \
33 struct clk clk_##_name = { \
39 struct clk clk_##_name = { \
46 struct clk clk_##_name = { \
55 void clk_pxa2xx_cken_enable(struct clk *clk);
56 void clk_pxa2xx_cken_disable(struct clk *clk);
62 struct clk clk_##_name = { \
75 extern void clk_pxa3xx_cken_enable(struct clk *);
76 extern void clk_pxa3xx_cken_disable(struct clk *);
|
| H A D | clock-pxa2xx.c | 19 void clk_pxa2xx_cken_enable(struct clk *clk) clk_pxa2xx_cken_enable() argument
21 CKEN |= 1 << clk->cken; clk_pxa2xx_cken_enable()
24 void clk_pxa2xx_cken_disable(struct clk *clk) clk_pxa2xx_cken_disable() argument
26 CKEN &= ~(1 << clk->cken); clk_pxa2xx_cken_disable()
|
| H A D | clock-pxa3xx.c | 79 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) clk_pxa3xx_ac97_getrate() argument
98 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) clk_pxa3xx_hsio_getrate() argument
115 static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) clk_pxa3xx_smemc_getrate() argument
124 void clk_pxa3xx_cken_enable(struct clk *clk) clk_pxa3xx_cken_enable() argument
126 unsigned long mask = 1ul << (clk->cken & 0x1f); clk_pxa3xx_cken_enable()
128 if (clk->cken < 32) clk_pxa3xx_cken_enable()
130 else if (clk->cken < 64) clk_pxa3xx_cken_enable()
136 void clk_pxa3xx_cken_disable(struct clk *clk) clk_pxa3xx_cken_disable() argument
138 unsigned long mask = 1ul << (clk->cken & 0x1f); clk_pxa3xx_cken_disable()
140 if (clk->cken < 32) clk_pxa3xx_cken_disable()
142 else if (clk->cken < 64) clk_pxa3xx_cken_disable()
171 static void clk_pout_enable(struct clk *clk) clk_pout_enable() argument
176 static void clk_pout_disable(struct clk *clk) clk_pout_disable() argument
|
| /linux-4.1.27/arch/arm/mach-davinci/ |
| H A D | clock.c | 17 #include <linux/clk.h>
34 static void __clk_enable(struct clk *clk) __clk_enable() argument
36 if (clk->parent) __clk_enable()
37 __clk_enable(clk->parent); __clk_enable()
38 if (clk->usecount++ == 0) { __clk_enable()
39 if (clk->flags & CLK_PSC) __clk_enable()
40 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, __clk_enable()
41 true, clk->flags); __clk_enable()
42 else if (clk->clk_enable) __clk_enable()
43 clk->clk_enable(clk); __clk_enable()
47 static void __clk_disable(struct clk *clk) __clk_disable() argument
49 if (WARN_ON(clk->usecount == 0)) __clk_disable()
51 if (--clk->usecount == 0) { __clk_disable()
52 if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) __clk_disable()
53 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, __clk_disable()
54 false, clk->flags); __clk_disable()
55 else if (clk->clk_disable) __clk_disable()
56 clk->clk_disable(clk); __clk_disable()
58 if (clk->parent) __clk_disable()
59 __clk_disable(clk->parent); __clk_disable()
62 int davinci_clk_reset(struct clk *clk, bool reset) davinci_clk_reset() argument
66 if (clk == NULL || IS_ERR(clk)) davinci_clk_reset()
70 if (clk->flags & CLK_PSC) davinci_clk_reset()
71 davinci_psc_reset(clk->gpsc, clk->lpsc, reset); davinci_clk_reset()
78 int davinci_clk_reset_assert(struct clk *clk) davinci_clk_reset_assert() argument
80 if (clk == NULL || IS_ERR(clk) || !clk->reset) davinci_clk_reset_assert()
83 return clk->reset(clk, true); davinci_clk_reset_assert()
87 int davinci_clk_reset_deassert(struct clk *clk) davinci_clk_reset_deassert() argument
89 if (clk == NULL || IS_ERR(clk) || !clk->reset) davinci_clk_reset_deassert()
92 return clk->reset(clk, false); davinci_clk_reset_deassert()
96 int clk_enable(struct clk *clk) clk_enable() argument
100 if (clk == NULL || IS_ERR(clk)) clk_enable()
104 __clk_enable(clk); clk_enable()
111 void clk_disable(struct clk *clk) clk_disable() argument
115 if (clk == NULL || IS_ERR(clk)) clk_disable()
119 __clk_disable(clk); clk_disable()
124 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
126 if (clk == NULL || IS_ERR(clk)) clk_get_rate()
129 return clk->rate; clk_get_rate()
133 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
135 if (clk == NULL || IS_ERR(clk)) clk_round_rate()
138 if (clk->round_rate) clk_round_rate()
139 return clk->round_rate(clk, rate); clk_round_rate()
141 return clk->rate; clk_round_rate()
146 static void propagate_rate(struct clk *root) propagate_rate()
148 struct clk *clk; propagate_rate() local
150 list_for_each_entry(clk, &root->children, childnode) { propagate_rate()
151 if (clk->recalc) propagate_rate()
152 clk->rate = clk->recalc(clk); propagate_rate()
153 propagate_rate(clk); propagate_rate()
157 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
162 if (clk == NULL || IS_ERR(clk)) clk_set_rate()
165 if (clk->set_rate) clk_set_rate()
166 ret = clk->set_rate(clk, rate); clk_set_rate()
170 if (clk->recalc) clk_set_rate()
171 clk->rate = clk->recalc(clk); clk_set_rate()
172 propagate_rate(clk); clk_set_rate()
180 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
184 if (clk == NULL || IS_ERR(clk)) clk_set_parent()
188 if (WARN_ON(clk->usecount)) clk_set_parent()
192 clk->parent = parent; clk_set_parent()
193 list_del_init(&clk->childnode); clk_set_parent()
194 list_add(&clk->childnode, &clk->parent->children); clk_set_parent()
198 if (clk->recalc) clk_set_parent()
199 clk->rate = clk->recalc(clk); clk_set_parent()
200 propagate_rate(clk); clk_set_parent()
207 int clk_register(struct clk *clk) clk_register() argument
209 if (clk == NULL || IS_ERR(clk)) clk_register()
212 if (WARN(clk->parent && !clk->parent->rate, clk_register()
214 clk->name, clk->parent->name)) clk_register()
217 INIT_LIST_HEAD(&clk->children); clk_register()
220 list_add_tail(&clk->node, &clocks); clk_register()
221 if (clk->parent) clk_register()
222 list_add_tail(&clk->childnode, &clk->parent->children); clk_register()
226 if (clk->rate) clk_register()
230 if (clk->recalc) clk_register()
231 clk->rate = clk->recalc(clk); clk_register()
234 else if (clk->parent) clk_register()
235 clk->rate = clk->parent->rate; clk_register()
241 void clk_unregister(struct clk *clk) clk_unregister() argument
243 if (clk == NULL || IS_ERR(clk)) clk_unregister()
247 list_del(&clk->node); clk_unregister()
248 list_del(&clk->childnode); clk_unregister()
259 struct clk *ck; davinci_clk_disable_unused()
283 static unsigned long clk_sysclk_recalc(struct clk *clk) clk_sysclk_recalc() argument
287 unsigned long rate = clk->rate; clk_sysclk_recalc()
290 if (clk->pll_data) clk_sysclk_recalc()
293 if (WARN_ON(!clk->parent)) clk_sysclk_recalc()
296 rate = clk->parent->rate; clk_sysclk_recalc()
299 if (WARN_ON(!clk->parent->pll_data)) clk_sysclk_recalc()
302 pll = clk->parent->pll_data; clk_sysclk_recalc()
305 if (clk->flags & PRE_PLL) clk_sysclk_recalc()
308 if (!clk->div_reg) clk_sysclk_recalc()
311 v = __raw_readl(pll->base + clk->div_reg); clk_sysclk_recalc()
321 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) davinci_set_sysclk_rate() argument
329 if (clk->pll_data) davinci_set_sysclk_rate()
333 if (WARN_ON(!clk->parent)) davinci_set_sysclk_rate()
337 if (WARN_ON(!clk->parent->pll_data)) davinci_set_sysclk_rate()
341 if (WARN_ON(!clk->div_reg)) davinci_set_sysclk_rate()
344 pll = clk->parent->pll_data; davinci_set_sysclk_rate()
346 input = clk->parent->rate; davinci_set_sysclk_rate()
349 if (clk->flags & PRE_PLL) davinci_set_sysclk_rate()
358 if (clk->maxrate) { davinci_set_sysclk_rate()
360 if (input / ratio > clk->maxrate) davinci_set_sysclk_rate()
377 v = __raw_readl(pll->base + clk->div_reg); davinci_set_sysclk_rate()
380 __raw_writel(v, pll->base + clk->div_reg); davinci_set_sysclk_rate()
394 static unsigned long clk_leafclk_recalc(struct clk *clk) clk_leafclk_recalc() argument
396 if (WARN_ON(!clk->parent)) clk_leafclk_recalc()
397 return clk->rate; clk_leafclk_recalc()
399 return clk->parent->rate; clk_leafclk_recalc()
402 int davinci_simple_set_rate(struct clk *clk, unsigned long rate) davinci_simple_set_rate() argument
404 clk->rate = rate; davinci_simple_set_rate()
408 static unsigned long clk_pllclk_recalc(struct clk *clk) clk_pllclk_recalc() argument
412 struct pll_data *pll = clk->pll_data; clk_pllclk_recalc()
413 unsigned long rate = clk->rate; clk_pllclk_recalc()
416 rate = pll->input_rate = clk->parent->rate; clk_pllclk_recalc()
455 pll->num, clk->parent->rate / 1000000); clk_pllclk_recalc()
563 struct clk *refclk; davinci_set_refclk_rate()
581 struct clk *clk; davinci_clk_init() local
584 for (c = clocks; c->clk; c++) { davinci_clk_init()
585 clk = c->clk; davinci_clk_init()
587 if (!clk->recalc) { davinci_clk_init()
590 if (clk->pll_data) davinci_clk_init()
591 clk->recalc = clk_pllclk_recalc; davinci_clk_init()
594 else if (clk->flags & CLK_PLL) davinci_clk_init()
595 clk->recalc = clk_sysclk_recalc; davinci_clk_init()
598 else if (clk->parent) davinci_clk_init()
599 clk->recalc = clk_leafclk_recalc; davinci_clk_init()
602 if (clk->pll_data) { davinci_clk_init()
603 struct pll_data *pll = clk->pll_data; davinci_clk_init()
614 if (clk->recalc) davinci_clk_init()
615 clk->rate = clk->recalc(clk); davinci_clk_init()
617 if (clk->lpsc) davinci_clk_init()
618 clk->flags |= CLK_PSC; davinci_clk_init()
620 if (clk->flags & PSC_LRST) davinci_clk_init()
621 clk->reset = davinci_clk_reset; davinci_clk_init()
623 clk_register(clk); davinci_clk_init()
627 if (clk->flags & ALWAYS_ENABLED) davinci_clk_init()
628 clk_enable(clk); davinci_clk_init()
646 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) dump_clock()
650 struct clk *clk; dump_clock() local
672 list_for_each_entry(clk, &parent->children, childnode) { dump_clock()
673 dump_clock(s, nest + NEST_DELTA, clk); dump_clock()
679 struct clk *clk; davinci_ck_show() local
685 list_for_each_entry(clk, &clocks, node) davinci_ck_show()
686 if (!clk->parent) davinci_ck_show()
687 dump_clock(m, 0, clk); davinci_ck_show()
|
| H A D | clock.h | 87 struct clk { struct
98 struct clk *parent;
103 unsigned long (*recalc) (struct clk *);
104 int (*set_rate) (struct clk *clk, unsigned long rate);
105 int (*round_rate) (struct clk *clk, unsigned long rate);
106 int (*reset) (struct clk *clk, bool reset);
107 void (*clk_enable) (struct clk *clk);
108 void (*clk_disable) (struct clk *clk);
124 .clk = ck, \
130 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
132 int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
133 int davinci_clk_reset(struct clk *clk, bool reset);
|
| /linux-4.1.27/arch/arm/mach-sa1100/ |
| H A D | clock.c | 11 #include <linux/clk.h>
21 void (*enable)(struct clk *);
22 void (*disable)(struct clk *);
23 unsigned long (*get_rate)(struct clk *);
26 struct clk { struct
32 struct clk clk_##_name = { \
38 static void clk_gpio27_enable(struct clk *clk) clk_gpio27_enable() argument
49 static void clk_gpio27_disable(struct clk *clk) clk_gpio27_disable() argument
56 static void clk_cpu_enable(struct clk *clk) clk_cpu_enable() argument
60 static void clk_cpu_disable(struct clk *clk) clk_cpu_disable() argument
64 static unsigned long clk_cpu_get_rate(struct clk *clk) clk_cpu_get_rate() argument
69 int clk_enable(struct clk *clk) clk_enable() argument
73 if (clk) { clk_enable()
75 if (clk->enabled++ == 0) clk_enable()
76 clk->ops->enable(clk); clk_enable()
84 void clk_disable(struct clk *clk) clk_disable() argument
88 if (clk) { clk_disable()
89 WARN_ON(clk->enabled == 0); clk_disable()
91 if (--clk->enabled == 0) clk_disable()
92 clk->ops->disable(clk); clk_disable()
98 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
100 if (clk && clk->ops && clk->ops->get_rate) clk_get_rate()
101 return clk->ops->get_rate(clk); clk_get_rate()
122 static unsigned long clk_36864_get_rate(struct clk *clk) clk_36864_get_rate() argument
|
| /linux-4.1.27/arch/mips/ralink/ |
| H A D | clk.c | 13 #include <linux/clk.h>
19 struct clk { struct
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); ralink_clk_add() local
28 if (!clk) ralink_clk_add()
31 clk->cl.dev_id = dev; ralink_clk_add()
32 clk->cl.clk = clk; ralink_clk_add()
34 clk->rate = rate; ralink_clk_add()
36 clkdev_add(&clk->cl); ralink_clk_add()
42 int clk_enable(struct clk *clk) clk_enable() argument
48 void clk_disable(struct clk *clk) clk_disable() argument
53 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
55 return clk->rate; clk_get_rate()
59 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
67 struct clk *clk; plat_time_init() local
72 clk = clk_get_sys("cpu", NULL); plat_time_init()
73 if (IS_ERR(clk)) plat_time_init()
74 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); plat_time_init()
75 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); plat_time_init()
76 mips_hpt_frequency = clk_get_rate(clk) / 2; plat_time_init()
77 clk_put(clk); plat_time_init()
|
| /linux-4.1.27/drivers/sh/clk/ |
| H A D | cpg.c | 11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) sh_clk_read()
22 return ioread8(clk->mapped_reg); sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) sh_clk_read()
24 return ioread16(clk->mapped_reg); sh_clk_read()
26 return ioread32(clk->mapped_reg); sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) sh_clk_write()
32 iowrite8(value, clk->mapped_reg); sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) sh_clk_write()
34 iowrite16(value, clk->mapped_reg); sh_clk_write()
36 iowrite32(value, clk->mapped_reg); sh_clk_write()
54 static int sh_clk_mstp_enable(struct clk *clk) sh_clk_mstp_enable() argument
56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); sh_clk_mstp_enable()
57 if (clk->status_reg) { sh_clk_mstp_enable()
60 void __iomem *mapped_status = (phys_addr_t)clk->status_reg - sh_clk_mstp_enable()
61 (phys_addr_t)clk->enable_reg + clk->mapped_reg; sh_clk_mstp_enable()
63 if (clk->flags & CLK_ENABLE_REG_8BIT) sh_clk_mstp_enable()
65 else if (clk->flags & CLK_ENABLE_REG_16BIT) sh_clk_mstp_enable()
71 (read(mapped_status) & (1 << clk->enable_bit)) && i; sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); sh_clk_mstp_enable()
83 static void sh_clk_mstp_disable(struct clk *clk) sh_clk_mstp_disable() argument
85 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); sh_clk_mstp_disable()
94 int __init sh_clk_mstp_register(struct clk *clks, int nr) sh_clk_mstp_register()
96 struct clk *clkp; sh_clk_mstp_register()
112 static inline struct clk_div_table *clk_to_div_table(struct clk *clk) clk_to_div_table() argument
114 return clk->priv; clk_to_div_table()
117 static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk) clk_to_div_mult_table() argument
119 return clk_to_div_table(clk)->div_mult_table; clk_to_div_mult_table()
125 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) sh_clk_div_round_rate() argument
127 return clk_rate_table_round(clk, clk->freq_table, rate); sh_clk_div_round_rate()
130 static unsigned long sh_clk_div_recalc(struct clk *clk) sh_clk_div_recalc() argument
132 struct clk_div_mult_table *table = clk_to_div_mult_table(clk); sh_clk_div_recalc()
135 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, sh_clk_div_recalc()
136 table, clk->arch_flags ? &clk->arch_flags : NULL); sh_clk_div_recalc()
138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; sh_clk_div_recalc()
140 return clk->freq_table[idx].frequency; sh_clk_div_recalc()
143 static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate) sh_clk_div_set_rate() argument
145 struct clk_div_table *dt = clk_to_div_table(clk); sh_clk_div_set_rate()
149 idx = clk_rate_table_find(clk, clk->freq_table, rate); sh_clk_div_set_rate()
153 value = sh_clk_read(clk); sh_clk_div_set_rate()
154 value &= ~(clk->div_mask << clk->enable_bit); sh_clk_div_set_rate()
155 value |= (idx << clk->enable_bit); sh_clk_div_set_rate()
156 sh_clk_write(value, clk); sh_clk_div_set_rate()
160 dt->kick(clk); sh_clk_div_set_rate()
165 static int sh_clk_div_enable(struct clk *clk) sh_clk_div_enable() argument
167 if (clk->div_mask == SH_CLK_DIV6_MSK) { sh_clk_div_enable()
168 int ret = sh_clk_div_set_rate(clk, clk->rate); sh_clk_div_enable()
173 sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk); sh_clk_div_enable()
177 static void sh_clk_div_disable(struct clk *clk) sh_clk_div_disable() argument
181 val = sh_clk_read(clk); sh_clk_div_disable()
189 if (clk->flags & CLK_MASK_DIV_ON_DISABLE) sh_clk_div_disable()
190 val |= clk->div_mask; sh_clk_div_disable()
192 sh_clk_write(val, clk); sh_clk_div_disable()
209 static int __init sh_clk_init_parent(struct clk *clk) sh_clk_init_parent() argument
213 if (clk->parent) sh_clk_init_parent()
216 if (!clk->parent_table || !clk->parent_num) sh_clk_init_parent()
219 if (!clk->src_width) { sh_clk_init_parent()
224 val = (sh_clk_read(clk) >> clk->src_shift); sh_clk_init_parent()
225 val &= (1 << clk->src_width) - 1; sh_clk_init_parent()
227 if (val >= clk->parent_num) { sh_clk_init_parent()
232 clk_reparent(clk, clk->parent_table[val]); sh_clk_init_parent()
233 if (!clk->parent) { sh_clk_init_parent()
241 static int __init sh_clk_div_register_ops(struct clk *clks, int nr, sh_clk_div_register_ops()
244 struct clk *clkp; sh_clk_div_register_ops()
294 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) sh_clk_div6_set_parent() argument
296 struct clk_div_mult_table *table = clk_to_div_mult_table(clk); sh_clk_div6_set_parent()
300 if (!clk->parent_table || !clk->parent_num) sh_clk_div6_set_parent()
304 for (i = 0; i < clk->parent_num; i++) sh_clk_div6_set_parent()
305 if (clk->parent_table[i] == parent) sh_clk_div6_set_parent()
308 if (i == clk->parent_num) sh_clk_div6_set_parent()
311 ret = clk_reparent(clk, parent); sh_clk_div6_set_parent()
315 value = sh_clk_read(clk) & sh_clk_div6_set_parent()
316 ~(((1 << clk->src_width) - 1) << clk->src_shift); sh_clk_div6_set_parent()
318 sh_clk_write(value | (i << clk->src_shift), clk); sh_clk_div6_set_parent()
321 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, sh_clk_div6_set_parent()
336 int __init sh_clk_div6_register(struct clk *clks, int nr) sh_clk_div6_register()
342 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) sh_clk_div6_reparent_register()
351 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) sh_clk_div4_set_parent() argument
353 struct clk_div_mult_table *table = clk_to_div_mult_table(clk); sh_clk_div4_set_parent()
363 value = sh_clk_read(clk) & ~(1 << 7); sh_clk_div4_set_parent()
365 value = sh_clk_read(clk) | (1 << 7); sh_clk_div4_set_parent()
367 ret = clk_reparent(clk, parent); sh_clk_div4_set_parent()
371 sh_clk_write(value, clk); sh_clk_div4_set_parent()
374 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, sh_clk_div4_set_parent()
375 table, &clk->arch_flags); sh_clk_div4_set_parent()
389 int __init sh_clk_div4_register(struct clk *clks, int nr, sh_clk_div4_register()
395 int __init sh_clk_div4_enable_register(struct clk *clks, int nr, sh_clk_div4_enable_register()
402 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, sh_clk_div4_reparent_register()
410 static unsigned long fsidiv_recalc(struct clk *clk) fsidiv_recalc() argument
414 value = __raw_readl(clk->mapping->base); fsidiv_recalc()
418 return clk->parent->rate; fsidiv_recalc()
420 return clk->parent->rate / value; fsidiv_recalc()
423 static long fsidiv_round_rate(struct clk *clk, unsigned long rate) fsidiv_round_rate() argument
425 return clk_rate_div_range_round(clk, 1, 0xffff, rate); fsidiv_round_rate()
428 static void fsidiv_disable(struct clk *clk) fsidiv_disable() argument
430 __raw_writel(0, clk->mapping->base); fsidiv_disable()
433 static int fsidiv_enable(struct clk *clk) fsidiv_enable() argument
437 value = __raw_readl(clk->mapping->base) >> 16; fsidiv_enable()
441 __raw_writel((value << 16) | 0x3, clk->mapping->base); fsidiv_enable()
446 static int fsidiv_set_rate(struct clk *clk, unsigned long rate) fsidiv_set_rate() argument
450 idx = (clk->parent->rate / rate) & 0xffff; fsidiv_set_rate()
452 __raw_writel(0, clk->mapping->base); fsidiv_set_rate()
454 __raw_writel(idx << 16, clk->mapping->base); fsidiv_set_rate()
467 int __init sh_clk_fsidiv_register(struct clk *clks, int nr) sh_clk_fsidiv_register()
|
| H A D | core.c | 29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, clk_rate_table_round()
149 if (clk->nr_freqs < 1) clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), clk_rate_mult_range_round()
195 int clk_rate_table_find(struct clk *clk, clk_rate_table_find() argument
209 unsigned long followparent_recalc(struct clk *clk) followparent_recalc() argument
211 return clk->parent ? clk->parent->rate : 0; followparent_recalc()
214 int clk_reparent(struct clk *child, struct clk *parent) clk_reparent()
225 void propagate_rate(struct clk *tclk) propagate_rate()
227 struct clk *clkp; propagate_rate()
237 static void __clk_disable(struct clk *clk) __clk_disable() argument
239 if (WARN(!clk->usecount, "Trying to disable clock %p with 0 usecount\n", __clk_disable()
240 clk)) __clk_disable()
243 if (!(--clk->usecount)) { __clk_disable()
244 if (likely(allow_disable && clk->ops && clk->ops->disable)) __clk_disable()
245 clk->ops->disable(clk); __clk_disable()
246 if (likely(clk->parent)) __clk_disable()
247 __clk_disable(clk->parent); __clk_disable()
251 void clk_disable(struct clk *clk) clk_disable() argument
255 if (!clk) clk_disable()
259 __clk_disable(clk); clk_disable()
264 static int __clk_enable(struct clk *clk) __clk_enable() argument
268 if (clk->usecount++ == 0) { __clk_enable()
269 if (clk->parent) { __clk_enable()
270 ret = __clk_enable(clk->parent); __clk_enable()
275 if (clk->ops && clk->ops->enable) { __clk_enable()
276 ret = clk->ops->enable(clk); __clk_enable()
278 if (clk->parent) __clk_enable()
279 __clk_disable(clk->parent); __clk_enable()
287 clk->usecount--; __clk_enable()
291 int clk_enable(struct clk *clk) clk_enable() argument
296 if (!clk) clk_enable()
300 ret = __clk_enable(clk); clk_enable()
318 struct clk *clkp; recalculate_root_clocks()
329 static struct clk *lookup_root_clock(struct clk *clk) lookup_root_clock() argument
331 while (clk->parent) lookup_root_clock()
332 clk = clk->parent; lookup_root_clock()
334 return clk; lookup_root_clock()
337 static int clk_establish_mapping(struct clk *clk) clk_establish_mapping() argument
339 struct clk_mapping *mapping = clk->mapping; clk_establish_mapping()
345 struct clk *clkp; clk_establish_mapping()
350 if (!clk->parent) { clk_establish_mapping()
351 clk->mapping = &dummy_mapping; clk_establish_mapping()
359 clkp = lookup_root_clock(clk); clk_establish_mapping()
380 clk->mapping = mapping; clk_establish_mapping()
382 clk->mapped_reg = clk->mapping->base; clk_establish_mapping()
383 clk->mapped_reg += (phys_addr_t)clk->enable_reg - clk->mapping->phys; clk_establish_mapping()
396 static void clk_teardown_mapping(struct clk *clk) clk_teardown_mapping() argument
398 struct clk_mapping *mapping = clk->mapping; clk_teardown_mapping()
405 clk->mapping = NULL; clk_teardown_mapping()
407 clk->mapped_reg = NULL; clk_teardown_mapping()
410 int clk_register(struct clk *clk) clk_register() argument
414 if (IS_ERR_OR_NULL(clk)) clk_register()
420 if (clk->node.next || clk->node.prev) clk_register()
425 INIT_LIST_HEAD(&clk->children); clk_register()
426 clk->usecount = 0; clk_register()
428 ret = clk_establish_mapping(clk); clk_register()
432 if (clk->parent) clk_register()
433 list_add(&clk->sibling, &clk->parent->children); clk_register()
435 list_add(&clk->sibling, &root_clks); clk_register()
437 list_add(&clk->node, &clock_list); clk_register()
440 if (clk->ops && clk->ops->init) clk_register()
441 clk->ops->init(clk); clk_register()
451 void clk_unregister(struct clk *clk) clk_unregister() argument
454 list_del(&clk->sibling); clk_unregister()
455 list_del(&clk->node); clk_unregister()
456 clk_teardown_mapping(clk); clk_unregister()
463 struct clk *clkp; clk_enable_init_clocks()
470 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
472 return clk->rate; clk_get_rate()
476 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
483 if (likely(clk->ops && clk->ops->set_rate)) { clk_set_rate()
484 ret = clk->ops->set_rate(clk, rate); clk_set_rate()
488 clk->rate = rate; clk_set_rate()
492 if (clk->ops && clk->ops->recalc) clk_set_rate()
493 clk->rate = clk->ops->recalc(clk); clk_set_rate()
495 propagate_rate(clk); clk_set_rate()
504 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
509 if (!parent || !clk) clk_set_parent()
511 if (clk->parent == parent) clk_set_parent()
515 if (clk->usecount == 0) { clk_set_parent()
516 if (clk->ops->set_parent) clk_set_parent()
517 ret = clk->ops->set_parent(clk, parent); clk_set_parent()
519 ret = clk_reparent(clk, parent); clk_set_parent()
522 if (clk->ops->recalc) clk_set_parent()
523 clk->rate = clk->ops->recalc(clk); clk_set_parent()
525 clk, clk->parent, clk->rate); clk_set_parent()
526 propagate_rate(clk); clk_set_parent()
536 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
538 return clk->parent; clk_get_parent()
542 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
544 if (likely(clk->ops && clk->ops->round_rate)) { clk_round_rate()
548 rounded = clk->ops->round_rate(clk, rate); clk_round_rate()
554 return clk_get_rate(clk); clk_round_rate()
558 long clk_round_parent(struct clk *clk, unsigned long target, clk_round_parent() argument
564 struct clk *parent = clk_get_parent(clk); clk_round_parent()
568 *best_freq = clk_round_rate(clk, target); clk_round_parent()
649 struct clk *clkp; clks_core_resume()
682 struct clk *clk; clk_late_init() local
688 list_for_each_entry(clk, &clock_list, node) clk_late_init()
689 if (!clk->usecount && clk->ops && clk->ops->disable) clk_late_init()
690 clk->ops->disable(clk); clk_late_init()
|
| /linux-4.1.27/drivers/media/v4l2-core/ |
| H A D | v4l2-clk.c | 12 #include <linux/clk.h>
21 #include <media/v4l2-clk.h>
29 struct v4l2_clk *clk; v4l2_clk_find() local
31 list_for_each_entry(clk, &clk_list, list) v4l2_clk_find()
32 if (!strcmp(dev_id, clk->dev_id)) v4l2_clk_find()
33 return clk; v4l2_clk_find()
40 struct v4l2_clk *clk; v4l2_clk_get() local
41 struct clk *ccf_clk = clk_get(dev, id); v4l2_clk_get()
47 clk = kzalloc(sizeof(*clk), GFP_KERNEL); v4l2_clk_get()
48 if (!clk) { v4l2_clk_get()
52 clk->clk = ccf_clk; v4l2_clk_get()
54 return clk; v4l2_clk_get()
58 clk = v4l2_clk_find(dev_name(dev)); v4l2_clk_get()
60 if (!IS_ERR(clk)) v4l2_clk_get()
61 atomic_inc(&clk->use_count); v4l2_clk_get()
64 return clk; v4l2_clk_get()
68 void v4l2_clk_put(struct v4l2_clk *clk) v4l2_clk_put() argument
72 if (IS_ERR(clk)) v4l2_clk_put()
75 if (clk->clk) { v4l2_clk_put()
76 clk_put(clk->clk); v4l2_clk_put()
77 kfree(clk); v4l2_clk_put()
84 if (tmp == clk) v4l2_clk_put()
85 atomic_dec(&clk->use_count); v4l2_clk_put()
91 static int v4l2_clk_lock_driver(struct v4l2_clk *clk) v4l2_clk_lock_driver() argument
99 if (tmp == clk) { v4l2_clk_lock_driver()
100 ret = !try_module_get(clk->ops->owner); v4l2_clk_lock_driver()
111 static void v4l2_clk_unlock_driver(struct v4l2_clk *clk) v4l2_clk_unlock_driver() argument
113 module_put(clk->ops->owner); v4l2_clk_unlock_driver()
116 int v4l2_clk_enable(struct v4l2_clk *clk) v4l2_clk_enable() argument
120 if (clk->clk) v4l2_clk_enable()
121 return clk_prepare_enable(clk->clk); v4l2_clk_enable()
123 ret = v4l2_clk_lock_driver(clk); v4l2_clk_enable()
127 mutex_lock(&clk->lock); v4l2_clk_enable()
129 if (++clk->enable == 1 && clk->ops->enable) { v4l2_clk_enable()
130 ret = clk->ops->enable(clk); v4l2_clk_enable()
132 clk->enable--; v4l2_clk_enable()
135 mutex_unlock(&clk->lock); v4l2_clk_enable()
145 void v4l2_clk_disable(struct v4l2_clk *clk) v4l2_clk_disable() argument
149 if (clk->clk) v4l2_clk_disable()
150 return clk_disable_unprepare(clk->clk); v4l2_clk_disable()
152 mutex_lock(&clk->lock); v4l2_clk_disable()
154 enable = --clk->enable; v4l2_clk_disable()
156 clk->dev_id)) v4l2_clk_disable()
157 clk->enable++; v4l2_clk_disable()
158 else if (!enable && clk->ops->disable) v4l2_clk_disable()
159 clk->ops->disable(clk); v4l2_clk_disable()
161 mutex_unlock(&clk->lock); v4l2_clk_disable()
163 v4l2_clk_unlock_driver(clk); v4l2_clk_disable()
167 unsigned long v4l2_clk_get_rate(struct v4l2_clk *clk) v4l2_clk_get_rate() argument
171 if (clk->clk) v4l2_clk_get_rate()
172 return clk_get_rate(clk->clk); v4l2_clk_get_rate()
174 ret = v4l2_clk_lock_driver(clk); v4l2_clk_get_rate()
178 mutex_lock(&clk->lock); v4l2_clk_get_rate()
179 if (!clk->ops->get_rate) v4l2_clk_get_rate()
182 ret = clk->ops->get_rate(clk); v4l2_clk_get_rate()
183 mutex_unlock(&clk->lock); v4l2_clk_get_rate()
185 v4l2_clk_unlock_driver(clk); v4l2_clk_get_rate()
191 int v4l2_clk_set_rate(struct v4l2_clk *clk, unsigned long rate) v4l2_clk_set_rate() argument
195 if (clk->clk) { v4l2_clk_set_rate()
196 long r = clk_round_rate(clk->clk, rate); v4l2_clk_set_rate()
199 return clk_set_rate(clk->clk, r); v4l2_clk_set_rate()
202 ret = v4l2_clk_lock_driver(clk); v4l2_clk_set_rate()
207 mutex_lock(&clk->lock); v4l2_clk_set_rate()
208 if (!clk->ops->set_rate) v4l2_clk_set_rate()
211 ret = clk->ops->set_rate(clk, rate); v4l2_clk_set_rate()
212 mutex_unlock(&clk->lock); v4l2_clk_set_rate()
214 v4l2_clk_unlock_driver(clk); v4l2_clk_set_rate()
224 struct v4l2_clk *clk; v4l2_clk_register() local
230 clk = kzalloc(sizeof(struct v4l2_clk), GFP_KERNEL); v4l2_clk_register()
231 if (!clk) v4l2_clk_register()
234 clk->dev_id = kstrdup(dev_id, GFP_KERNEL); v4l2_clk_register()
235 if (!clk->dev_id) { v4l2_clk_register()
239 clk->ops = ops; v4l2_clk_register()
240 clk->priv = priv; v4l2_clk_register()
241 atomic_set(&clk->use_count, 0); v4l2_clk_register()
242 mutex_init(&clk->lock); v4l2_clk_register()
250 list_add_tail(&clk->list, &clk_list); v4l2_clk_register()
253 return clk; v4l2_clk_register()
257 kfree(clk->dev_id); v4l2_clk_register()
258 kfree(clk); v4l2_clk_register()
263 void v4l2_clk_unregister(struct v4l2_clk *clk) v4l2_clk_unregister() argument
265 if (WARN(atomic_read(&clk->use_count), v4l2_clk_unregister()
267 __func__, clk->dev_id)) v4l2_clk_unregister()
271 list_del(&clk->list); v4l2_clk_unregister()
274 kfree(clk->dev_id); v4l2_clk_unregister()
275 kfree(clk); v4l2_clk_unregister()
284 static unsigned long fixed_get_rate(struct v4l2_clk *clk) fixed_get_rate() argument
286 struct v4l2_clk_fixed *priv = clk->priv; fixed_get_rate()
293 struct v4l2_clk *clk; __v4l2_clk_register_fixed() local
303 clk = v4l2_clk_register(&priv->ops, dev_id, priv); __v4l2_clk_register_fixed()
304 if (IS_ERR(clk)) __v4l2_clk_register_fixed()
307 return clk; __v4l2_clk_register_fixed()
311 void v4l2_clk_unregister_fixed(struct v4l2_clk *clk) v4l2_clk_unregister_fixed() argument
313 kfree(clk->priv); v4l2_clk_unregister_fixed()
314 v4l2_clk_unregister(clk); v4l2_clk_unregister_fixed()
|
| /linux-4.1.27/arch/avr32/mach-at32ap/ |
| H A D | clock.h | 14 #include <linux/clk.h>
18 void at32_clk_register(struct clk *clk);
20 struct clk { struct
24 struct clk *parent; /* Parent clock, if any */
25 void (*mode)(struct clk *clk, int enabled);
26 unsigned long (*get_rate)(struct clk *clk);
27 long (*set_rate)(struct clk *clk, unsigned long rate,
29 int (*set_parent)(struct clk *clk, struct clk *parent);
34 unsigned long pba_clk_get_rate(struct clk *clk);
35 void pba_clk_mode(struct clk *clk, int enabled);
|
| H A D | clock.c | 14 #include <linux/clk.h>
31 void at32_clk_register(struct clk *clk) at32_clk_register() argument
35 list_add_tail(&clk->list, &at32_clock_list); at32_clk_register()
39 static struct clk *__clk_get(struct device *dev, const char *id) __clk_get()
41 struct clk *clk; __clk_get() local
43 list_for_each_entry(clk, &at32_clock_list, list) { __clk_get()
44 if (clk->dev == dev && strcmp(id, clk->name) == 0) { __clk_get()
45 return clk; __clk_get()
52 struct clk *clk_get(struct device *dev, const char *id) clk_get()
54 struct clk *clk; clk_get() local
57 clk = __clk_get(dev, id); clk_get()
60 return clk; clk_get()
65 void clk_put(struct clk *clk) clk_put() argument
71 static void __clk_enable(struct clk *clk) __clk_enable() argument
73 if (clk->parent) __clk_enable()
74 __clk_enable(clk->parent); __clk_enable()
75 if (clk->users++ == 0 && clk->mode) __clk_enable()
76 clk->mode(clk, 1); __clk_enable()
79 int clk_enable(struct clk *clk) clk_enable() argument
83 if (!clk) clk_enable()
87 __clk_enable(clk); clk_enable()
94 static void __clk_disable(struct clk *clk) __clk_disable() argument
96 if (clk->users == 0) { __clk_disable()
97 printk(KERN_ERR "%s: mismatched disable\n", clk->name); __clk_disable()
102 if (--clk->users == 0 && clk->mode) __clk_disable()
103 clk->mode(clk, 0); __clk_disable()
104 if (clk->parent) __clk_disable()
105 __clk_disable(clk->parent); __clk_disable()
108 void clk_disable(struct clk *clk) clk_disable() argument
112 if (IS_ERR_OR_NULL(clk)) clk_disable()
116 __clk_disable(clk); clk_disable()
121 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
126 if (!clk) clk_get_rate()
130 rate = clk->get_rate(clk); clk_get_rate()
137 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
141 if (!clk) clk_round_rate()
144 if (!clk->set_rate) clk_round_rate()
148 actual_rate = clk->set_rate(clk, rate, 0); clk_round_rate()
155 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
160 if (!clk) clk_set_rate()
163 if (!clk->set_rate) clk_set_rate()
167 ret = clk->set_rate(clk, rate, 1); clk_set_rate()
174 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
179 if (!clk) clk_set_parent()
182 if (!clk->set_parent) clk_set_parent()
186 ret = clk->set_parent(clk, parent); clk_set_parent()
193 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
195 return !clk ? NULL : clk->parent; clk_get_parent()
220 dump_clock(struct clk *parent, struct clkinf *r) dump_clock()
224 struct clk *clk; dump_clock() local
250 list_for_each_entry(clk, &at32_clock_list, list) { dump_clock()
251 if (clk->parent == parent) dump_clock()
252 dump_clock(clk, r); dump_clock()
261 struct clk *clk; clk_show() local
287 clk = __clk_get(NULL, "osc32k"); clk_show()
288 dump_clock(clk, &r); clk_show()
289 clk_put(clk); clk_show()
291 clk = __clk_get(NULL, "osc0"); clk_show()
292 dump_clock(clk, &r); clk_show()
293 clk_put(clk); clk_show()
295 clk = __clk_get(NULL, "osc1"); clk_show()
296 dump_clock(clk, &r); clk_show()
297 clk_put(clk); clk_show()
|
| /linux-4.1.27/arch/mips/jz4740/ |
| H A D | clock.h | 31 struct clk;
34 unsigned long (*get_rate)(struct clk *clk);
35 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
36 int (*set_rate)(struct clk *clk, unsigned long rate);
37 int (*enable)(struct clk *clk);
38 int (*disable)(struct clk *clk);
39 int (*is_enabled)(struct clk *clk);
41 int (*set_parent)(struct clk *clk, struct clk *parent);
45 struct clk { struct
47 struct clk *parent;
64 int clk_is_enabled(struct clk *clk);
68 void jz4740_clock_debugfs_add_clk(struct clk *clk);
69 void jz4740_clock_debugfs_update_parent(struct clk *clk);
72 static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {}; jz4740_clock_debugfs_update_parent() argument
73 static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {}; argument
|
| H A D | clock.c | 18 #include <linux/clk.h>
105 struct clk clk; member in struct:main_clk
110 struct clk clk; member in struct:divided_clk
116 struct clk clk; member in struct:static_clk
159 static int jz_clk_enable_gating(struct clk *clk) jz_clk_enable_gating() argument
161 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) jz_clk_enable_gating()
164 jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); jz_clk_enable_gating()
168 static int jz_clk_disable_gating(struct clk *clk) jz_clk_disable_gating() argument
170 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) jz_clk_disable_gating()
173 jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); jz_clk_disable_gating()
177 static int jz_clk_is_enabled_gating(struct clk *clk) jz_clk_is_enabled_gating() argument
179 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) jz_clk_is_enabled_gating()
182 return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit); jz_clk_is_enabled_gating()
185 static unsigned long jz_clk_static_get_rate(struct clk *clk) jz_clk_static_get_rate() argument
187 return ((struct static_clk *)clk)->rate; jz_clk_static_get_rate()
190 static int jz_clk_ko_enable(struct clk *clk) jz_clk_ko_enable() argument
196 static int jz_clk_ko_disable(struct clk *clk) jz_clk_ko_disable() argument
202 static int jz_clk_ko_is_enabled(struct clk *clk) jz_clk_ko_is_enabled() argument
209 static unsigned long jz_clk_pll_get_rate(struct clk *clk) jz_clk_pll_get_rate() argument
219 return clk_get_rate(clk->parent); jz_clk_pll_get_rate()
225 return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; jz_clk_pll_get_rate()
228 static unsigned long jz_clk_pll_half_get_rate(struct clk *clk) jz_clk_pll_half_get_rate() argument
234 return jz_clk_pll_get_rate(clk->parent); jz_clk_pll_half_get_rate()
235 return jz_clk_pll_get_rate(clk->parent) >> 1; jz_clk_pll_half_get_rate()
240 static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate) jz_clk_main_round_rate() argument
242 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); jz_clk_main_round_rate()
256 static unsigned long jz_clk_main_get_rate(struct clk *clk) jz_clk_main_get_rate() argument
258 struct main_clk *mclk = (struct main_clk *)clk; jz_clk_main_get_rate()
269 return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; jz_clk_main_get_rate()
272 static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate) jz_clk_main_set_rate() argument
274 struct main_clk *mclk = (struct main_clk *)clk; jz_clk_main_set_rate()
277 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); jz_clk_main_set_rate()
279 rate = jz_clk_main_round_rate(clk, rate); jz_clk_main_set_rate()
301 .clk = {
312 static struct clk jz_clk_pll = {
314 .parent = &jz_clk_ext.clk,
322 static struct clk jz_clk_pll_half = {
335 .clk = {
344 .clk = {
353 .clk = {
363 .clk = {
377 static struct clk jz_clk_ko = {
379 .parent = &jz_clk_memory.clk,
383 static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent) jz_clk_spi_set_parent() argument
387 else if (parent == &jz_clk_ext.clk) jz_clk_spi_set_parent()
392 clk->parent = parent; jz_clk_spi_set_parent()
397 static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent) jz_clk_i2s_set_parent() argument
401 else if (parent == &jz_clk_ext.clk) jz_clk_i2s_set_parent()
406 clk->parent = parent; jz_clk_i2s_set_parent()
411 static int jz_clk_udc_enable(struct clk *clk) jz_clk_udc_enable() argument
419 static int jz_clk_udc_disable(struct clk *clk) jz_clk_udc_disable() argument
427 static int jz_clk_udc_is_enabled(struct clk *clk) jz_clk_udc_is_enabled() argument
433 static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent) jz_clk_udc_set_parent() argument
437 else if (parent == &jz_clk_ext.clk) jz_clk_udc_set_parent()
442 clk->parent = parent; jz_clk_udc_set_parent()
447 static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate) jz_clk_udc_set_rate() argument
451 if (clk->parent == &jz_clk_ext.clk) jz_clk_udc_set_rate()
454 div = clk_get_rate(clk->parent) / rate - 1; jz_clk_udc_set_rate()
466 static unsigned long jz_clk_udc_get_rate(struct clk *clk) jz_clk_udc_get_rate() argument
470 if (clk->parent == &jz_clk_ext.clk) jz_clk_udc_get_rate()
471 return clk_get_rate(clk->parent); jz_clk_udc_get_rate()
477 return clk_get_rate(clk->parent) / div; jz_clk_udc_get_rate()
480 static unsigned long jz_clk_divided_get_rate(struct clk *clk) jz_clk_divided_get_rate() argument
482 struct divided_clk *dclk = (struct divided_clk *)clk; jz_clk_divided_get_rate()
485 if (clk->parent == &jz_clk_ext.clk) jz_clk_divided_get_rate()
486 return clk_get_rate(clk->parent); jz_clk_divided_get_rate()
490 return clk_get_rate(clk->parent) / div; jz_clk_divided_get_rate()
493 static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate) jz_clk_divided_set_rate() argument
495 struct divided_clk *dclk = (struct divided_clk *)clk; jz_clk_divided_set_rate()
498 if (clk->parent == &jz_clk_ext.clk) jz_clk_divided_set_rate()
501 div = clk_get_rate(clk->parent) / rate - 1; jz_clk_divided_set_rate()
513 static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate) jz_clk_ldclk_round_rate() argument
516 unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent); jz_clk_ldclk_round_rate()
530 static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate) jz_clk_ldclk_set_rate() argument
537 div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; jz_clk_ldclk_set_rate()
549 static unsigned long jz_clk_ldclk_get_rate(struct clk *clk) jz_clk_ldclk_get_rate() argument
556 return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); jz_clk_ldclk_get_rate()
568 static struct clk jz_clk_ld = {
603 .clk = {
605 .parent = &jz_clk_ext.clk,
613 .clk = {
615 .parent = &jz_clk_ext.clk,
623 .clk = {
633 .clk = {
643 .clk = {
669 static struct clk jz4740_clock_simple_clks[] = {
672 .parent = &jz_clk_ext.clk,
677 .parent = &jz_clk_ext.clk,
683 .parent = &jz_clk_ext.clk,
689 .parent = &jz_clk_high_speed_peripheral.clk,
695 .parent = &jz_clk_high_speed_peripheral.clk,
701 .parent = &jz_clk_ext.clk,
707 .parent = &jz_clk_ext.clk,
713 .parent = &jz_clk_ext.clk,
720 .clk = {
728 int clk_enable(struct clk *clk) clk_enable() argument
730 if (!clk->ops->enable) clk_enable()
733 return clk->ops->enable(clk); clk_enable()
737 void clk_disable(struct clk *clk) clk_disable() argument
739 if (clk->ops->disable) clk_disable()
740 clk->ops->disable(clk); clk_disable()
744 int clk_is_enabled(struct clk *clk) clk_is_enabled() argument
746 if (clk->ops->is_enabled) clk_is_enabled()
747 return clk->ops->is_enabled(clk); clk_is_enabled()
752 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
754 if (clk->ops->get_rate) clk_get_rate()
755 return clk->ops->get_rate(clk); clk_get_rate()
756 if (clk->parent) clk_get_rate()
757 return clk_get_rate(clk->parent); clk_get_rate()
763 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
765 if (!clk->ops->set_rate) clk_set_rate()
767 return clk->ops->set_rate(clk, rate); clk_set_rate()
771 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
773 if (clk->ops->round_rate) clk_round_rate()
774 return clk->ops->round_rate(clk, rate); clk_round_rate()
780 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
785 if (!clk->ops->set_parent) clk_set_parent()
788 enabled = clk_is_enabled(clk); clk_set_parent()
790 clk_disable(clk); clk_set_parent()
791 ret = clk->ops->set_parent(clk, parent); clk_set_parent()
793 clk_enable(clk); clk_set_parent()
795 jz4740_clock_debugfs_update_parent(clk); clk_set_parent()
801 struct clk *clk_get(struct device *dev, const char *name) clk_get()
803 struct clk *clk; clk_get() local
805 list_for_each_entry(clk, &jz_clocks, list) { clk_get()
806 if (strcmp(clk->name, name) == 0) clk_get()
807 return clk; clk_get()
813 void clk_put(struct clk *clk) clk_put() argument
818 static inline void clk_add(struct clk *clk) clk_add() argument
820 list_add_tail(&clk->list, &jz_clocks); clk_add()
822 jz4740_clock_debugfs_add_clk(clk); clk_add()
829 clk_add(&jz_clk_ext.clk); clk_register_clks()
832 clk_add(&jz_clk_cpu.clk); clk_register_clks()
833 clk_add(&jz_clk_high_speed_peripheral.clk); clk_register_clks()
834 clk_add(&jz_clk_low_speed_peripheral.clk); clk_register_clks()
837 clk_add(&jz_clk_rtc.clk); clk_register_clks()
840 clk_add(&jz4740_clock_divided_clks[i].clk); clk_register_clks()
908 jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; jz4740_clock_init()
913 jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; jz4740_clock_init()
|
| H A D | clock-debugfs.c | 18 #include <linux/clk.h>
31 struct clk *clk = data; jz4740_clock_debugfs_show_enabled() local
32 *value = clk_is_enabled(clk); jz4740_clock_debugfs_show_enabled()
39 struct clk *clk = data; jz4740_clock_debugfs_set_enabled() local
42 return clk_enable(clk); jz4740_clock_debugfs_set_enabled()
44 clk_disable(clk); jz4740_clock_debugfs_set_enabled()
56 struct clk *clk = data; jz4740_clock_debugfs_show_rate() local
57 *value = clk_get_rate(clk); jz4740_clock_debugfs_show_rate()
67 void jz4740_clock_debugfs_add_clk(struct clk *clk) jz4740_clock_debugfs_add_clk() argument
72 clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs); jz4740_clock_debugfs_add_clk()
73 debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk, jz4740_clock_debugfs_add_clk()
75 debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk, jz4740_clock_debugfs_add_clk()
78 if (clk->parent) { jz4740_clock_debugfs_add_clk()
80 snprintf(parent_path, 100, "../%s", clk->parent->name); jz4740_clock_debugfs_add_clk()
81 clk->debugfs_parent_entry = debugfs_create_symlink("parent", jz4740_clock_debugfs_add_clk()
82 clk->debugfs_entry, jz4740_clock_debugfs_add_clk()
88 void jz4740_clock_debugfs_update_parent(struct clk *clk) jz4740_clock_debugfs_update_parent() argument
90 debugfs_remove(clk->debugfs_parent_entry); jz4740_clock_debugfs_update_parent()
92 if (clk->parent) { jz4740_clock_debugfs_update_parent()
94 snprintf(parent_path, 100, "../%s", clk->parent->name); jz4740_clock_debugfs_update_parent()
95 clk->debugfs_parent_entry = debugfs_create_symlink("parent", jz4740_clock_debugfs_update_parent()
96 clk->debugfs_entry, jz4740_clock_debugfs_update_parent()
99 clk->debugfs_parent_entry = NULL; jz4740_clock_debugfs_update_parent()
|
| /linux-4.1.27/arch/arm/mach-omap1/ |
| H A D | clock.c | 20 #include <linux/clk.h>
34 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
44 unsigned long omap1_uart_recalc(struct clk *clk) omap1_uart_recalc() argument
46 unsigned int val = __raw_readl(clk->enable_reg); omap1_uart_recalc()
47 return val & clk->enable_bit ? 48000000 : 12000000; omap1_uart_recalc()
50 unsigned long omap1_sossi_recalc(struct clk *clk) omap1_sossi_recalc() argument
57 return clk->parent->rate / div; omap1_sossi_recalc()
60 static void omap1_clk_allow_idle(struct clk *clk) omap1_clk_allow_idle() argument
62 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; omap1_clk_allow_idle()
64 if (!(clk->flags & CLOCK_IDLE_CONTROL)) omap1_clk_allow_idle()
71 static void omap1_clk_deny_idle(struct clk *clk) omap1_clk_deny_idle() argument
73 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; omap1_clk_deny_idle()
75 if (!(clk->flags & CLOCK_IDLE_CONTROL)) omap1_clk_deny_idle()
135 static int calc_dsor_exp(struct clk *clk, unsigned long rate) calc_dsor_exp() argument
149 struct clk * parent; calc_dsor_exp()
152 parent = clk->parent; calc_dsor_exp()
167 unsigned long omap1_ckctl_recalc(struct clk *clk) omap1_ckctl_recalc() argument
170 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); omap1_ckctl_recalc()
172 return clk->parent->rate / dsor; omap1_ckctl_recalc()
175 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) omap1_ckctl_recalc_dsp_domain() argument
187 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); omap1_ckctl_recalc_dsp_domain()
190 return clk->parent->rate / dsor; omap1_ckctl_recalc_dsp_domain()
194 int omap1_select_table_rate(struct clk *clk, unsigned long rate) omap1_select_table_rate() argument
229 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) omap1_clk_set_rate_dsp_domain() argument
234 dsor_exp = calc_dsor_exp(clk, rate); omap1_clk_set_rate_dsp_domain()
241 regval &= ~(3 << clk->rate_offset); omap1_clk_set_rate_dsp_domain()
242 regval |= dsor_exp << clk->rate_offset; omap1_clk_set_rate_dsp_domain()
244 clk->rate = clk->parent->rate / (1 << dsor_exp); omap1_clk_set_rate_dsp_domain()
249 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) omap1_clk_round_rate_ckctl_arm() argument
251 int dsor_exp = calc_dsor_exp(clk, rate); omap1_clk_round_rate_ckctl_arm()
256 return clk->parent->rate / (1 << dsor_exp); omap1_clk_round_rate_ckctl_arm()
259 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) omap1_clk_set_rate_ckctl_arm() argument
264 dsor_exp = calc_dsor_exp(clk, rate); omap1_clk_set_rate_ckctl_arm()
271 regval &= ~(3 << clk->rate_offset); omap1_clk_set_rate_ckctl_arm()
272 regval |= dsor_exp << clk->rate_offset; omap1_clk_set_rate_ckctl_arm()
275 clk->rate = clk->parent->rate / (1 << dsor_exp); omap1_clk_set_rate_ckctl_arm()
279 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) omap1_round_to_table_rate() argument
330 int omap1_set_uart_rate(struct clk *clk, unsigned long rate) omap1_set_uart_rate() argument
334 val = __raw_readl(clk->enable_reg); omap1_set_uart_rate()
336 val &= ~(1 << clk->enable_bit); omap1_set_uart_rate()
338 val |= (1 << clk->enable_bit); omap1_set_uart_rate()
341 __raw_writel(val, clk->enable_reg); omap1_set_uart_rate()
342 clk->rate = rate; omap1_set_uart_rate()
348 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) omap1_set_ext_clk_rate() argument
354 clk->rate = 96000000 / dsor; omap1_set_ext_clk_rate()
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; omap1_set_ext_clk_rate()
361 __raw_writew(ratio_bits, clk->enable_reg); omap1_set_ext_clk_rate()
366 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) omap1_set_sossi_rate() argument
372 p_rate = clk->parent->rate; omap1_set_sossi_rate()
384 clk->rate = p_rate / (div + 1); omap1_set_sossi_rate()
389 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) omap1_round_ext_clk_rate() argument
394 void omap1_init_ext_clk(struct clk *clk) omap1_init_ext_clk() argument
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1; omap1_init_ext_clk()
401 __raw_writew(ratio_bits, clk->enable_reg); omap1_init_ext_clk()
409 clk-> rate = 96000000 / dsor; omap1_init_ext_clk()
412 int omap1_clk_enable(struct clk *clk) omap1_clk_enable() argument
416 if (clk->usecount++ == 0) { omap1_clk_enable()
417 if (clk->parent) { omap1_clk_enable()
418 ret = omap1_clk_enable(clk->parent); omap1_clk_enable()
422 if (clk->flags & CLOCK_NO_IDLE_PARENT) omap1_clk_enable()
423 omap1_clk_deny_idle(clk->parent); omap1_clk_enable()
426 ret = clk->ops->enable(clk); omap1_clk_enable()
428 if (clk->parent) omap1_clk_enable()
429 omap1_clk_disable(clk->parent); omap1_clk_enable()
436 clk->usecount--; omap1_clk_enable()
440 void omap1_clk_disable(struct clk *clk) omap1_clk_disable() argument
442 if (clk->usecount > 0 && !(--clk->usecount)) { omap1_clk_disable()
443 clk->ops->disable(clk); omap1_clk_disable()
444 if (likely(clk->parent)) { omap1_clk_disable()
445 omap1_clk_disable(clk->parent); omap1_clk_disable()
446 if (clk->flags & CLOCK_NO_IDLE_PARENT) omap1_clk_disable()
447 omap1_clk_allow_idle(clk->parent); omap1_clk_disable()
452 static int omap1_clk_enable_generic(struct clk *clk) omap1_clk_enable_generic() argument
457 if (unlikely(clk->enable_reg == NULL)) { omap1_clk_enable_generic()
459 clk->name); omap1_clk_enable_generic()
463 if (clk->flags & ENABLE_REG_32BIT) { omap1_clk_enable_generic()
464 regval32 = __raw_readl(clk->enable_reg); omap1_clk_enable_generic()
465 regval32 |= (1 << clk->enable_bit); omap1_clk_enable_generic()
466 __raw_writel(regval32, clk->enable_reg); omap1_clk_enable_generic()
468 regval16 = __raw_readw(clk->enable_reg); omap1_clk_enable_generic()
469 regval16 |= (1 << clk->enable_bit); omap1_clk_enable_generic()
470 __raw_writew(regval16, clk->enable_reg); omap1_clk_enable_generic()
476 static void omap1_clk_disable_generic(struct clk *clk) omap1_clk_disable_generic() argument
481 if (clk->enable_reg == NULL) omap1_clk_disable_generic()
484 if (clk->flags & ENABLE_REG_32BIT) { omap1_clk_disable_generic()
485 regval32 = __raw_readl(clk->enable_reg); omap1_clk_disable_generic()
486 regval32 &= ~(1 << clk->enable_bit); omap1_clk_disable_generic()
487 __raw_writel(regval32, clk->enable_reg); omap1_clk_disable_generic()
489 regval16 = __raw_readw(clk->enable_reg); omap1_clk_disable_generic()
490 regval16 &= ~(1 << clk->enable_bit); omap1_clk_disable_generic()
491 __raw_writew(regval16, clk->enable_reg); omap1_clk_disable_generic()
500 static int omap1_clk_enable_dsp_domain(struct clk *clk) omap1_clk_enable_dsp_domain() argument
506 retval = omap1_clk_enable_generic(clk); omap1_clk_enable_dsp_domain()
513 static void omap1_clk_disable_dsp_domain(struct clk *clk) omap1_clk_disable_dsp_domain() argument
516 omap1_clk_disable_generic(clk); omap1_clk_disable_dsp_domain()
527 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) omap1_clk_enable_uart_functional_16xx() argument
532 ret = omap1_clk_enable_generic(clk); omap1_clk_enable_uart_functional_16xx()
535 uclk = (struct uart_clk *)clk; omap1_clk_enable_uart_functional_16xx()
544 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk) omap1_clk_disable_uart_functional_16xx() argument
549 uclk = (struct uart_clk *)clk; omap1_clk_disable_uart_functional_16xx()
552 omap1_clk_disable_generic(clk); omap1_clk_disable_uart_functional_16xx()
561 long omap1_clk_round_rate(struct clk *clk, unsigned long rate) omap1_clk_round_rate() argument
563 if (clk->round_rate != NULL) omap1_clk_round_rate()
564 return clk->round_rate(clk, rate); omap1_clk_round_rate()
566 return clk->rate; omap1_clk_round_rate()
569 int omap1_clk_set_rate(struct clk *clk, unsigned long rate) omap1_clk_set_rate() argument
573 if (clk->set_rate) omap1_clk_set_rate()
574 ret = clk->set_rate(clk, rate); omap1_clk_set_rate()
584 void omap1_clk_disable_unused(struct clk *clk) omap1_clk_disable_unused() argument
590 if (clk->enable_reg == DSP_IDLECT2) { omap1_clk_disable_unused()
592 clk->name); omap1_clk_disable_unused()
597 if (clk->flags & ENABLE_REG_32BIT) omap1_clk_disable_unused()
598 regval32 = __raw_readl(clk->enable_reg); omap1_clk_disable_unused()
600 regval32 = __raw_readw(clk->enable_reg); omap1_clk_disable_unused()
602 if ((regval32 & (1 << clk->enable_bit)) == 0) omap1_clk_disable_unused()
605 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); omap1_clk_disable_unused()
606 clk->ops->disable(clk); omap1_clk_disable_unused()
613 int clk_enable(struct clk *clk) clk_enable() argument
618 if (clk == NULL || IS_ERR(clk)) clk_enable()
622 ret = omap1_clk_enable(clk); clk_enable()
629 void clk_disable(struct clk *clk) clk_disable() argument
633 if (clk == NULL || IS_ERR(clk)) clk_disable()
637 if (clk->usecount == 0) { clk_disable()
639 clk->name); clk_disable()
644 omap1_clk_disable(clk); clk_disable()
651 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
656 if (clk == NULL || IS_ERR(clk)) clk_get_rate()
660 ret = clk->rate; clk_get_rate()
668 * Optional clock functions defined in include/linux/clk.h
671 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
676 if (clk == NULL || IS_ERR(clk)) clk_round_rate()
680 ret = omap1_clk_round_rate(clk, rate); clk_round_rate()
687 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
692 if (clk == NULL || IS_ERR(clk)) clk_set_rate()
696 ret = omap1_clk_set_rate(clk, rate); clk_set_rate()
698 propagate_rate(clk); clk_set_rate()
705 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
713 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
715 return clk->parent; clk_get_parent()
744 unsigned long followparent_recalc(struct clk *clk) followparent_recalc() argument
746 return clk->parent->rate; followparent_recalc()
753 unsigned long omap_fixed_divisor_recalc(struct clk *clk) omap_fixed_divisor_recalc() argument
755 WARN_ON(!clk->fixed_div); omap_fixed_divisor_recalc()
757 return clk->parent->rate / clk->fixed_div; omap_fixed_divisor_recalc()
760 void clk_reparent(struct clk *child, struct clk *parent) clk_reparent()
772 void propagate_rate(struct clk *tclk) propagate_rate()
774 struct clk *clkp; propagate_rate()
794 struct clk *clkp; recalculate_root_clocks()
804 * clk_preinit - initialize any fields in the struct clk before clk init
805 * @clk: struct clk * to initialize
807 * Initialize any struct clk fields needed before normal clk initialization
810 void clk_preinit(struct clk *clk) clk_preinit() argument
812 INIT_LIST_HEAD(&clk->children); clk_preinit()
815 int clk_register(struct clk *clk) clk_register() argument
817 if (clk == NULL || IS_ERR(clk)) clk_register()
823 if (clk->node.next || clk->node.prev) clk_register()
827 if (clk->parent) clk_register()
828 list_add(&clk->sibling, &clk->parent->children); clk_register()
830 list_add(&clk->sibling, &root_clks); clk_register()
832 list_add(&clk->node, &clocks); clk_register()
833 if (clk->init) clk_register()
834 clk->init(clk); clk_register()
841 void clk_unregister(struct clk *clk) clk_unregister() argument
843 if (clk == NULL || IS_ERR(clk)) clk_unregister()
847 list_del(&clk->sibling); clk_unregister()
848 list_del(&clk->node); clk_unregister()
855 struct clk *clkp; clk_enable_init_clocks()
863 * omap_clk_get_by_name - locate OMAP struct clk by its name
864 * @name: name of the struct clk to locate
866 * Locate an OMAP struct clk by its name. Assumes that struct clk
868 * struct clk if found.
870 struct clk *omap_clk_get_by_name(const char *name) omap_clk_get_by_name()
872 struct clk *c; omap_clk_get_by_name()
873 struct clk *ret = NULL; omap_clk_get_by_name()
891 struct clk *c; omap_clk_enable_autoidle_all()
907 struct clk *c; omap_clk_disable_autoidle_all()
924 static int clkll_enable_null(struct clk *clk) clkll_enable_null() argument
929 static void clkll_disable_null(struct clk *clk) clkll_disable_null() argument
943 struct clk dummy_ck = {
958 struct clk *ck; clk_disable_unused()
993 struct clk *c; clk_dbg_show_summary()
994 struct clk *pa; clk_dbg_show_summary()
1023 static int clk_debugfs_register_one(struct clk *c) clk_debugfs_register_one()
1027 struct clk *pa = c->parent; clk_debugfs_register_one()
1056 static int clk_debugfs_register(struct clk *c) clk_debugfs_register()
1059 struct clk *pa = c->parent; clk_debugfs_register()
1077 struct clk *c; clk_debugfs_init()
|
| H A D | clock.h | 16 #include <linux/clk.h>
22 struct clk;
35 .clk = ck, \
48 #define __clk_get_name(clk) (clk->name)
49 #define __clk_get_parent(clk) (clk->parent)
50 #define __clk_get_rate(clk) (clk->rate)
57 * @find_companion: function returning the "companion" clk reg for the clock
61 * A "companion" clk is an accompanying clock to the one being queried
71 int (*enable)(struct clk *);
72 void (*disable)(struct clk *);
73 void (*find_idlest)(struct clk *, void __iomem **,
75 void (*find_companion)(struct clk *, void __iomem **,
77 void (*allow_idle)(struct clk *);
78 void (*deny_idle)(struct clk *);
82 * struct clk.flags possibilities
101 * struct clk - OMAP struct clk
105 * @parent: pointer to this clock's parent struct clk
107 * @sibling: list_head connecting this clk to its parent clk's @children
117 * @flags: see "struct clk.flags possibilities" above
141 struct clk { struct
145 struct clk *parent;
150 unsigned long (*recalc)(struct clk *);
151 int (*set_rate)(struct clk *, unsigned long);
152 long (*round_rate)(struct clk *, unsigned long);
153 void (*init)(struct clk *);
166 int (*clk_enable)(struct clk *clk);
167 void (*clk_disable)(struct clk *clk);
168 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
169 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
170 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
171 void (*clk_allow_idle)(struct clk *clk);
172 void (*clk_deny_idle)(struct clk *clk);
173 void (*clk_disable_unused)(struct clk *clk);
179 extern void clk_preinit(struct clk *clk);
180 extern int clk_register(struct clk *clk);
181 extern void clk_reparent(struct clk *child, struct clk *parent);
182 extern void clk_unregister(struct clk *clk);
183 extern void propagate_rate(struct clk *clk);
185 extern unsigned long followparent_recalc(struct clk *clk);
187 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
188 extern struct clk *omap_clk_get_by_name(const char *name);
194 extern struct clk dummy_ck;
198 extern int omap1_clk_enable(struct clk *clk);
199 extern void omap1_clk_disable(struct clk *clk);
200 extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
201 extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
202 extern unsigned long omap1_ckctl_recalc(struct clk *clk);
203 extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
204 extern unsigned long omap1_sossi_recalc(struct clk *clk);
205 extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
206 extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
207 extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
208 extern unsigned long omap1_uart_recalc(struct clk *clk);
209 extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
210 extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
211 extern void omap1_init_ext_clk(struct clk *clk);
212 extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
213 extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
214 extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
215 extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
216 extern unsigned long omap1_watchdog_recalc(struct clk *clk);
219 extern void omap1_clk_disable_unused(struct clk *clk);
225 struct clk clk; member in struct:uart_clk
231 struct clk clk; member in struct:arm_idlect1_clk
283 extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
|
| H A D | clock_data.c | 19 #include <linux/clk.h>
45 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
52 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
58 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
78 static struct clk ck_ref = {
84 static struct clk ck_dpll1 = {
95 .clk = {
108 static struct clk sossi_ck = {
111 .parent = &ck_dpll1out.clk,
119 static struct clk arm_ck = {
130 .clk = {
149 static struct clk arm_gpio_ck = {
160 .clk = {
173 .clk = {
186 .clk = {
199 static struct clk arminth_ck16xx = {
211 static struct clk dsp_ck = {
223 static struct clk dspmmu_ck = {
233 static struct clk dspper_ck = {
245 static struct clk dspxor_ck = {
254 static struct clk dsptim_ck = {
264 .clk = {
277 static struct clk arminth_ck1510 = {
280 .parent = &tc_ck.clk,
288 static struct clk tipb_ck = {
292 .parent = &tc_ck.clk,
296 static struct clk l3_ocpi_ck = {
300 .parent = &tc_ck.clk,
306 static struct clk tc1_ck = {
309 .parent = &tc_ck.clk,
319 static struct clk tc2_ck = {
322 .parent = &tc_ck.clk,
329 static struct clk dma_ck = {
333 .parent = &tc_ck.clk,
337 static struct clk dma_lcdfree_ck = {
340 .parent = &tc_ck.clk,
345 .clk = {
348 .parent = &tc_ck.clk,
358 .clk = {
361 .parent = &tc_ck.clk,
370 static struct clk rhea1_ck = {
373 .parent = &tc_ck.clk,
377 static struct clk rhea2_ck = {
380 .parent = &tc_ck.clk,
384 static struct clk lcd_ck_16xx = {
397 .clk = {
418 static struct clk uart1_1510 = {
422 .parent = &armper_ck.clk,
438 .clk = {
442 .parent = &armper_ck.clk,
457 static struct clk uart2_ck = {
461 .parent = &armper_ck.clk,
476 static struct clk uart3_1510 = {
480 .parent = &armper_ck.clk,
496 .clk = {
500 .parent = &armper_ck.clk,
509 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
519 static struct clk usb_hhc_ck1510 = {
529 static struct clk usb_hhc_ck16xx = {
540 static struct clk usb_dc_ck = {
549 static struct clk uart1_7xx = {
558 static struct clk uart2_7xx = {
567 static struct clk mclk_1510 = {
576 static struct clk mclk_16xx = {
587 static struct clk bclk_1510 = {
594 static struct clk bclk_16xx = {
605 static struct clk mmc1_ck = {
609 .parent = &armper_ck.clk,
620 static struct clk mmc2_ck = {
624 .parent = &armper_ck.clk,
631 static struct clk mmc3_ck = {
635 .parent = &armper_ck.clk,
642 static struct clk virtual_ck_mpu = {
653 static struct clk i2c_fck = {
657 .parent = &armxor_ck.clk,
661 static struct clk i2c_ick = {
665 .parent = &armper_ck.clk,
678 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
681 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
683 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
684 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
685 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
686 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
697 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
704 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
705 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
709 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
712 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
717 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
728 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
730 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
740 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
743 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
748 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
790 clk_preinit(c->lk.clk); omap1_clk_init()
807 clk_register(c->lk.clk); omap1_clk_init()
896 clk_enable(&armper_ck.clk); omap1_clk_init()
897 clk_enable(&armxor_ck.clk); omap1_clk_init()
898 clk_enable(&armtim_ck.clk); /* This should be done by timer code */ omap1_clk_init()
|
| /linux-4.1.27/arch/blackfin/mach-bf609/ |
| H A D | clock.c | 7 #include <linux/clk.h>
57 .clk = &_clk, \
82 printk(KERN_CRIT "fail to align clk\n"); wait_for_pll_align()
89 int clk_enable(struct clk *clk) clk_enable() argument
92 if (clk->ops && clk->ops->enable) clk_enable()
93 ret = clk->ops->enable(clk); clk_enable()
98 void clk_disable(struct clk *clk) clk_disable() argument
100 if (clk->ops && clk->ops->disable) clk_disable()
101 clk->ops->disable(clk); clk_disable()
106 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
109 if (clk->ops && clk->ops->get_rate) clk_get_rate()
110 ret = clk->ops->get_rate(clk); clk_get_rate()
115 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
118 if (clk->ops && clk->ops->round_rate) clk_round_rate()
119 ret = clk->ops->round_rate(clk, rate); clk_round_rate()
124 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
127 if (clk->ops && clk->ops->set_rate) clk_set_rate()
128 ret = clk->ops->set_rate(clk, rate); clk_set_rate()
133 unsigned long vco_get_rate(struct clk *clk) vco_get_rate() argument
135 return clk->rate; vco_get_rate()
138 unsigned long pll_get_rate(struct clk *clk) pll_get_rate() argument
148 clk->parent->rate = clk_get_rate(clk->parent); pll_get_rate()
149 return clk->parent->rate / (df + 1) * msel * 2; pll_get_rate()
152 unsigned long pll_round_rate(struct clk *clk, unsigned long rate) pll_round_rate() argument
155 div = rate / clk->parent->rate; pll_round_rate()
156 return clk->parent->rate * div; pll_round_rate()
159 int pll_set_rate(struct clk *clk, unsigned long rate) pll_set_rate() argument
169 msel = rate / clk->parent->rate / 2; pll_set_rate()
172 clk->rate = rate; pll_set_rate()
176 unsigned long cclk_get_rate(struct clk *clk) cclk_get_rate() argument
178 if (clk->parent) cclk_get_rate()
179 return clk->parent->rate; cclk_get_rate()
184 unsigned long sys_clk_get_rate(struct clk *clk) sys_clk_get_rate() argument
191 div = (div & clk->mask) >> clk->shift; sys_clk_get_rate()
195 if (!strcmp(clk->parent->name, "SYS_CLKIN")) { sys_clk_get_rate()
196 drate = clk->parent->rate / (df + 1); sys_clk_get_rate()
201 clk->parent->rate = clk_get_rate(clk->parent); sys_clk_get_rate()
202 return clk->parent->rate / div; sys_clk_get_rate()
206 unsigned long dummy_get_rate(struct clk *clk) dummy_get_rate() argument
208 clk->parent->rate = clk_get_rate(clk->parent); dummy_get_rate()
209 return clk->parent->rate; dummy_get_rate()
212 unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) sys_clk_round_rate() argument
223 max_rate = clk->parent->rate / (df + 1) * msel; sys_clk_round_rate()
228 for (i = 1; i < clk->mask; i++) { sys_clk_round_rate()
236 int sys_clk_set_rate(struct clk *clk, unsigned long rate) sys_clk_set_rate() argument
239 div = (div & clk->mask) >> clk->shift; sys_clk_set_rate()
241 rate = clk_round_rate(clk, rate); sys_clk_set_rate()
246 div = (clk_get_rate(clk) * div) / rate; sys_clk_set_rate()
250 clk_reg_write_mask(CGU0_DIV, div << clk->shift, sys_clk_set_rate()
251 clk->mask); sys_clk_set_rate()
252 clk->rate = rate; sys_clk_set_rate()
279 static struct clk sys_clkin = {
285 static struct clk pll_clk = {
293 static struct clk cclk = {
303 static struct clk cclk0 = {
309 static struct clk cclk1 = {
315 static struct clk sysclk = {
325 static struct clk sclk0 = {
334 static struct clk sclk1 = {
343 static struct clk dclk = {
352 static struct clk oclk = {
360 static struct clk ethclk = {
366 static struct clk ethpclk = {
372 static struct clk spiclk = {
397 struct clk *clkp; clk_init()
399 clkp = bf609_clks[i].clk; clk_init()
|
| /linux-4.1.27/arch/mips/loongson/lemote-2f/ |
| H A D | clock.c | 9 #include <linux/clk.h>
44 static struct clk cpu_clk = {
50 struct clk *clk_get(struct device *dev, const char *id) clk_get()
56 static void propagate_rate(struct clk *clk) propagate_rate() argument
58 struct clk *clkp; propagate_rate()
61 if (likely(clkp->parent != clk)) propagate_rate()
70 int clk_enable(struct clk *clk) clk_enable() argument
76 void clk_disable(struct clk *clk) clk_disable() argument
81 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
83 return (unsigned long)clk->rate; clk_get_rate()
87 void clk_put(struct clk *clk) clk_put() argument
92 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
99 if (likely(clk->ops && clk->ops->set_rate)) { clk_set_rate()
103 ret = clk->ops->set_rate(clk, rate, 0); clk_set_rate()
107 if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) clk_set_rate()
108 propagate_rate(clk); clk_set_rate()
116 clk->rate = rate; clk_set_rate()
126 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
128 if (likely(clk->ops && clk->ops->round_rate)) { clk_round_rate()
132 rounded = clk->ops->round_rate(clk, rate); clk_round_rate()
|
| /linux-4.1.27/arch/mips/lantiq/xway/ |
| H A D | clk.c | 11 #include <linux/clk.h>
19 #include "../clk.h"
58 unsigned long clk; ltq_danube_pp32_hz() local
62 clk = CLOCK_240M; ltq_danube_pp32_hz()
65 clk = CLOCK_222M; ltq_danube_pp32_hz()
68 clk = CLOCK_133M; ltq_danube_pp32_hz()
71 clk = CLOCK_266M; ltq_danube_pp32_hz()
75 return clk; ltq_danube_pp32_hz()
105 unsigned long clk; ltq_vr9_cpu_hz() local
111 clk = CLOCK_600M; ltq_vr9_cpu_hz()
114 clk = CLOCK_500M; ltq_vr9_cpu_hz()
117 clk = CLOCK_393M; ltq_vr9_cpu_hz()
120 clk = CLOCK_333M; ltq_vr9_cpu_hz()
124 clk = CLOCK_196_608M; ltq_vr9_cpu_hz()
127 clk = CLOCK_167M; ltq_vr9_cpu_hz()
132 clk = CLOCK_125M; ltq_vr9_cpu_hz()
135 clk = 0; ltq_vr9_cpu_hz()
139 return clk; ltq_vr9_cpu_hz()
145 unsigned long clk; ltq_vr9_fpi_hz() local
153 clk = cpu_clk; ltq_vr9_fpi_hz()
157 clk = cpu_clk / 2; ltq_vr9_fpi_hz()
161 clk = (cpu_clk * 2) / 5; ltq_vr9_fpi_hz()
165 clk = cpu_clk / 3; ltq_vr9_fpi_hz()
168 clk = 0; ltq_vr9_fpi_hz()
172 return clk; ltq_vr9_fpi_hz()
178 unsigned long clk; ltq_vr9_pp32_hz() local
182 clk = CLOCK_450M; ltq_vr9_pp32_hz()
185 clk = CLOCK_300M; ltq_vr9_pp32_hz()
188 clk = CLOCK_500M; ltq_vr9_pp32_hz()
192 return clk; ltq_vr9_pp32_hz()
|
| H A D | sysctrl.c | 18 #include "../clk.h"
109 static int cgu_enable(struct clk *clk) cgu_enable() argument
111 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); cgu_enable()
116 static void cgu_disable(struct clk *clk) cgu_disable() argument
118 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); cgu_disable()
122 static int pmu_enable(struct clk *clk) pmu_enable() argument
126 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, pmu_enable()
127 PWDCR(clk->module)); pmu_enable()
128 do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); pmu_enable()
137 static void pmu_disable(struct clk *clk) pmu_disable() argument
139 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, pmu_disable()
140 PWDCR(clk->module)); pmu_disable()
144 static int pci_enable(struct clk *clk) pci_enable() argument
151 if (clk->rate == CLOCK_33M) pci_enable()
157 if (clk->rate == CLOCK_33M) pci_enable()
163 pmu_enable(clk); pci_enable()
168 static int pci_ext_enable(struct clk *clk) pci_ext_enable() argument
176 static void pci_ext_disable(struct clk *clk) pci_ext_disable() argument
183 static int clkout_enable(struct clk *clk) clkout_enable() argument
189 if (clk->rates[i] == clk->rate) { clkout_enable()
190 int shift = 14 - (2 * clk->module); clkout_enable()
191 int enable = 7 - clk->module; clkout_enable()
208 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_pmu() local
210 clk->cl.dev_id = dev; clkdev_add_pmu()
211 clk->cl.con_id = con; clkdev_add_pmu()
212 clk->cl.clk = clk; clkdev_add_pmu()
213 clk->enable = pmu_enable; clkdev_add_pmu()
214 clk->disable = pmu_disable; clkdev_add_pmu()
215 clk->module = module; clkdev_add_pmu()
216 clk->bits = bits; clkdev_add_pmu()
217 clkdev_add(&clk->cl); clkdev_add_pmu()
224 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_cgu() local
226 clk->cl.dev_id = dev; clkdev_add_cgu()
227 clk->cl.con_id = con; clkdev_add_cgu()
228 clk->cl.clk = clk; clkdev_add_cgu()
229 clk->enable = cgu_enable; clkdev_add_cgu()
230 clk->disable = cgu_disable; clkdev_add_cgu()
231 clk->bits = bits; clkdev_add_cgu()
232 clkdev_add(&clk->cl); clkdev_add_cgu()
240 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_pci() local
241 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_pci()
244 clk->cl.dev_id = "17000000.pci"; clkdev_add_pci()
245 clk->cl.con_id = NULL; clkdev_add_pci()
246 clk->cl.clk = clk; clkdev_add_pci()
247 clk->rate = CLOCK_33M; clkdev_add_pci()
248 clk->rates = valid_pci_rates; clkdev_add_pci()
249 clk->enable = pci_enable; clkdev_add_pci()
250 clk->disable = pmu_disable; clkdev_add_pci()
251 clk->module = 0; clkdev_add_pci()
252 clk->bits = PMU_PCI; clkdev_add_pci()
253 clkdev_add(&clk->cl); clkdev_add_pci()
258 clk_ext->cl.clk = clk_ext; clkdev_add_pci()
277 struct clk *clk; clkdev_add_clkout() local
283 clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_clkout()
284 clk->cl.dev_id = "1f103000.cgu"; clkdev_add_clkout()
285 clk->cl.con_id = name; clkdev_add_clkout()
286 clk->cl.clk = clk; clkdev_add_clkout()
287 clk->rate = 0; clkdev_add_clkout()
288 clk->rates = valid_clkout_rates[i]; clkdev_add_clkout()
289 clk->enable = clkout_enable; clkdev_add_clkout()
290 clk->module = i; clkdev_add_clkout()
291 clkdev_add(&clk->cl); clkdev_add_clkout()
|
| H A D | Makefile | 1 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
|
| H A D | gptu.c | 17 #include "../clk.h"
96 static int gptu_enable(struct clk *clk) gptu_enable() argument
98 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, gptu_enable()
106 GPTU_CON(clk->bits)); gptu_enable()
107 gptu_w32(1, GPTU_RLD(clk->bits)); gptu_enable()
108 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); gptu_enable()
109 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); gptu_enable()
113 static void gptu_disable(struct clk *clk) gptu_disable() argument
115 gptu_w32(0, GPTU_RUN(clk->bits)); gptu_disable()
116 gptu_w32(0, GPTU_CON(clk->bits)); gptu_disable()
117 gptu_w32(0, GPTU_RLD(clk->bits)); gptu_disable()
118 gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); gptu_disable()
119 free_irq(irqres[clk->bits].start, NULL); gptu_disable()
125 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_gptu() local
127 clk->cl.dev_id = dev_name(dev); clkdev_add_gptu()
128 clk->cl.con_id = con; clkdev_add_gptu()
129 clk->cl.clk = clk; clkdev_add_gptu()
130 clk->enable = gptu_enable; clkdev_add_gptu()
131 clk->disable = gptu_disable; clkdev_add_gptu()
132 clk->bits = timer; clkdev_add_gptu()
133 clkdev_add(&clk->cl); clkdev_add_gptu()
138 struct clk *clk; gptu_probe() local
154 clk = clk_get(&pdev->dev, NULL); gptu_probe()
155 if (IS_ERR(clk)) { gptu_probe()
159 clk_enable(clk); gptu_probe()
168 clk_disable(clk); gptu_probe()
169 clk_put(clk); gptu_probe()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 24 #include <subdev/clk.h>
40 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, nvkm_clk_adjust() argument
43 struct nvkm_bios *bios = nvkm_bios(clk); nvkm_clk_adjust()
78 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) nvkm_cstate_prog() argument
80 struct nvkm_therm *ptherm = nvkm_therm(clk); nvkm_cstate_prog()
81 struct nvkm_volt *volt = nvkm_volt(clk); nvkm_cstate_prog()
94 nv_error(clk, "failed to raise fan speed: %d\n", ret); nvkm_cstate_prog()
102 nv_error(clk, "failed to raise voltage: %d\n", ret); nvkm_cstate_prog()
107 ret = clk->calc(clk, cstate); nvkm_cstate_prog()
109 ret = clk->prog(clk); nvkm_cstate_prog()
110 clk->tidy(clk); nvkm_cstate_prog()
116 nv_error(clk, "failed to lower voltage: %d\n", ret); nvkm_cstate_prog()
122 nv_error(clk, "failed to lower fan speed: %d\n", ret); nvkm_cstate_prog()
136 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) nvkm_cstate_new() argument
138 struct nvkm_bios *bios = nvkm_bios(clk); nvkm_cstate_new()
139 struct nvkm_domain *domain = clk->domains; nvkm_cstate_new()
158 u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, nvkm_cstate_new()
173 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) nvkm_pstate_prog() argument
175 struct nvkm_fb *pfb = nvkm_fb(clk); nvkm_pstate_prog()
179 list_for_each_entry(pstate, &clk->states, head) { nvkm_pstate_prog()
184 nv_debug(clk, "setting performance state %d\n", pstatei); nvkm_pstate_prog()
185 clk->pstate = pstatei; nvkm_pstate_prog()
197 return nvkm_cstate_prog(clk, pstate, 0); nvkm_pstate_prog()
203 struct nvkm_clk *clk = container_of(work, typeof(*clk), work); nvkm_pstate_work() local
206 if (!atomic_xchg(&clk->waiting, 0)) nvkm_pstate_work()
208 clk->pwrsrc = power_supply_is_system_supplied(); nvkm_pstate_work()
210 nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", nvkm_pstate_work()
211 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, nvkm_pstate_work()
212 clk->astate, clk->tstate, clk->dstate); nvkm_pstate_work()
214 pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; nvkm_pstate_work()
215 if (clk->state_nr && pstate != -1) { nvkm_pstate_work()
216 pstate = (pstate < 0) ? clk->astate : pstate; nvkm_pstate_work()
217 pstate = min(pstate, clk->state_nr - 1 - clk->tstate); nvkm_pstate_work()
218 pstate = max(pstate, clk->dstate); nvkm_pstate_work()
220 pstate = clk->pstate = -1; nvkm_pstate_work()
223 nv_trace(clk, "-> %d\n", pstate); nvkm_pstate_work()
224 if (pstate != clk->pstate) { nvkm_pstate_work()
225 int ret = nvkm_pstate_prog(clk, pstate); nvkm_pstate_work()
227 nv_error(clk, "error setting pstate %d: %d\n", nvkm_pstate_work()
232 wake_up_all(&clk->wait); nvkm_pstate_work()
233 nvkm_notify_get(&clk->pwrsrc_ntfy); nvkm_pstate_work()
237 nvkm_pstate_calc(struct nvkm_clk *clk, bool wait) nvkm_pstate_calc() argument
239 atomic_set(&clk->waiting, 1); nvkm_pstate_calc()
240 schedule_work(&clk->work); nvkm_pstate_calc()
242 wait_event(clk->wait, !atomic_read(&clk->waiting)); nvkm_pstate_calc()
247 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) nvkm_pstate_info() argument
249 struct nvkm_domain *clock = clk->domains - 1; nvkm_pstate_info()
264 nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); nvkm_pstate_info()
269 nv_debug(clk, "%10d KHz\n", freq); nvkm_pstate_info()
285 nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); nvkm_pstate_info()
302 nvkm_pstate_new(struct nvkm_clk *clk, int idx) nvkm_pstate_new() argument
304 struct nvkm_bios *bios = nvkm_bios(clk); nvkm_pstate_new()
305 struct nvkm_domain *domain = clk->domains - 1; nvkm_pstate_new()
344 perfS.v40.freq = nvkm_clk_adjust(clk, false, nvkm_pstate_new()
357 nvkm_cstate_new(clk, idx, pstate); nvkm_pstate_new()
361 nvkm_pstate_info(clk, pstate); nvkm_pstate_new()
362 list_add_tail(&pstate->head, &clk->states); nvkm_pstate_new()
363 clk->state_nr++; nvkm_pstate_new()
371 nvkm_clk_ustate_update(struct nvkm_clk *clk, int req) nvkm_clk_ustate_update() argument
376 if (!clk->allow_reclock) nvkm_clk_ustate_update()
380 list_for_each_entry(pstate, &clk->states, head) { nvkm_clk_ustate_update()
395 nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) nvkm_clk_nstate() argument
399 if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) nvkm_clk_nstate()
408 ret = nvkm_clk_ustate_update(clk, v); nvkm_clk_nstate()
419 nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr) nvkm_clk_ustate() argument
421 int ret = nvkm_clk_ustate_update(clk, req); nvkm_clk_ustate()
423 if (ret -= 2, pwr) clk->ustate_ac = ret; nvkm_clk_ustate()
424 else clk->ustate_dc = ret; nvkm_clk_ustate()
425 return nvkm_pstate_calc(clk, true); nvkm_clk_ustate()
431 nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait) nvkm_clk_astate() argument
433 if (!rel) clk->astate = req; nvkm_clk_astate()
434 if ( rel) clk->astate += rel; nvkm_clk_astate()
435 clk->astate = min(clk->astate, clk->state_nr - 1); nvkm_clk_astate()
436 clk->astate = max(clk->astate, 0); nvkm_clk_astate()
437 return nvkm_pstate_calc(clk, wait); nvkm_clk_astate()
441 nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel) nvkm_clk_tstate() argument
443 if (!rel) clk->tstate = req; nvkm_clk_tstate()
444 if ( rel) clk->tstate += rel; nvkm_clk_tstate()
445 clk->tstate = min(clk->tstate, 0); nvkm_clk_tstate()
446 clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); nvkm_clk_tstate()
447 return nvkm_pstate_calc(clk, true); nvkm_clk_tstate()
451 nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel) nvkm_clk_dstate() argument
453 if (!rel) clk->dstate = req; nvkm_clk_dstate()
454 if ( rel) clk->dstate += rel; nvkm_clk_dstate()
455 clk->dstate = min(clk->dstate, clk->state_nr - 1); nvkm_clk_dstate()
456 clk->dstate = max(clk->dstate, 0); nvkm_clk_dstate()
457 return nvkm_pstate_calc(clk, true); nvkm_clk_dstate()
463 struct nvkm_clk *clk = nvkm_clk_pwrsrc() local
464 container_of(notify, typeof(*clk), pwrsrc_ntfy); nvkm_clk_pwrsrc()
465 nvkm_pstate_calc(clk, false); nvkm_clk_pwrsrc()
476 struct nvkm_clk *clk = (void *)object; _nvkm_clk_fini() local
477 nvkm_notify_put(&clk->pwrsrc_ntfy); _nvkm_clk_fini()
478 return nvkm_subdev_fini(&clk->base, suspend); _nvkm_clk_fini()
484 struct nvkm_clk *clk = (void *)object; _nvkm_clk_init() local
485 struct nvkm_domain *clock = clk->domains; _nvkm_clk_init()
488 ret = nvkm_subdev_init(&clk->base); _nvkm_clk_init()
492 memset(&clk->bstate, 0x00, sizeof(clk->bstate)); _nvkm_clk_init()
493 INIT_LIST_HEAD(&clk->bstate.list); _nvkm_clk_init()
494 clk->bstate.pstate = 0xff; _nvkm_clk_init()
497 ret = clk->read(clk, clock->name); _nvkm_clk_init()
499 nv_error(clk, "%02x freq unknown\n", clock->name); _nvkm_clk_init()
502 clk->bstate.base.domain[clock->name] = ret; _nvkm_clk_init()
506 nvkm_pstate_info(clk, &clk->bstate); _nvkm_clk_init()
508 clk->astate = clk->state_nr - 1; _nvkm_clk_init()
509 clk->tstate = 0; _nvkm_clk_init()
510 clk->dstate = 0; _nvkm_clk_init()
511 clk->pstate = -1; _nvkm_clk_init()
512 nvkm_pstate_calc(clk, true); _nvkm_clk_init()
519 struct nvkm_clk *clk = (void *)object; _nvkm_clk_dtor() local
522 nvkm_notify_fini(&clk->pwrsrc_ntfy); _nvkm_clk_dtor()
524 list_for_each_entry_safe(pstate, temp, &clk->states, head) { _nvkm_clk_dtor()
528 nvkm_subdev_destroy(&clk->base); _nvkm_clk_dtor()
538 struct nvkm_clk *clk; nvkm_clk_create_() local
544 clk = *object; nvkm_clk_create_()
548 INIT_LIST_HEAD(&clk->states); nvkm_clk_create_()
549 clk->domains = clocks; nvkm_clk_create_()
550 clk->ustate_ac = -1; nvkm_clk_create_()
551 clk->ustate_dc = -1; nvkm_clk_create_()
553 INIT_WORK(&clk->work, nvkm_pstate_work); nvkm_clk_create_()
554 init_waitqueue_head(&clk->wait); nvkm_clk_create_()
555 atomic_set(&clk->waiting, 0); nvkm_clk_create_()
561 ret = nvkm_pstate_new(clk, idx++); nvkm_clk_create_()
565 list_add_tail(&pstates[idx].head, &clk->states); nvkm_clk_create_()
566 clk->state_nr = nb_pstates; nvkm_clk_create_()
569 clk->allow_reclock = allow_reclock; nvkm_clk_create_()
572 NULL, 0, 0, &clk->pwrsrc_ntfy); nvkm_clk_create_()
578 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_create_()
579 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_create_()
584 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_create_()
588 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_create_()
|
| H A D | gt215.h | 3 #include <subdev/clk.h>
6 u32 clk; member in struct:gt215_clk_info
16 int gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags);
17 void gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags);
|
| H A D | mcp77.c | 42 read_div(struct nvkm_clk *clk) read_div() argument
44 return nv_rd32(clk, 0x004600); read_div()
48 read_pll(struct nvkm_clk *clk, u32 base) read_pll() argument
50 u32 ctrl = nv_rd32(clk, base + 0); read_pll()
51 u32 coef = nv_rd32(clk, base + 4); read_pll()
52 u32 ref = clk->read(clk, nv_clk_src_href); read_pll()
59 post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); read_pll()
62 post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; read_pll()
79 mcp77_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) mcp77_clk_read() argument
81 struct mcp77_clk_priv *priv = (void *)clk; mcp77_clk_read()
82 u32 mast = nv_rd32(clk, 0x00c054); mcp77_clk_read()
91 return clk->read(clk, nv_clk_src_href) * 4; mcp77_clk_read()
93 return clk->read(clk, nv_clk_src_href) * 2 / 3; mcp77_clk_read()
96 case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3); mcp77_clk_read()
98 case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4); mcp77_clk_read()
99 case 0x000c0000: return clk->read(clk, nv_clk_src_cclk); mcp77_clk_read()
103 P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; mcp77_clk_read()
106 case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; mcp77_clk_read()
108 case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P; mcp77_clk_read()
109 case 0x00000003: return read_pll(clk, 0x004028) >> P; mcp77_clk_read()
114 return clk->read(clk, nv_clk_src_core); mcp77_clk_read()
117 return clk->read(clk, nv_clk_src_core); mcp77_clk_read()
120 case 0x00000000: return clk->read(clk, nv_clk_src_href); mcp77_clk_read()
121 case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4); mcp77_clk_read()
122 case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3); mcp77_clk_read()
126 P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; mcp77_clk_read()
130 return clk->read(clk, nv_clk_src_href) >> P; mcp77_clk_read()
131 return clk->read(clk, nv_clk_src_crystal) >> P; mcp77_clk_read()
133 case 0x00000020: return read_pll(clk, 0x004028) >> P; mcp77_clk_read()
134 case 0x00000030: return read_pll(clk, 0x004020) >> P; mcp77_clk_read()
141 P = (read_div(clk) & 0x00000700) >> 8; mcp77_clk_read()
145 return clk->read(clk, nv_clk_src_core) >> P; mcp77_clk_read()
166 struct nvkm_clk *clk = &priv->base; calc_pll() local
174 pll.refclk = clk->read(clk, nv_clk_src_href); calc_pll()
200 mcp77_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) mcp77_clk_calc() argument
202 struct mcp77_clk_priv *priv = (void *)clk; mcp77_clk_calc()
211 if (core < clk->read(clk, nv_clk_src_hclkm4)) mcp77_clk_calc()
212 out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs); mcp77_clk_calc()
238 if (shader == clk->read(clk, nv_clk_src_href)) { mcp77_clk_calc()
295 mcp77_clk_prog(struct nvkm_clk *clk) mcp77_clk_prog() argument
297 struct mcp77_clk_priv *priv = (void *)clk; mcp77_clk_prog()
303 ret = gt215_clk_pre(clk, f); mcp77_clk_prog()
308 mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); mcp77_clk_prog()
314 nv_mask(clk, 0x4028, 0x00070000, priv->cctrl); mcp77_clk_prog()
318 nv_wr32(clk, 0x402c, priv->ccoef); mcp77_clk_prog()
319 nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl); mcp77_clk_prog()
320 nv_wr32(clk, 0x4040, priv->cpost); mcp77_clk_prog()
331 nv_mask(clk, 0x4020, 0x00070000, 0x00000000); mcp77_clk_prog()
335 nv_mask(clk, 0x4020, 0x00070000, priv->sctrl); mcp77_clk_prog()
339 nv_wr32(clk, 0x4024, priv->scoef); mcp77_clk_prog()
340 nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl); mcp77_clk_prog()
341 nv_wr32(clk, 0x4070, priv->spost); mcp77_clk_prog()
350 if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { mcp77_clk_prog()
359 nv_wr32(clk, 0x4600, priv->vdiv); mcp77_clk_prog()
362 nv_wr32(clk, 0xc054, mast); mcp77_clk_prog()
367 nv_wr32(clk, 0x4040, 0x00000000); mcp77_clk_prog()
368 nv_mask(clk, 0x4028, 0x80000000, 0x00000000); mcp77_clk_prog()
372 nv_wr32(clk, 0x4070, 0x00000000); mcp77_clk_prog()
373 nv_mask(clk, 0x4020, 0x80000000, 0x00000000); mcp77_clk_prog()
380 gt215_clk_post(clk, f); mcp77_clk_prog()
385 mcp77_clk_tidy(struct nvkm_clk *clk) mcp77_clk_tidy() argument
|
| H A D | gf100.c | 24 #include <subdev/clk.h>
51 struct nvkm_clk *clk = &priv->base; read_vco() local
54 return clk->read(clk, nv_clk_src_sppll0); read_vco()
55 return clk->read(clk, nv_clk_src_sppll1); read_vco()
61 struct nvkm_clk *clk = &priv->base; read_pll() local
79 sclk = clk->read(clk, nv_clk_src_mpllsrc); read_pll()
82 sclk = clk->read(clk, nv_clk_src_mpllsrcref); read_pll()
124 read_clk(struct gf100_clk_priv *priv, int clk) read_clk() argument
126 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); read_clk()
130 if (ssel & (1 << clk)) { read_clk()
131 if (clk < 7) read_clk()
132 sclk = read_pll(priv, 0x137000 + (clk * 0x20)); read_clk()
137 sclk = read_div(priv, clk, 0x137160, 0x1371d0); read_clk()
148 gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) gf100_clk_read() argument
150 struct nvkm_device *device = nv_device(clk); gf100_clk_read()
151 struct gf100_clk_priv *priv = (void *)clk; gf100_clk_read()
173 return clk->read(clk, nv_clk_src_mpll); gf100_clk_read()
174 return clk->read(clk, nv_clk_src_mdiv); gf100_clk_read()
193 nv_error(clk, "invalid clock source %d\n", src); gf100_clk_read()
199 calc_div(struct gf100_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) calc_div() argument
210 calc_src(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) calc_src() argument
232 sclk = read_vco(priv, 0x137160 + (clk * 4)); calc_src()
233 if (clk < 7) calc_src()
234 sclk = calc_div(priv, clk, sclk, freq, ddiv); calc_src()
239 calc_pll(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *coef) calc_pll() argument
245 ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); calc_pll()
249 limits.refclk = read_div(priv, clk, 0x137120, 0x137140); calc_pll()
263 struct nvkm_cstate *cstate, int clk, int dom) calc_clk()
265 struct gf100_clk_info *info = &priv->eng[clk]; calc_clk()
275 clk0 = calc_src(priv, clk, freq, &src0, &div0); calc_clk()
276 clk0 = calc_div(priv, clk, clk0, freq, &div1D); calc_clk()
279 if (clk0 != freq && (0x00004387 & (1 << clk))) { calc_clk()
280 if (clk <= 7) calc_clk()
281 clk1 = calc_pll(priv, clk, freq, &info->coef); calc_clk()
284 clk1 = calc_div(priv, clk, clk1, freq, &div1P); calc_clk()
306 info->ssel = (1 << clk); calc_clk()
314 gf100_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) gf100_clk_calc() argument
316 struct gf100_clk_priv *priv = (void *)clk; gf100_clk_calc()
333 gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk) gf100_clk_prog_0() argument
335 struct gf100_clk_info *info = &priv->eng[clk]; gf100_clk_prog_0()
336 if (clk < 7 && !info->ssel) { gf100_clk_prog_0()
337 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); gf100_clk_prog_0()
338 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); gf100_clk_prog_0()
343 gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk) gf100_clk_prog_1() argument
345 nv_mask(priv, 0x137100, (1 << clk), 0x00000000); gf100_clk_prog_1()
346 nv_wait(priv, 0x137100, (1 << clk), 0x00000000); gf100_clk_prog_1()
350 gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk) gf100_clk_prog_2() argument
352 struct gf100_clk_info *info = &priv->eng[clk]; gf100_clk_prog_2()
353 const u32 addr = 0x137000 + (clk * 0x20); gf100_clk_prog_2()
354 if (clk <= 7) { gf100_clk_prog_2()
367 gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk) gf100_clk_prog_3() argument
369 struct gf100_clk_info *info = &priv->eng[clk]; gf100_clk_prog_3()
371 nv_mask(priv, 0x137100, (1 << clk), info->ssel); gf100_clk_prog_3()
372 nv_wait(priv, 0x137100, (1 << clk), info->ssel); gf100_clk_prog_3()
377 gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk) gf100_clk_prog_4() argument
379 struct gf100_clk_info *info = &priv->eng[clk]; gf100_clk_prog_4()
380 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); gf100_clk_prog_4()
384 gf100_clk_prog(struct nvkm_clk *clk) gf100_clk_prog() argument
386 struct gf100_clk_priv *priv = (void *)clk; gf100_clk_prog()
410 gf100_clk_tidy(struct nvkm_clk *clk) gf100_clk_tidy() argument
412 struct gf100_clk_priv *priv = (void *)clk; gf100_clk_tidy()
262 calc_clk(struct gf100_clk_priv *priv, struct nvkm_cstate *cstate, int clk, int dom) calc_clk() argument
|
| H A D | nv50.c | 54 struct nvkm_clk *clk = &priv->base; read_pll_src() local
55 u32 coef, ref = clk->read(clk, nv_clk_src_crystal); read_pll_src()
102 case 1: return clk->read(clk, nv_clk_src_crystal); read_pll_src()
103 case 2: return clk->read(clk, nv_clk_src_href); read_pll_src()
126 struct nvkm_clk *clk = &priv->base; read_pll_ref() local
143 return clk->read(clk, nv_clk_src_crystal); read_pll_ref()
150 return clk->read(clk, nv_clk_src_href); read_pll_ref()
158 struct nvkm_clk *clk = &priv->base; read_pll() local
169 return clk->read(clk, nv_clk_src_dom6); read_pll()
190 nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) nv50_clk_read() argument
192 struct nv50_clk_priv *priv = (void *)clk; nv50_clk_read()
202 return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); nv50_clk_read()
204 return clk->read(clk, nv_clk_src_hclk) * 3; nv50_clk_read()
206 return clk->read(clk, nv_clk_src_hclk) * 3 / 2; nv50_clk_read()
209 case 0x00000000: return clk->read(clk, nv_clk_src_href); nv50_clk_read()
212 case 0x30000000: return clk->read(clk, nv_clk_src_hclk); nv50_clk_read()
219 case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; nv50_clk_read()
220 case 0x00000001: return clk->read(clk, nv_clk_src_dom6); nv50_clk_read()
230 return clk->read(clk, nv_clk_src_host) >> P; nv50_clk_read()
231 return clk->read(clk, nv_clk_src_crystal) >> P; nv50_clk_read()
242 return clk->read(clk, nv_clk_src_crystal) >> P; nv50_clk_read()
245 return clk->read(clk, nv_clk_src_href) >> P; nv50_clk_read()
263 return clk->read(clk, nv_clk_src_core) >> P; nv50_clk_read()
264 return clk->read(clk, nv_clk_src_crystal) >> P; nv50_clk_read()
272 return clk->read(clk, nv_clk_src_core) >> P; nv50_clk_read()
278 return clk->read(clk, nv_clk_src_core) >> P; nv50_clk_read()
282 return clk->read(clk, nv_clk_src_hclkm3d2) >> P; nv50_clk_read()
284 return clk->read(clk, nv_clk_src_mem) >> P; nv50_clk_read()
302 case 0x00000000: return clk->read(clk, nv_clk_src_href); nv50_clk_read()
304 case 0x08000000: return clk->read(clk, nv_clk_src_hclk); nv50_clk_read()
306 return clk->read(clk, nv_clk_src_hclkm3) >> P; nv50_clk_read()
321 calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) calc_pll() argument
336 return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); calc_pll()
364 nv50_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) nv50_clk_calc() argument
366 struct nv50_clk_priv *priv = (void *)clk; nv50_clk_calc()
378 out = clk_init(hwsq, nv_subdev(clk)); nv50_clk_calc()
399 out = clk->read(clk, nv_clk_src_hclkm3d2); nv50_clk_calc()
420 if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { nv50_clk_calc()
423 if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { nv50_clk_calc()
426 freq = clk->read(clk, nv_clk_src_hclk) * 3; nv50_clk_calc()
489 nv50_clk_prog(struct nvkm_clk *clk) nv50_clk_prog() argument
491 struct nv50_clk_priv *priv = (void *)clk; nv50_clk_prog()
496 nv50_clk_tidy(struct nvkm_clk *clk) nv50_clk_tidy() argument
498 struct nv50_clk_priv *priv = (void *)clk; nv50_clk_tidy()
|
| H A D | gk104.c | 24 #include <subdev/clk.h>
141 read_clk(struct gk104_clk_priv *priv, int clk) read_clk() argument
143 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); read_clk()
146 if (clk < 7) { read_clk()
148 if (ssel & (1 << clk)) { read_clk()
149 sclk = read_pll(priv, 0x137000 + (clk * 0x20)); read_clk()
152 sclk = read_div(priv, clk, 0x137160, 0x1371d0); read_clk()
156 u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); read_clk()
158 sclk = read_div(priv, clk, 0x137160, 0x1371d0); read_clk()
167 sclk = read_div(priv, clk, 0x137160, 0x1371d0); read_clk()
184 gk104_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) gk104_clk_read() argument
186 struct nvkm_device *device = nv_device(clk); gk104_clk_read()
187 struct gk104_clk_priv *priv = (void *)clk; gk104_clk_read()
211 nv_error(clk, "invalid clock source %d\n", src); gk104_clk_read()
217 calc_div(struct gk104_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) calc_div() argument
228 calc_src(struct gk104_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) calc_src() argument
250 sclk = read_vco(priv, 0x137160 + (clk * 4)); calc_src()
251 if (clk < 7) calc_src()
252 sclk = calc_div(priv, clk, sclk, freq, ddiv); calc_src()
257 calc_pll(struct gk104_clk_priv *priv, int clk, u32 freq, u32 *coef) calc_pll() argument
263 ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); calc_pll()
267 limits.refclk = read_div(priv, clk, 0x137120, 0x137140); calc_pll()
281 struct nvkm_cstate *cstate, int clk, int dom) calc_clk()
283 struct gk104_clk_info *info = &priv->eng[clk]; calc_clk()
293 clk0 = calc_src(priv, clk, freq, &src0, &div0); calc_clk()
294 clk0 = calc_div(priv, clk, clk0, freq, &div1D); calc_clk()
297 if (clk0 != freq && (0x0000ff87 & (1 << clk))) { calc_clk()
298 if (clk <= 7) calc_clk()
299 clk1 = calc_pll(priv, clk, freq, &info->coef); calc_clk()
302 clk1 = calc_div(priv, clk, clk1, freq, &div1P); calc_clk()
323 info->ssel = (1 << clk); calc_clk()
332 gk104_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) gk104_clk_calc() argument
334 struct gk104_clk_priv *priv = (void *)clk; gk104_clk_calc()
350 gk104_clk_prog_0(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_0() argument
352 struct gk104_clk_info *info = &priv->eng[clk]; gk104_clk_prog_0()
354 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); gk104_clk_prog_0()
355 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); gk104_clk_prog_0()
360 gk104_clk_prog_1_0(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_1_0() argument
362 nv_mask(priv, 0x137100, (1 << clk), 0x00000000); gk104_clk_prog_1_0()
363 nv_wait(priv, 0x137100, (1 << clk), 0x00000000); gk104_clk_prog_1_0()
367 gk104_clk_prog_1_1(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_1_1() argument
369 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); gk104_clk_prog_1_1()
373 gk104_clk_prog_2(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_2() argument
375 struct gk104_clk_info *info = &priv->eng[clk]; gk104_clk_prog_2()
376 const u32 addr = 0x137000 + (clk * 0x20); gk104_clk_prog_2()
388 gk104_clk_prog_3(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_3() argument
390 struct gk104_clk_info *info = &priv->eng[clk]; gk104_clk_prog_3()
392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); gk104_clk_prog_3()
394 nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); gk104_clk_prog_3()
398 gk104_clk_prog_4_0(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_4_0() argument
400 struct gk104_clk_info *info = &priv->eng[clk]; gk104_clk_prog_4_0()
402 nv_mask(priv, 0x137100, (1 << clk), info->ssel); gk104_clk_prog_4_0()
403 nv_wait(priv, 0x137100, (1 << clk), info->ssel); gk104_clk_prog_4_0()
408 gk104_clk_prog_4_1(struct gk104_clk_priv *priv, int clk) gk104_clk_prog_4_1() argument
410 struct gk104_clk_info *info = &priv->eng[clk]; gk104_clk_prog_4_1()
412 nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); gk104_clk_prog_4_1()
413 nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); gk104_clk_prog_4_1()
418 gk104_clk_prog(struct nvkm_clk *clk) gk104_clk_prog() argument
420 struct gk104_clk_priv *priv = (void *)clk; gk104_clk_prog()
449 gk104_clk_tidy(struct nvkm_clk *clk) gk104_clk_tidy() argument
451 struct gk104_clk_priv *priv = (void *)clk; gk104_clk_tidy()
280 calc_clk(struct gk104_clk_priv *priv, struct nvkm_cstate *cstate, int clk, int dom) calc_clk() argument
|
| /linux-4.1.27/drivers/clk/ |
| H A D | clk.c | 9 * Standard functionality for the common clock API. See Documentation/clk.txt
12 #include <linux/clk-provider.h>
13 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
40 static long clk_core_get_accuracy(struct clk_core *clk);
41 static unsigned long clk_core_get_rate(struct clk_core *clk);
42 static int clk_core_get_phase(struct clk_core *clk);
43 static bool clk_core_is_prepared(struct clk_core *clk);
44 static bool clk_core_is_enabled(struct clk_core *clk);
81 #include <trace/events/clk.h>
83 struct clk { struct
297 static int clk_debug_create_one(struct clk_core *clk, struct dentry *pdentry) clk_debug_create_one() argument
302 if (!clk || !pdentry) { clk_debug_create_one()
307 d = debugfs_create_dir(clk->name, pdentry); clk_debug_create_one()
311 clk->dentry = d; clk_debug_create_one()
313 d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry, clk_debug_create_one()
314 (u32 *)&clk->rate); clk_debug_create_one()
318 d = debugfs_create_u32("clk_accuracy", S_IRUGO, clk->dentry, clk_debug_create_one()
319 (u32 *)&clk->accuracy); clk_debug_create_one()
323 d = debugfs_create_u32("clk_phase", S_IRUGO, clk->dentry, clk_debug_create_one()
324 (u32 *)&clk->phase); clk_debug_create_one()
328 d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry, clk_debug_create_one()
329 (u32 *)&clk->flags); clk_debug_create_one()
333 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry, clk_debug_create_one()
334 (u32 *)&clk->prepare_count); clk_debug_create_one()
338 d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry, clk_debug_create_one()
339 (u32 *)&clk->enable_count); clk_debug_create_one()
343 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry, clk_debug_create_one()
344 (u32 *)&clk->notifier_count); clk_debug_create_one()
348 if (clk->ops->debug_init) { clk_debug_create_one()
349 ret = clk->ops->debug_init(clk->hw, clk->dentry); clk_debug_create_one()
358 debugfs_remove_recursive(clk->dentry); clk_debug_create_one()
359 clk->dentry = NULL; clk_debug_create_one()
365 * clk_debug_register - add a clk node to the debugfs clk tree
366 * @clk: the clk being added to the debugfs clk tree
368 * Dynamically adds a clk to the debugfs clk tree if debugfs has been
369 * initialized. Otherwise it bails out early since the debugfs clk tree
372 static int clk_debug_register(struct clk_core *clk) clk_debug_register() argument
377 hlist_add_head(&clk->debug_node, &clk_debug_list); clk_debug_register()
382 ret = clk_debug_create_one(clk, rootdir); clk_debug_register()
390 * clk_debug_unregister - remove a clk node from the debugfs clk tree
391 * @clk: the clk being removed from the debugfs clk tree
393 * Dynamically removes a clk and all it's children clk nodes from the
394 * debugfs clk tree if clk->dentry points to debugfs created by
397 static void clk_debug_unregister(struct clk_core *clk) clk_debug_unregister() argument
400 hlist_del_init(&clk->debug_node); clk_debug_unregister()
401 debugfs_remove_recursive(clk->dentry); clk_debug_unregister()
402 clk->dentry = NULL; clk_debug_unregister()
420 * clk_debug_init - lazily create the debugfs clk tree visualization
424 * clk_debug_init walks the clk tree hierarchy while holding
427 * represented in the debugfs clk tree. This function should only be
433 struct clk_core *clk; clk_debug_init() local
436 rootdir = debugfs_create_dir("clk", NULL); clk_debug_init()
462 hlist_for_each_entry(clk, &clk_debug_list, debug_node) clk_debug_init()
463 clk_debug_create_one(clk, rootdir); clk_debug_init()
472 static inline int clk_debug_register(struct clk_core *clk) { return 0; } clk_debug_reparent() argument
473 static inline void clk_debug_reparent(struct clk_core *clk, clk_debug_reparent() argument
477 static inline void clk_debug_unregister(struct clk_core *clk) clk_debug_unregister() argument
483 static void clk_unprepare_unused_subtree(struct clk_core *clk) clk_unprepare_unused_subtree() argument
489 hlist_for_each_entry(child, &clk->children, child_node) clk_unprepare_unused_subtree()
492 if (clk->prepare_count) clk_unprepare_unused_subtree()
495 if (clk->flags & CLK_IGNORE_UNUSED) clk_unprepare_unused_subtree()
498 if (clk_core_is_prepared(clk)) { clk_unprepare_unused_subtree()
499 trace_clk_unprepare(clk); clk_unprepare_unused_subtree()
500 if (clk->ops->unprepare_unused) clk_unprepare_unused_subtree()
501 clk->ops->unprepare_unused(clk->hw); clk_unprepare_unused_subtree()
502 else if (clk->ops->unprepare) clk_unprepare_unused_subtree()
503 clk->ops->unprepare(clk->hw); clk_unprepare_unused_subtree()
504 trace_clk_unprepare_complete(clk); clk_unprepare_unused_subtree()
509 static void clk_disable_unused_subtree(struct clk_core *clk) clk_disable_unused_subtree() argument
516 hlist_for_each_entry(child, &clk->children, child_node) clk_disable_unused_subtree()
521 if (clk->enable_count) clk_disable_unused_subtree()
524 if (clk->flags & CLK_IGNORE_UNUSED) clk_disable_unused_subtree()
532 if (clk_core_is_enabled(clk)) { clk_disable_unused_subtree()
533 trace_clk_disable(clk); clk_disable_unused_subtree()
534 if (clk->ops->disable_unused) clk_disable_unused_subtree()
535 clk->ops->disable_unused(clk->hw); clk_disable_unused_subtree()
536 else if (clk->ops->disable) clk_disable_unused_subtree()
537 clk->ops->disable(clk->hw); clk_disable_unused_subtree()
538 trace_clk_disable_complete(clk); clk_disable_unused_subtree()
555 struct clk_core *clk; clk_disable_unused() local
558 pr_warn("clk: Not disabling unused clocks\n"); clk_disable_unused()
564 hlist_for_each_entry(clk, &clk_root_list, child_node) clk_disable_unused()
565 clk_disable_unused_subtree(clk); clk_disable_unused()
567 hlist_for_each_entry(clk, &clk_orphan_list, child_node) clk_disable_unused()
568 clk_disable_unused_subtree(clk); clk_disable_unused()
570 hlist_for_each_entry(clk, &clk_root_list, child_node) clk_disable_unused()
571 clk_unprepare_unused_subtree(clk); clk_disable_unused()
573 hlist_for_each_entry(clk, &clk_orphan_list, child_node) clk_disable_unused()
574 clk_unprepare_unused_subtree(clk); clk_disable_unused()
584 const char *__clk_get_name(struct clk *clk) __clk_get_name() argument
586 return !clk ? NULL : clk->core->name; __clk_get_name()
590 struct clk_hw *__clk_get_hw(struct clk *clk) __clk_get_hw() argument
592 return !clk ? NULL : clk->core->hw; __clk_get_hw()
596 u8 __clk_get_num_parents(struct clk *clk) __clk_get_num_parents() argument
598 return !clk ? 0 : clk->core->num_parents; __clk_get_num_parents()
602 struct clk *__clk_get_parent(struct clk *clk) __clk_get_parent() argument
604 if (!clk) __clk_get_parent()
607 /* TODO: Create a per-user clk and change callers to call clk_put */ __clk_get_parent()
608 return !clk->core->parent ? NULL : clk->core->parent->hw->clk; __clk_get_parent()
612 static struct clk_core *clk_core_get_parent_by_index(struct clk_core *clk, clk_core_get_parent_by_index() argument
615 if (!clk || index >= clk->num_parents) clk_core_get_parent_by_index()
617 else if (!clk->parents) clk_core_get_parent_by_index()
618 return clk_core_lookup(clk->parent_names[index]); clk_core_get_parent_by_index()
619 else if (!clk->parents[index]) clk_core_get_parent_by_index()
620 return clk->parents[index] = clk_core_get_parent_by_index()
621 clk_core_lookup(clk->parent_names[index]); clk_core_get_parent_by_index()
623 return clk->parents[index]; clk_core_get_parent_by_index()
626 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) clk_get_parent_by_index() argument
630 if (!clk) clk_get_parent_by_index()
633 parent = clk_core_get_parent_by_index(clk->core, index); clk_get_parent_by_index()
635 return !parent ? NULL : parent->hw->clk; clk_get_parent_by_index()
639 unsigned int __clk_get_enable_count(struct clk *clk) __clk_get_enable_count() argument
641 return !clk ? 0 : clk->core->enable_count; __clk_get_enable_count()
644 static unsigned long clk_core_get_rate_nolock(struct clk_core *clk) clk_core_get_rate_nolock() argument
648 if (!clk) { clk_core_get_rate_nolock()
653 ret = clk->rate; clk_core_get_rate_nolock()
655 if (clk->flags & CLK_IS_ROOT) clk_core_get_rate_nolock()
658 if (!clk->parent) clk_core_get_rate_nolock()
665 unsigned long __clk_get_rate(struct clk *clk) __clk_get_rate() argument
667 if (!clk) __clk_get_rate()
670 return clk_core_get_rate_nolock(clk->core); __clk_get_rate()
674 static unsigned long __clk_get_accuracy(struct clk_core *clk) __clk_get_accuracy() argument
676 if (!clk) __clk_get_accuracy()
679 return clk->accuracy; __clk_get_accuracy()
682 unsigned long __clk_get_flags(struct clk *clk) __clk_get_flags() argument
684 return !clk ? 0 : clk->core->flags; __clk_get_flags()
688 static bool clk_core_is_prepared(struct clk_core *clk) clk_core_is_prepared() argument
692 if (!clk) clk_core_is_prepared()
699 if (!clk->ops->is_prepared) { clk_core_is_prepared()
700 ret = clk->prepare_count ? 1 : 0; clk_core_is_prepared()
704 ret = clk->ops->is_prepared(clk->hw); clk_core_is_prepared()
709 bool __clk_is_prepared(struct clk *clk) __clk_is_prepared() argument
711 if (!clk) __clk_is_prepared()
714 return clk_core_is_prepared(clk->core); __clk_is_prepared()
717 static bool clk_core_is_enabled(struct clk_core *clk) clk_core_is_enabled() argument
721 if (!clk) clk_core_is_enabled()
728 if (!clk->ops->is_enabled) { clk_core_is_enabled()
729 ret = clk->enable_count ? 1 : 0; clk_core_is_enabled()
733 ret = clk->ops->is_enabled(clk->hw); clk_core_is_enabled()
738 bool __clk_is_enabled(struct clk *clk) __clk_is_enabled() argument
740 if (!clk) __clk_is_enabled()
743 return clk_core_is_enabled(clk->core); __clk_is_enabled()
748 struct clk_core *clk) __clk_lookup_subtree()
753 if (!strcmp(clk->name, name)) __clk_lookup_subtree()
754 return clk; __clk_lookup_subtree()
756 hlist_for_each_entry(child, &clk->children, child_node) { __clk_lookup_subtree()
773 /* search the 'proper' clk tree first */ clk_core_lookup()
850 struct clk *__clk_lookup(const char *name) __clk_lookup()
854 return !core ? NULL : core->hw->clk; __clk_lookup()
857 static void clk_core_get_boundaries(struct clk_core *clk, clk_core_get_boundaries() argument
861 struct clk *clk_user; clk_core_get_boundaries()
866 hlist_for_each_entry(clk_user, &clk->clks, clks_node) clk_core_get_boundaries()
869 hlist_for_each_entry(clk_user, &clk->clks, clks_node) clk_core_get_boundaries()
903 /*** clk api ***/
905 static void clk_core_unprepare(struct clk_core *clk) clk_core_unprepare() argument
907 if (!clk) clk_core_unprepare()
910 if (WARN_ON(clk->prepare_count == 0)) clk_core_unprepare()
913 if (--clk->prepare_count > 0) clk_core_unprepare()
916 WARN_ON(clk->enable_count > 0); clk_core_unprepare()
918 trace_clk_unprepare(clk); clk_core_unprepare()
920 if (clk->ops->unprepare) clk_core_unprepare()
921 clk->ops->unprepare(clk->hw); clk_core_unprepare()
923 trace_clk_unprepare_complete(clk); clk_core_unprepare()
924 clk_core_unprepare(clk->parent); clk_core_unprepare()
929 * @clk: the clk being unprepared
932 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
933 * if the operation may sleep. One example is a clk which is accessed over
934 * I2c. In the complex case a clk gate operation may require a fast and a slow
938 void clk_unprepare(struct clk *clk) clk_unprepare() argument
940 if (IS_ERR_OR_NULL(clk)) clk_unprepare()
944 clk_core_unprepare(clk->core); clk_unprepare()
949 static int clk_core_prepare(struct clk_core *clk) clk_core_prepare() argument
953 if (!clk) clk_core_prepare()
956 if (clk->prepare_count == 0) { clk_core_prepare()
957 ret = clk_core_prepare(clk->parent); clk_core_prepare()
961 trace_clk_prepare(clk); clk_core_prepare()
963 if (clk->ops->prepare) clk_core_prepare()
964 ret = clk->ops->prepare(clk->hw); clk_core_prepare()
966 trace_clk_prepare_complete(clk); clk_core_prepare()
969 clk_core_unprepare(clk->parent); clk_core_prepare()
974 clk->prepare_count++; clk_core_prepare()
981 * @clk: the clk being prepared
984 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
985 * operation may sleep. One example is a clk which is accessed over I2c. In
986 * the complex case a clk ungate operation may require a fast and a slow part.
991 int clk_prepare(struct clk *clk) clk_prepare() argument
995 if (!clk) clk_prepare()
999 ret = clk_core_prepare(clk->core); clk_prepare()
1006 static void clk_core_disable(struct clk_core *clk) clk_core_disable() argument
1008 if (!clk) clk_core_disable()
1011 if (WARN_ON(clk->enable_count == 0)) clk_core_disable()
1014 if (--clk->enable_count > 0) clk_core_disable()
1017 trace_clk_disable(clk); clk_core_disable()
1019 if (clk->ops->disable) clk_core_disable()
1020 clk->ops->disable(clk->hw); clk_core_disable()
1022 trace_clk_disable_complete(clk); clk_core_disable()
1024 clk_core_disable(clk->parent); clk_core_disable()
1027 static void __clk_disable(struct clk *clk) __clk_disable() argument
1029 if (!clk) __clk_disable()
1032 clk_core_disable(clk->core); __clk_disable()
1037 * @clk: the clk being gated
1041 * clk if the operation is fast and will never sleep. One example is a
1042 * SoC-internal clk which is controlled via simple register writes. In the
1043 * complex case a clk gate operation may require a fast and a slow part. It is
1047 void clk_disable(struct clk *clk) clk_disable() argument
1051 if (IS_ERR_OR_NULL(clk)) clk_disable()
1055 __clk_disable(clk); clk_disable()
1060 static int clk_core_enable(struct clk_core *clk) clk_core_enable() argument
1064 if (!clk) clk_core_enable()
1067 if (WARN_ON(clk->prepare_count == 0)) clk_core_enable()
1070 if (clk->enable_count == 0) { clk_core_enable()
1071 ret = clk_core_enable(clk->parent); clk_core_enable()
1076 trace_clk_enable(clk); clk_core_enable()
1078 if (clk->ops->enable) clk_core_enable()
1079 ret = clk->ops->enable(clk->hw); clk_core_enable()
1081 trace_clk_enable_complete(clk); clk_core_enable()
1084 clk_core_disable(clk->parent); clk_core_enable()
1089 clk->enable_count++; clk_core_enable()
1093 static int __clk_enable(struct clk *clk) __clk_enable() argument
1095 if (!clk) __clk_enable()
1098 return clk_core_enable(clk->core); __clk_enable()
1103 * @clk: the clk being ungated
1106 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
1107 * if the operation will never sleep. One example is a SoC-internal clk which
1108 * is controlled via simple register writes. In the complex case a clk ungate
1114 int clk_enable(struct clk *clk) clk_enable() argument
1120 ret = __clk_enable(clk); clk_enable()
1127 static unsigned long clk_core_round_rate_nolock(struct clk_core *clk, clk_core_round_rate_nolock() argument
1138 if (!clk) clk_core_round_rate_nolock()
1141 parent = clk->parent; clk_core_round_rate_nolock()
1145 if (clk->ops->determine_rate) { clk_core_round_rate_nolock()
1147 return clk->ops->determine_rate(clk->hw, rate, clk_core_round_rate_nolock()
1150 } else if (clk->ops->round_rate) clk_core_round_rate_nolock()
1151 return clk->ops->round_rate(clk->hw, rate, &parent_rate); clk_core_round_rate_nolock()
1152 else if (clk->flags & CLK_SET_RATE_PARENT) clk_core_round_rate_nolock()
1153 return clk_core_round_rate_nolock(clk->parent, rate, min_rate, clk_core_round_rate_nolock()
1156 return clk->rate; clk_core_round_rate_nolock()
1182 * __clk_round_rate - round the given rate for a clk
1183 * @clk: round the rate of this clock
1188 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) __clk_round_rate() argument
1193 if (!clk) __clk_round_rate()
1196 clk_core_get_boundaries(clk->core, &min_rate, &max_rate); __clk_round_rate()
1198 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate); __clk_round_rate()
1203 * clk_round_rate - round the given rate for a clk
1204 * @clk: the clk for which we are rounding a rate
1207 * Takes in a rate as input and rounds it to a rate that the clk can actually
1208 * use which is then returned. If clk doesn't support round_rate operation
1211 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
1215 if (!clk) clk_round_rate()
1219 ret = __clk_round_rate(clk, rate); clk_round_rate()
1227 * __clk_notify - call clk notifier chain
1228 * @clk: struct clk * that is changing rate
1229 * @msg: clk notifier type (see include/linux/clk.h)
1230 * @old_rate: old clk rate
1231 * @new_rate: new clk rate
1233 * Triggers a notifier call chain on the clk rate-change notification
1234 * for 'clk'. Passes a pointer to the struct clk and the previous
1240 static int __clk_notify(struct clk_core *clk, unsigned long msg, __clk_notify() argument
1251 if (cn->clk->core == clk) { __clk_notify()
1252 cnd.clk = cn->clk; __clk_notify()
1263 * @clk: first clk in the subtree
1265 * Walks the subtree of clks starting with clk and recalculates accuracies as
1266 * it goes. Note that if a clk does not implement the .recalc_accuracy
1272 static void __clk_recalc_accuracies(struct clk_core *clk) __clk_recalc_accuracies() argument
1279 if (clk->parent) __clk_recalc_accuracies()
1280 parent_accuracy = clk->parent->accuracy; __clk_recalc_accuracies()
1282 if (clk->ops->recalc_accuracy) __clk_recalc_accuracies()
1283 clk->accuracy = clk->ops->recalc_accuracy(clk->hw, __clk_recalc_accuracies()
1286 clk->accuracy = parent_accuracy; __clk_recalc_accuracies()
1288 hlist_for_each_entry(child, &clk->children, child_node) __clk_recalc_accuracies()
1292 static long clk_core_get_accuracy(struct clk_core *clk) clk_core_get_accuracy() argument
1297 if (clk && (clk->flags & CLK_GET_ACCURACY_NOCACHE)) clk_core_get_accuracy()
1298 __clk_recalc_accuracies(clk); clk_core_get_accuracy()
1300 accuracy = __clk_get_accuracy(clk); clk_core_get_accuracy()
1307 * clk_get_accuracy - return the accuracy of clk
1308 * @clk: the clk whose accuracy is being returned
1310 * Simply returns the cached accuracy of the clk, unless
1313 * If clk is NULL then returns 0.
1315 long clk_get_accuracy(struct clk *clk) clk_get_accuracy() argument
1317 if (!clk) clk_get_accuracy()
1320 return clk_core_get_accuracy(clk->core); clk_get_accuracy()
1324 static unsigned long clk_recalc(struct clk_core *clk, clk_recalc() argument
1327 if (clk->ops->recalc_rate) clk_recalc()
1328 return clk->ops->recalc_rate(clk->hw, parent_rate); clk_recalc()
1334 * @clk: first clk in the subtree
1335 * @msg: notification type (see include/linux/clk.h)
1337 * Walks the subtree of clks starting with clk and recalculates rates as it
1338 * goes. Note that if a clk does not implement the .recalc_rate callback then
1346 static void __clk_recalc_rates(struct clk_core *clk, unsigned long msg) __clk_recalc_rates() argument
1354 old_rate = clk->rate; __clk_recalc_rates()
1356 if (clk->parent) __clk_recalc_rates()
1357 parent_rate = clk->parent->rate; __clk_recalc_rates()
1359 clk->rate = clk_recalc(clk, parent_rate); __clk_recalc_rates()
1365 if (clk->notifier_count && msg) __clk_recalc_rates()
1366 __clk_notify(clk, msg, old_rate, clk->rate); __clk_recalc_rates()
1368 hlist_for_each_entry(child, &clk->children, child_node) __clk_recalc_rates()
1372 static unsigned long clk_core_get_rate(struct clk_core *clk) clk_core_get_rate() argument
1378 if (clk && (clk->flags & CLK_GET_RATE_NOCACHE)) clk_core_get_rate()
1379 __clk_recalc_rates(clk, 0); clk_core_get_rate()
1381 rate = clk_core_get_rate_nolock(clk); clk_core_get_rate()
1388 * clk_get_rate - return the rate of clk
1389 * @clk: the clk whose rate is being returned
1391 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1393 * If clk is NULL then returns 0.
1395 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
1397 if (!clk) clk_get_rate()
1400 return clk_core_get_rate(clk->core); clk_get_rate()
1404 static int clk_fetch_parent_index(struct clk_core *clk, clk_fetch_parent_index() argument
1409 if (!clk->parents) { clk_fetch_parent_index()
1410 clk->parents = kcalloc(clk->num_parents, clk_fetch_parent_index()
1411 sizeof(struct clk *), GFP_KERNEL); clk_fetch_parent_index()
1412 if (!clk->parents) clk_fetch_parent_index()
1421 for (i = 0; i < clk->num_parents; i++) { clk_fetch_parent_index()
1422 if (clk->parents[i] == parent) clk_fetch_parent_index()
1425 if (clk->parents[i]) clk_fetch_parent_index()
1428 if (!strcmp(clk->parent_names[i], parent->name)) { clk_fetch_parent_index()
1429 clk->parents[i] = clk_core_lookup(parent->name); clk_fetch_parent_index()
1437 static void clk_reparent(struct clk_core *clk, struct clk_core *new_parent) clk_reparent() argument
1439 hlist_del(&clk->child_node); clk_reparent()
1443 if (new_parent->new_child == clk) clk_reparent()
1446 hlist_add_head(&clk->child_node, &new_parent->children); clk_reparent()
1448 hlist_add_head(&clk->child_node, &clk_orphan_list); clk_reparent()
1451 clk->parent = new_parent; clk_reparent()
1454 static struct clk_core *__clk_set_parent_before(struct clk_core *clk, __clk_set_parent_before() argument
1458 struct clk_core *old_parent = clk->parent; __clk_set_parent_before()
1477 if (clk->prepare_count) { __clk_set_parent_before()
1481 clk_core_enable(clk); __clk_set_parent_before()
1485 /* update the clk tree topology */ __clk_set_parent_before()
1487 clk_reparent(clk, parent); __clk_set_parent_before()
1512 static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent, __clk_set_parent() argument
1519 old_parent = __clk_set_parent_before(clk, parent); __clk_set_parent()
1521 trace_clk_set_parent(clk, parent); __clk_set_parent()
1524 if (parent && clk->ops->set_parent) __clk_set_parent()
1525 ret = clk->ops->set_parent(clk->hw, p_index); __clk_set_parent()
1527 trace_clk_set_parent_complete(clk, parent); __clk_set_parent()
1531 clk_reparent(clk, old_parent); __clk_set_parent()
1534 if (clk->prepare_count) { __clk_set_parent()
1536 clk_core_disable(clk); __clk_set_parent()
1544 __clk_set_parent_after(clk, parent, old_parent); __clk_set_parent()
1551 * @clk: first clk in the subtree
1552 * @parent_rate: the "future" rate of clk's parent
1554 * Walks the subtree of clks starting with clk, speculating rates as it
1559 * subtree have subscribed to the notifications. Note that if a clk does not
1565 static int __clk_speculate_rates(struct clk_core *clk, __clk_speculate_rates() argument
1574 new_rate = clk_recalc(clk, parent_rate); __clk_speculate_rates()
1577 if (clk->notifier_count) __clk_speculate_rates()
1578 ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate); __clk_speculate_rates()
1581 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n", __clk_speculate_rates()
1582 __func__, clk->name, ret); __clk_speculate_rates()
1586 hlist_for_each_entry(child, &clk->children, child_node) { __clk_speculate_rates()
1596 static void clk_calc_subtree(struct clk_core *clk, unsigned long new_rate, clk_calc_subtree() argument
1601 clk->new_rate = new_rate; clk_calc_subtree()
1602 clk->new_parent = new_parent; clk_calc_subtree()
1603 clk->new_parent_index = p_index; clk_calc_subtree()
1604 /* include clk in new parent's PRE_RATE_CHANGE notifications */ clk_calc_subtree()
1605 clk->new_child = NULL; clk_calc_subtree()
1606 if (new_parent && new_parent != clk->parent) clk_calc_subtree()
1607 new_parent->new_child = clk; clk_calc_subtree()
1609 hlist_for_each_entry(child, &clk->children, child_node) { clk_calc_subtree()
1619 static struct clk_core *clk_calc_new_rates(struct clk_core *clk, clk_calc_new_rates() argument
1622 struct clk_core *top = clk; clk_calc_new_rates()
1633 if (IS_ERR_OR_NULL(clk)) clk_calc_new_rates()
1637 parent = old_parent = clk->parent; clk_calc_new_rates()
1641 clk_core_get_boundaries(clk, &min_rate, &max_rate); clk_calc_new_rates()
1643 /* find the closest rate and parent clk/rate */ clk_calc_new_rates()
1644 if (clk->ops->determine_rate) { clk_calc_new_rates()
1646 ret = clk->ops->determine_rate(clk->hw, rate, clk_calc_new_rates()
1656 } else if (clk->ops->round_rate) { clk_calc_new_rates()
1657 ret = clk->ops->round_rate(clk->hw, rate, clk_calc_new_rates()
1665 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) { clk_calc_new_rates()
1667 clk->new_rate = clk->rate; clk_calc_new_rates()
1678 (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) { clk_calc_new_rates()
1680 __func__, clk->name); clk_calc_new_rates()
1685 if (parent && clk->num_parents > 1) { clk_calc_new_rates()
1686 p_index = clk_fetch_parent_index(clk, parent); clk_calc_new_rates()
1688 pr_debug("%s: clk %s can not be parent of clk %s\n", clk_calc_new_rates()
1689 __func__, parent->name, clk->name); clk_calc_new_rates()
1694 if ((clk->flags & CLK_SET_RATE_PARENT) && parent && clk_calc_new_rates()
1699 clk_calc_subtree(clk, new_rate, parent, p_index); clk_calc_new_rates()
1709 static struct clk_core *clk_propagate_rate_change(struct clk_core *clk, clk_propagate_rate_change() argument
1715 if (clk->rate == clk->new_rate) clk_propagate_rate_change()
1718 if (clk->notifier_count) { clk_propagate_rate_change()
1719 ret = __clk_notify(clk, event, clk->rate, clk->new_rate); clk_propagate_rate_change()
1721 fail_clk = clk; clk_propagate_rate_change()
1724 hlist_for_each_entry(child, &clk->children, child_node) { clk_propagate_rate_change()
1726 if (child->new_parent && child->new_parent != clk) clk_propagate_rate_change()
1733 /* handle the new child who might not be in clk->children yet */ clk_propagate_rate_change()
1734 if (clk->new_child) { clk_propagate_rate_change()
1735 tmp_clk = clk_propagate_rate_change(clk->new_child, event); clk_propagate_rate_change()
1747 static void clk_change_rate(struct clk_core *clk) clk_change_rate() argument
1756 old_rate = clk->rate; clk_change_rate()
1758 if (clk->new_parent) clk_change_rate()
1759 best_parent_rate = clk->new_parent->rate; clk_change_rate()
1760 else if (clk->parent) clk_change_rate()
1761 best_parent_rate = clk->parent->rate; clk_change_rate()
1763 if (clk->new_parent && clk->new_parent != clk->parent) { clk_change_rate()
1764 old_parent = __clk_set_parent_before(clk, clk->new_parent); clk_change_rate()
1765 trace_clk_set_parent(clk, clk->new_parent); clk_change_rate()
1767 if (clk->ops->set_rate_and_parent) { clk_change_rate()
1769 clk->ops->set_rate_and_parent(clk->hw, clk->new_rate, clk_change_rate()
1771 clk->new_parent_index); clk_change_rate()
1772 } else if (clk->ops->set_parent) { clk_change_rate()
1773 clk->ops->set_parent(clk->hw, clk->new_parent_index); clk_change_rate()
1776 trace_clk_set_parent_complete(clk, clk->new_parent); clk_change_rate()
1777 __clk_set_parent_after(clk, clk->new_parent, old_parent); clk_change_rate()
1780 trace_clk_set_rate(clk, clk->new_rate); clk_change_rate()
1782 if (!skip_set_rate && clk->ops->set_rate) clk_change_rate()
1783 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate); clk_change_rate()
1785 trace_clk_set_rate_complete(clk, clk->new_rate); clk_change_rate()
1787 clk->rate = clk_recalc(clk, best_parent_rate); clk_change_rate()
1789 if (clk->notifier_count && old_rate != clk->rate) clk_change_rate()
1790 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); clk_change_rate()
1796 hlist_for_each_entry_safe(child, tmp, &clk->children, child_node) { clk_change_rate()
1798 if (child->new_parent && child->new_parent != clk) clk_change_rate()
1803 /* handle the new child who might not be in clk->children yet */ clk_change_rate()
1804 if (clk->new_child) clk_change_rate()
1805 clk_change_rate(clk->new_child); clk_change_rate()
1808 static int clk_core_set_rate_nolock(struct clk_core *clk, clk_core_set_rate_nolock() argument
1815 if (!clk) clk_core_set_rate_nolock()
1819 if (rate == clk_core_get_rate_nolock(clk)) clk_core_set_rate_nolock()
1822 if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count) clk_core_set_rate_nolock()
1826 top = clk_calc_new_rates(clk, rate); clk_core_set_rate_nolock()
1842 clk->req_rate = req_rate; clk_core_set_rate_nolock()
1848 * clk_set_rate - specify a new rate for clk
1849 * @clk: the clk whose rate is being changed
1850 * @rate: the new rate for clk
1852 * In the simplest case clk_set_rate will only adjust the rate of clk.
1855 * propagate up to clk's parent; whether or not this happens depends on the
1856 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1858 * *parent_rate comes back with a new rate for clk's parent then we propagate
1859 * up to clk's parent and set its rate. Upward propagation will continue
1860 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1861 * .round_rate stops requesting changes to clk's parent_rate.
1868 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
1872 if (!clk) clk_set_rate()
1878 ret = clk_core_set_rate_nolock(clk->core, rate); clk_set_rate()
1888 * @clk: clock source
1894 int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) clk_set_rate_range() argument
1898 if (!clk) clk_set_rate_range()
1902 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n", clk_set_rate_range()
1903 __func__, clk->core->name, clk->dev_id, clk->con_id, clk_set_rate_range()
1910 if (min != clk->min_rate || max != clk->max_rate) { clk_set_rate_range()
1911 clk->min_rate = min; clk_set_rate_range()
1912 clk->max_rate = max; clk_set_rate_range()
1913 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate); clk_set_rate_range()
1924 * @clk: clock source
1929 int clk_set_min_rate(struct clk *clk, unsigned long rate) clk_set_min_rate() argument
1931 if (!clk) clk_set_min_rate()
1934 return clk_set_rate_range(clk, rate, clk->max_rate); clk_set_min_rate()
1940 * @clk: clock source
1945 int clk_set_max_rate(struct clk *clk, unsigned long rate) clk_set_max_rate() argument
1947 if (!clk) clk_set_max_rate()
1950 return clk_set_rate_range(clk, clk->min_rate, rate); clk_set_max_rate()
1955 * clk_get_parent - return the parent of a clk
1956 * @clk: the clk whose parent gets returned
1958 * Simply returns clk->parent. Returns NULL if clk is NULL.
1960 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
1962 struct clk *parent; clk_get_parent()
1965 parent = __clk_get_parent(clk); clk_get_parent()
1981 static struct clk_core *__clk_init_parent(struct clk_core *clk) __clk_init_parent() argument
1988 if (!clk->num_parents) __clk_init_parent()
1991 if (clk->num_parents == 1) { __clk_init_parent()
1992 if (IS_ERR_OR_NULL(clk->parent)) __clk_init_parent()
1993 clk->parent = clk_core_lookup(clk->parent_names[0]); __clk_init_parent()
1994 ret = clk->parent; __clk_init_parent()
1998 if (!clk->ops->get_parent) { __clk_init_parent()
1999 WARN(!clk->ops->get_parent, __clk_init_parent()
2006 * Do our best to cache parent clocks in clk->parents. This prevents __clk_init_parent()
2007 * unnecessary and expensive lookups. We don't set clk->parent here; __clk_init_parent()
2011 index = clk->ops->get_parent(clk->hw); __clk_init_parent()
2013 if (!clk->parents) __clk_init_parent()
2014 clk->parents = __clk_init_parent()
2015 kcalloc(clk->num_parents, sizeof(struct clk *), __clk_init_parent()
2018 ret = clk_core_get_parent_by_index(clk, index); __clk_init_parent()
2024 static void clk_core_reparent(struct clk_core *clk, clk_core_reparent() argument
2027 clk_reparent(clk, new_parent); clk_core_reparent()
2028 __clk_recalc_accuracies(clk); clk_core_reparent()
2029 __clk_recalc_rates(clk, POST_RATE_CHANGE); clk_core_reparent()
2034 * @clk: clock source
2040 * Returns true if @parent is a possible parent for @clk, false otherwise.
2042 bool clk_has_parent(struct clk *clk, struct clk *parent) clk_has_parent() argument
2048 if (!clk || !parent) clk_has_parent()
2051 core = clk->core; clk_has_parent()
2066 static int clk_core_set_parent(struct clk_core *clk, struct clk_core *parent) clk_core_set_parent() argument
2072 if (!clk) clk_core_set_parent()
2078 if (clk->parent == parent) clk_core_set_parent()
2082 if ((clk->num_parents > 1) && (!clk->ops->set_parent)) { clk_core_set_parent()
2088 if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) { clk_core_set_parent()
2095 p_index = clk_fetch_parent_index(clk, parent); clk_core_set_parent()
2098 pr_debug("%s: clk %s can not be parent of clk %s\n", clk_core_set_parent()
2099 __func__, parent->name, clk->name); clk_core_set_parent()
2106 ret = __clk_speculate_rates(clk, p_rate); clk_core_set_parent()
2113 ret = __clk_set_parent(clk, parent, p_index); clk_core_set_parent()
2117 __clk_recalc_rates(clk, ABORT_RATE_CHANGE); clk_core_set_parent()
2119 __clk_recalc_rates(clk, POST_RATE_CHANGE); clk_core_set_parent()
2120 __clk_recalc_accuracies(clk); clk_core_set_parent()
2130 * clk_set_parent - switch the parent of a mux clk
2131 * @clk: the mux clk whose input we are switching
2132 * @parent: the new input to clk
2134 * Re-parent clk to use parent as its new input source. If clk is in
2135 * prepared state, the clk will get enabled for the duration of this call. If
2136 * that's not acceptable for a specific clk (Eg: the consumer can't handle
2138 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
2140 * After successfully changing clk's parent clk_set_parent will update the
2141 * clk topology, sysfs topology and propagate rate recalculation via
2146 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
2148 if (!clk) clk_set_parent()
2151 return clk_core_set_parent(clk->core, parent ? parent->core : NULL); clk_set_parent()
2157 * @clk: clock signal source
2175 int clk_set_phase(struct clk *clk, int degrees) clk_set_phase() argument
2179 if (!clk) clk_set_phase()
2189 trace_clk_set_phase(clk->core, degrees); clk_set_phase()
2191 if (clk->core->ops->set_phase) clk_set_phase()
2192 ret = clk->core->ops->set_phase(clk->core->hw, degrees); clk_set_phase()
2194 trace_clk_set_phase_complete(clk->core, degrees); clk_set_phase()
2197 clk->core->phase = degrees; clk_set_phase()
2205 static int clk_core_get_phase(struct clk_core *clk) clk_core_get_phase() argument
2209 if (!clk) clk_core_get_phase()
2213 ret = clk->phase; clk_core_get_phase()
2223 * @clk: clock signal source
2228 int clk_get_phase(struct clk *clk) clk_get_phase() argument
2230 if (!clk) clk_get_phase()
2233 return clk_core_get_phase(clk->core); clk_get_phase()
2237 * clk_is_match - check if two clk's point to the same hardware clock
2238 * @p: clk compared against q
2239 * @q: clk compared against p
2241 * Returns true if the two struct clk pointers both point to the same hardware
2242 * clock node. Put differently, returns true if struct clk *p and struct clk *q
2247 bool clk_is_match(const struct clk *p, const struct clk *q) clk_is_match()
2249 /* trivial case: identical struct clk's or both NULL */ clk_is_match()
2253 /* true if clk->core pointers match. Avoid derefing garbage */ clk_is_match()
2263 * __clk_init - initialize the data structures in a struct clk
2264 * @dev: device initializing this clk, placeholder for now
2265 * @clk: clk being initialized
2270 static int __clk_init(struct device *dev, struct clk *clk_user) __clk_init()
2275 struct clk_core *clk; __clk_init() local
2281 clk = clk_user->core; __clk_init()
2286 if (clk_core_lookup(clk->name)) { __clk_init()
2287 pr_debug("%s: clk %s already initialized\n", __clk_init()
2288 __func__, clk->name); __clk_init()
2293 /* check that clk_ops are sane. See Documentation/clk.txt */ __clk_init()
2294 if (clk->ops->set_rate && __clk_init()
2295 !((clk->ops->round_rate || clk->ops->determine_rate) && __clk_init()
2296 clk->ops->recalc_rate)) { __clk_init()
2298 __func__, clk->name); __clk_init()
2303 if (clk->ops->set_parent && !clk->ops->get_parent) { __clk_init()
2305 __func__, clk->name); __clk_init()
2310 if (clk->ops->set_rate_and_parent && __clk_init()
2311 !(clk->ops->set_parent && clk->ops->set_rate)) { __clk_init()
2313 __func__, clk->name); __clk_init()
2319 for (i = 0; i < clk->num_parents; i++) __clk_init()
2320 WARN(!clk->parent_names[i], __clk_init()
2322 __func__, clk->name); __clk_init()
2325 * Allocate an array of struct clk *'s to avoid unnecessary string __clk_init()
2326 * look-ups of clk's possible parents. This can fail for clocks passed __clk_init()
2327 * in to clk_init during early boot; thus any access to clk->parents[] __clk_init()
2331 * If clk->parents is not NULL we skip this entire block. This allows __clk_init()
2332 * for clock drivers to statically initialize clk->parents. __clk_init()
2334 if (clk->num_parents > 1 && !clk->parents) { __clk_init()
2335 clk->parents = kcalloc(clk->num_parents, sizeof(struct clk *), __clk_init()
2339 * clk_init'd; thus any access to clk->parents[] must check __clk_init()
2343 if (clk->parents) __clk_init()
2344 for (i = 0; i < clk->num_parents; i++) __clk_init()
2345 clk->parents[i] = __clk_init()
2346 clk_core_lookup(clk->parent_names[i]); __clk_init()
2349 clk->parent = __clk_init_parent(clk); __clk_init()
2352 * Populate clk->parent if parent has already been __clk_init'd. If __clk_init()
2353 * parent has not yet been __clk_init'd then place clk in the orphan __clk_init()
2354 * list. If clk has set the CLK_IS_ROOT flag then place it in the root __clk_init()
2355 * clk list. __clk_init()
2357 * Every time a new clk is clk_init'd then we walk the list of orphan __clk_init()
2361 if (clk->parent) __clk_init()
2362 hlist_add_head(&clk->child_node, __clk_init()
2363 &clk->parent->children); __clk_init()
2364 else if (clk->flags & CLK_IS_ROOT) __clk_init()
2365 hlist_add_head(&clk->child_node, &clk_root_list); __clk_init()
2367 hlist_add_head(&clk->child_node, &clk_orphan_list); __clk_init()
2370 * Set clk's accuracy. The preferred method is to use __clk_init()
2376 if (clk->ops->recalc_accuracy) __clk_init()
2377 clk->accuracy = clk->ops->recalc_accuracy(clk->hw, __clk_init()
2378 __clk_get_accuracy(clk->parent)); __clk_init()
2379 else if (clk->parent) __clk_init()
2380 clk->accuracy = clk->parent->accuracy; __clk_init()
2382 clk->accuracy = 0; __clk_init()
2385 * Set clk's phase. __clk_init()
2389 if (clk->ops->get_phase) __clk_init()
2390 clk->phase = clk->ops->get_phase(clk->hw); __clk_init()
2392 clk->phase = 0; __clk_init()
2395 * Set clk's rate. The preferred method is to use .recalc_rate. For __clk_init()
2400 if (clk->ops->recalc_rate) __clk_init()
2401 rate = clk->ops->recalc_rate(clk->hw, __clk_init()
2402 clk_core_get_rate_nolock(clk->parent)); __clk_init()
2403 else if (clk->parent) __clk_init()
2404 rate = clk->parent->rate; __clk_init()
2407 clk->rate = clk->req_rate = rate; __clk_init()
2416 if (!strcmp(clk->name, orphan->parent_names[i])) __clk_init()
2417 clk_core_reparent(orphan, clk); __clk_init()
2422 if (!strcmp(clk->name, orphan->parent_names[i])) { __clk_init()
2423 clk_core_reparent(orphan, clk); __clk_init()
2436 if (clk->ops->init) __clk_init()
2437 clk->ops->init(clk->hw); __clk_init()
2439 kref_init(&clk->ref); __clk_init()
2444 clk_debug_register(clk); __clk_init()
2449 struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id, __clk_create_clk()
2452 struct clk *clk; __clk_create_clk() local
2456 return (struct clk *) hw; __clk_create_clk()
2458 clk = kzalloc(sizeof(*clk), GFP_KERNEL); __clk_create_clk()
2459 if (!clk) __clk_create_clk()
2462 clk->core = hw->core; __clk_create_clk()
2463 clk->dev_id = dev_id; __clk_create_clk()
2464 clk->con_id = con_id; __clk_create_clk()
2465 clk->max_rate = ULONG_MAX; __clk_create_clk()
2468 hlist_add_head(&clk->clks_node, &hw->core->clks); __clk_create_clk()
2471 return clk; __clk_create_clk()
2474 void __clk_free_clk(struct clk *clk) __clk_free_clk() argument
2477 hlist_del(&clk->clks_node); __clk_free_clk()
2480 kfree(clk); __clk_free_clk()
2489 * clock nodes. It returns a pointer to the newly allocated struct clk which
2494 struct clk *clk_register(struct device *dev, struct clk_hw *hw) clk_register()
2497 struct clk_core *clk; clk_register() local
2499 clk = kzalloc(sizeof(*clk), GFP_KERNEL); clk_register()
2500 if (!clk) { clk_register()
2501 pr_err("%s: could not allocate clk\n", __func__); clk_register()
2506 clk->name = kstrdup_const(hw->init->name, GFP_KERNEL); clk_register()
2507 if (!clk->name) { clk_register()
2508 pr_err("%s: could not allocate clk->name\n", __func__); clk_register()
2512 clk->ops = hw->init->ops; clk_register()
2514 clk->owner = dev->driver->owner; clk_register()
2515 clk->hw = hw; clk_register()
2516 clk->flags = hw->init->flags; clk_register()
2517 clk->num_parents = hw->init->num_parents; clk_register()
2518 hw->core = clk; clk_register()
2521 clk->parent_names = kcalloc(clk->num_parents, sizeof(char *), clk_register()
2524 if (!clk->parent_names) { clk_register()
2525 pr_err("%s: could not allocate clk->parent_names\n", __func__); clk_register()
2532 for (i = 0; i < clk->num_parents; i++) { clk_register()
2533 clk->parent_names[i] = kstrdup_const(hw->init->parent_names[i], clk_register()
2535 if (!clk->parent_names[i]) { clk_register()
2542 INIT_HLIST_HEAD(&clk->clks); clk_register()
2544 hw->clk = __clk_create_clk(hw, NULL, NULL); clk_register()
2545 if (IS_ERR(hw->clk)) { clk_register()
2546 pr_err("%s: could not allocate per-user clk\n", __func__); clk_register()
2547 ret = PTR_ERR(hw->clk); clk_register()
2551 ret = __clk_init(dev, hw->clk); clk_register()
2553 return hw->clk; clk_register()
2555 __clk_free_clk(hw->clk); clk_register()
2556 hw->clk = NULL; clk_register()
2560 kfree_const(clk->parent_names[i]); clk_register()
2561 kfree(clk->parent_names); clk_register()
2563 kfree_const(clk->name); clk_register()
2565 kfree(clk); clk_register()
2577 struct clk_core *clk = container_of(ref, struct clk_core, ref); __clk_release() local
2578 int i = clk->num_parents; __clk_release()
2582 kfree(clk->parents); __clk_release()
2584 kfree_const(clk->parent_names[i]); __clk_release()
2586 kfree(clk->parent_names); __clk_release()
2587 kfree_const(clk->name); __clk_release()
2588 kfree(clk); __clk_release()
2594 * consumer calls clk_put() and the struct clk object is freed.
2628 * @clk: clock to unregister
2630 void clk_unregister(struct clk *clk) clk_unregister() argument
2634 if (!clk || WARN_ON_ONCE(IS_ERR(clk))) clk_unregister()
2637 clk_debug_unregister(clk->core); clk_unregister()
2641 if (clk->core->ops == &clk_nodrv_ops) { clk_unregister()
2643 clk->core->name); clk_unregister()
2651 clk->core->ops = &clk_nodrv_ops; clk_unregister()
2654 if (!hlist_empty(&clk->core->children)) { clk_unregister()
2659 hlist_for_each_entry_safe(child, t, &clk->core->children, clk_unregister()
2664 hlist_del_init(&clk->core->child_node); clk_unregister()
2666 if (clk->core->prepare_count) clk_unregister()
2668 __func__, clk->core->name); clk_unregister()
2669 kref_put(&clk->core->ref, __clk_release); clk_unregister()
2677 clk_unregister(*(struct clk **)res); devm_clk_release()
2689 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw) devm_clk_register()
2691 struct clk *clk; devm_clk_register() local
2692 struct clk **clkp; devm_clk_register()
2698 clk = clk_register(dev, hw); devm_clk_register()
2699 if (!IS_ERR(clk)) { devm_clk_register()
2700 *clkp = clk; devm_clk_register()
2706 return clk; devm_clk_register()
2712 struct clk *c = res; devm_clk_match()
2720 * @clk: clock to unregister
2726 void devm_clk_unregister(struct device *dev, struct clk *clk) devm_clk_unregister() argument
2728 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk)); devm_clk_unregister()
2735 int __clk_get(struct clk *clk) __clk_get() argument
2737 struct clk_core *core = !clk ? NULL : clk->core; __clk_get()
2748 void __clk_put(struct clk *clk) __clk_put() argument
2752 if (!clk || WARN_ON_ONCE(IS_ERR(clk))) __clk_put()
2757 hlist_del(&clk->clks_node); __clk_put()
2758 if (clk->min_rate > clk->core->req_rate || __clk_put()
2759 clk->max_rate < clk->core->req_rate) __clk_put()
2760 clk_core_set_rate_nolock(clk->core, clk->core->req_rate); __clk_put()
2762 owner = clk->core->owner; __clk_put()
2763 kref_put(&clk->core->ref, __clk_release); __clk_put()
2769 kfree(clk); __clk_put()
2772 /*** clk rate change notifiers ***/
2775 * clk_notifier_register - add a clk rate change notifier
2776 * @clk: struct clk * to watch
2779 * Request notification when clk's rate changes. This uses an SRCU
2782 * re-enter into the clk framework by calling any top-level clk APIs;
2795 int clk_notifier_register(struct clk *clk, struct notifier_block *nb) clk_notifier_register() argument
2800 if (!clk || !nb) clk_notifier_register()
2805 /* search the list of notifiers for this clk */ clk_notifier_register()
2807 if (cn->clk == clk) clk_notifier_register()
2810 /* if clk wasn't in the notifier list, allocate new clk_notifier */ clk_notifier_register()
2811 if (cn->clk != clk) { clk_notifier_register()
2816 cn->clk = clk; clk_notifier_register()
2824 clk->core->notifier_count++; clk_notifier_register()
2834 * clk_notifier_unregister - remove a clk rate change notifier
2835 * @clk: struct clk *
2838 * Request no further notification for changes to 'clk' and frees memory
2844 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb) clk_notifier_unregister() argument
2849 if (!clk || !nb) clk_notifier_unregister()
2855 if (cn->clk == clk) clk_notifier_unregister()
2858 if (cn->clk == clk) { clk_notifier_unregister()
2861 clk->core->notifier_count--; clk_notifier_unregister()
2885 * @get: Get clock callback. Returns NULL or a struct clk for the
2893 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2903 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, of_clk_src_simple_get()
2910 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data) of_clk_src_onecell_get()
2931 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec, of_clk_add_provider()
2980 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec, __of_clk_get_from_provider()
2984 struct clk *clk = ERR_PTR(-EPROBE_DEFER); __of_clk_get_from_provider() local
2993 clk = provider->get(clkspec, provider->data); __of_clk_get_from_provider()
2994 if (!IS_ERR(clk)) { __of_clk_get_from_provider()
2995 clk = __clk_create_clk(__clk_get_hw(clk), dev_id, __of_clk_get_from_provider()
2998 if (!IS_ERR(clk) && !__clk_get(clk)) { __of_clk_get_from_provider()
2999 __clk_free_clk(clk); __of_clk_get_from_provider()
3000 clk = ERR_PTR(-ENOENT); __of_clk_get_from_provider()
3008 return clk; __of_clk_get_from_provider()
3015 * This function looks up a struct clk from the registered list of clock
3019 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) of_clk_get_from_provider()
3090 struct clk *clk = of_clk_get(np, i); parent_ready() local
3093 if (!IS_ERR(clk)) { parent_ready()
3094 clk_put(clk); parent_ready()
3100 if (PTR_ERR(clk) == -EPROBE_DEFER) parent_ready()
747 __clk_lookup_subtree(const char *name, struct clk_core *clk) __clk_lookup_subtree() argument
|
| H A D | clk-ls1x.c | 11 #include <linux/clk-provider.h>
51 static struct clk *__init clk_register_pll(struct device *dev, clk_register_pll()
57 struct clk *clk; clk_register_pll() local
75 clk = clk_register(dev, hw); clk_register_pll()
77 if (IS_ERR(clk)) clk_register_pll()
80 return clk; clk_register_pll()
89 struct clk *clk; ls1x_clk_init() local
91 clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT, ls1x_clk_init()
93 clk_register_clkdev(clk, "osc_33m_clk", NULL); ls1x_clk_init()
95 /* clock derived from 33 MHz OSC clk */ ls1x_clk_init()
96 clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0); ls1x_clk_init()
97 clk_register_clkdev(clk, "pll_clk", NULL); ls1x_clk_init()
99 /* clock derived from PLL clk */ ls1x_clk_init()
106 clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk", ls1x_clk_init()
111 clk_register_clkdev(clk, "cpu_clk_div", NULL); ls1x_clk_init()
112 clk = clk_register_mux(NULL, "cpu_clk", cpu_parents, ls1x_clk_init()
116 clk_register_clkdev(clk, "cpu_clk", NULL); ls1x_clk_init()
124 clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk", ls1x_clk_init()
127 clk_register_clkdev(clk, "dc_clk_div", NULL); ls1x_clk_init()
128 clk = clk_register_mux(NULL, "dc_clk", dc_parents, ls1x_clk_init()
132 clk_register_clkdev(clk, "dc_clk", NULL); ls1x_clk_init()
140 clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk", ls1x_clk_init()
144 clk_register_clkdev(clk, "ahb_clk_div", NULL); ls1x_clk_init()
145 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, ls1x_clk_init()
149 clk_register_clkdev(clk, "ahb_clk", NULL); ls1x_clk_init()
150 clk_register_clkdev(clk, "stmmaceth", NULL); ls1x_clk_init()
152 /* clock derived from AHB clk */ ls1x_clk_init()
153 /* APB clk is always half of the AHB clk */ ls1x_clk_init()
154 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, ls1x_clk_init()
156 clk_register_clkdev(clk, "apb_clk", NULL); ls1x_clk_init()
157 clk_register_clkdev(clk, "ls1x_i2c", NULL); ls1x_clk_init()
158 clk_register_clkdev(clk, "ls1x_pwmtimer", NULL); ls1x_clk_init()
159 clk_register_clkdev(clk, "ls1x_spi", NULL); ls1x_clk_init()
160 clk_register_clkdev(clk, "ls1x_wdt", NULL); ls1x_clk_init()
161 clk_register_clkdev(clk, "serial8250", NULL); ls1x_clk_init()
|
| H A D | clk-efm32gg.c | 9 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
19 static struct clk *clk[37]; variable in typeref:struct:clk
21 .clks = clk,
22 .clk_num = ARRAY_SIZE(clk),
30 for (i = 0; i < ARRAY_SIZE(clk); ++i) efm32gg_cmu_init()
31 clk[i] = ERR_PTR(-ENOENT); efm32gg_cmu_init()
39 clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL, efm32gg_cmu_init()
42 clk[clk_HFPERCLKUSART0] = clk_register_gate(NULL, "HFPERCLK.USART0", efm32gg_cmu_init()
44 clk[clk_HFPERCLKUSART1] = clk_register_gate(NULL, "HFPERCLK.USART1", efm32gg_cmu_init()
46 clk[clk_HFPERCLKUSART2] = clk_register_gate(NULL, "HFPERCLK.USART2", efm32gg_cmu_init()
48 clk[clk_HFPERCLKUART0] = clk_register_gate(NULL, "HFPERCLK.UART0", efm32gg_cmu_init()
50 clk[clk_HFPERCLKUART1] = clk_register_gate(NULL, "HFPERCLK.UART1", efm32gg_cmu_init()
52 clk[clk_HFPERCLKTIMER0] = clk_register_gate(NULL, "HFPERCLK.TIMER0", efm32gg_cmu_init()
54 clk[clk_HFPERCLKTIMER1] = clk_register_gate(NULL, "HFPERCLK.TIMER1", efm32gg_cmu_init()
56 clk[clk_HFPERCLKTIMER2] = clk_register_gate(NULL, "HFPERCLK.TIMER2", efm32gg_cmu_init()
58 clk[clk_HFPERCLKTIMER3] = clk_register_gate(NULL, "HFPERCLK.TIMER3", efm32gg_cmu_init()
60 clk[clk_HFPERCLKACMP0] = clk_register_gate(NULL, "HFPERCLK.ACMP0", efm32gg_cmu_init()
62 clk[clk_HFPERCLKACMP1] = clk_register_gate(NULL, "HFPERCLK.ACMP1", efm32gg_cmu_init()
64 clk[clk_HFPERCLKI2C0] = clk_register_gate(NULL, "HFPERCLK.I2C0", efm32gg_cmu_init()
66 clk[clk_HFPERCLKI2C1] = clk_register_gate(NULL, "HFPERCLK.I2C1", efm32gg_cmu_init()
68 clk[clk_HFPERCLKGPIO] = clk_register_gate(NULL, "HFPERCLK.GPIO", efm32gg_cmu_init()
70 clk[clk_HFPERCLKVCMP] = clk_register_gate(NULL, "HFPERCLK.VCMP", efm32gg_cmu_init()
72 clk[clk_HFPERCLKPRS] = clk_register_gate(NULL, "HFPERCLK.PRS", efm32gg_cmu_init()
74 clk[clk_HFPERCLKADC0] = clk_register_gate(NULL, "HFPERCLK.ADC0", efm32gg_cmu_init()
76 clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0", efm32gg_cmu_init()
|
| H A D | clk-devres.c | 7 #include <linux/clk.h>
14 clk_put(*(struct clk **)res); devm_clk_release()
17 struct clk *devm_clk_get(struct device *dev, const char *id) devm_clk_get()
19 struct clk **ptr, *clk; devm_clk_get() local
25 clk = clk_get(dev, id); devm_clk_get()
26 if (!IS_ERR(clk)) { devm_clk_get()
27 *ptr = clk; devm_clk_get()
33 return clk; devm_clk_get()
39 struct clk **c = res; devm_clk_match()
47 void devm_clk_put(struct device *dev, struct clk *clk) devm_clk_put() argument
51 ret = devres_release(dev, devm_clk_release, devm_clk_match, clk); devm_clk_put()
|
| H A D | clk.h | 2 * linux/drivers/clk/clk.h
15 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
20 struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
22 void __clk_free_clk(struct clk *clk);
25 static inline struct clk * __clk_create_clk()
28 return (struct clk *)hw; __clk_create_clk()
30 static inline void __clk_free_clk(struct clk *clk) { } __clk_get_hw() argument
31 static struct clk_hw *__clk_get_hw(struct clk *clk) __clk_get_hw() argument
33 return (struct clk_hw *)clk; __clk_get_hw()
|
| H A D | clk-conf.c | 10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clk/clk-conf.h>
21 struct clk *clk, *pclk; __set_clk_parents() local
26 pr_err("clk: invalid value of clock-parents property at %s\n", __set_clk_parents()
43 pr_warn("clk: couldn't get parent clock %d for %s\n", __set_clk_parents()
56 clk = of_clk_get_from_provider(&clkspec); __set_clk_parents()
57 if (IS_ERR(clk)) { __set_clk_parents()
58 pr_warn("clk: couldn't get parent clock %d for %s\n", __set_clk_parents()
60 rc = PTR_ERR(clk); __set_clk_parents()
64 rc = clk_set_parent(clk, pclk); __set_clk_parents()
66 pr_err("clk: failed to reparent %s to %s: %d\n", __set_clk_parents()
67 __clk_get_name(clk), __clk_get_name(pclk), rc); __set_clk_parents()
68 clk_put(clk); __set_clk_parents()
83 struct clk *clk; __set_clk_rates() local
100 clk = of_clk_get_from_provider(&clkspec); __set_clk_rates()
101 if (IS_ERR(clk)) { __set_clk_rates()
102 pr_warn("clk: couldn't get clock %d for %s\n", __set_clk_rates()
104 return PTR_ERR(clk); __set_clk_rates()
107 rc = clk_set_rate(clk, rate); __set_clk_rates()
109 pr_err("clk: couldn't set %s clock rate: %d\n", __set_clk_rates()
110 __clk_get_name(clk), rc); __set_clk_rates()
111 clk_put(clk); __set_clk_rates()
|
| H A D | clk-bcm2835.c | 20 #include <linux/clk-provider.h>
22 #include <linux/clk/bcm2835.h>
32 struct clk *clk; bcm2835_init_clocks() local
35 clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, bcm2835_init_clocks()
37 if (IS_ERR(clk)) bcm2835_init_clocks()
40 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, bcm2835_init_clocks()
42 if (IS_ERR(clk)) bcm2835_init_clocks()
45 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT, bcm2835_init_clocks()
47 if (IS_ERR(clk)) bcm2835_init_clocks()
49 ret = clk_register_clkdev(clk, NULL, "20201000.uart"); bcm2835_init_clocks()
53 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT, bcm2835_init_clocks()
55 if (IS_ERR(clk)) bcm2835_init_clocks()
57 ret = clk_register_clkdev(clk, NULL, "20215000.uart"); bcm2835_init_clocks()
|
| H A D | clkdev.c | 2 * drivers/clk/clkdev.c
10 * Helper for the clk API to assist looking up a struct clk.
20 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
25 #include "clk.h"
31 static struct clk *__of_clk_get(struct device_node *np, int index, __of_clk_get()
35 struct clk *clk; __of_clk_get() local
46 clk = __of_clk_get_from_provider(&clkspec, dev_id, con_id); __of_clk_get()
49 return clk; __of_clk_get()
52 struct clk *of_clk_get(struct device_node *np, int index) of_clk_get()
58 static struct clk *__of_clk_get_by_name(struct device_node *np, __of_clk_get_by_name()
62 struct clk *clk = ERR_PTR(-ENOENT); __of_clk_get_by_name() local
75 clk = __of_clk_get(np, index, dev_id, name); __of_clk_get_by_name()
76 if (!IS_ERR(clk)) { __of_clk_get_by_name()
79 if (PTR_ERR(clk) != -EPROBE_DEFER) __of_clk_get_by_name()
82 return clk; __of_clk_get_by_name()
95 return clk; __of_clk_get_by_name()
104 * and uses them to look up the struct clk from the registered list of clock
107 struct clk *of_clk_get_by_name(struct device_node *np, const char *name) of_clk_get_by_name()
118 static struct clk *__of_clk_get_by_name(struct device_node *np, __of_clk_get_by_name()
127 * Find the correct struct clk for the device and connection ID.
169 struct clk *clk_get_sys(const char *dev_id, const char *con_id) clk_get_sys()
172 struct clk *clk = NULL; clk_get_sys() local
180 clk = __clk_create_clk(__clk_get_hw(cl->clk), dev_id, con_id); clk_get_sys()
181 if (IS_ERR(clk)) clk_get_sys()
184 if (!__clk_get(clk)) { clk_get_sys()
185 __clk_free_clk(clk); clk_get_sys()
193 return cl ? clk : ERR_PTR(-ENOENT); clk_get_sys()
197 struct clk *clk_get(struct device *dev, const char *con_id) clk_get()
200 struct clk *clk; clk_get() local
203 clk = __of_clk_get_by_name(dev->of_node, dev_id, con_id); clk_get()
204 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) clk_get()
205 return clk; clk_get()
212 void clk_put(struct clk *clk) clk_put() argument
214 __clk_put(clk); clk_put()
246 vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, vclkdev_alloc() argument
255 cla->cl.clk = clk; vclkdev_alloc()
270 clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) clkdev_alloc() argument
276 cl = vclkdev_alloc(clk, con_id, dev_fmt, ap); clkdev_alloc()
286 struct clk *r = clk_get(dev, id); clk_add_alias()
314 * clk_register_clkdev - register one clock lookup for a struct clk
315 * @clk: struct clk to associate with all clk_lookups
327 int clk_register_clkdev(struct clk *clk, const char *con_id, clk_register_clkdev() argument
333 if (IS_ERR(clk)) clk_register_clkdev()
334 return PTR_ERR(clk); clk_register_clkdev()
337 cl = vclkdev_alloc(clk, con_id, dev_fmt, ap); clk_register_clkdev()
350 * clk_register_clkdevs - register a set of clk_lookup for a struct clk
351 * @clk: struct clk to associate with all clk_lookups
360 int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num) clk_register_clkdevs() argument
364 if (IS_ERR(clk)) clk_register_clkdevs()
365 return PTR_ERR(clk); clk_register_clkdevs()
368 cl->clk = clk; clk_register_clkdevs()
|
| H A D | clk-nspire.c | 11 #include <linux/clk-provider.h>
45 static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) nspire_clkinfo_cx() argument
48 clk->base_clock = 48 * MHZ; nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; nspire_clkinfo_cx()
52 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN); nspire_clkinfo_cx()
53 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); nspire_clkinfo_cx()
56 static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) nspire_clkinfo_classic() argument
59 clk->base_clock = 27 * MHZ; nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; nspire_clkinfo_classic()
63 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2; nspire_clkinfo_classic()
64 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); nspire_clkinfo_classic()
72 struct clk *clk; nspire_ahbdiv_setup() local
88 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, nspire_ahbdiv_setup()
90 if (!IS_ERR(clk)) nspire_ahbdiv_setup()
91 of_clk_add_provider(node, of_clk_src_simple_get, clk); nspire_ahbdiv_setup()
114 struct clk *clk; nspire_clk_setup() local
128 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, nspire_clk_setup()
130 if (!IS_ERR(clk)) nspire_clk_setup()
131 of_clk_add_provider(node, of_clk_src_simple_get, clk); nspire_clk_setup()
|
| H A D | clk-gpio-gate.c | 12 #include <linux/clk-provider.h>
35 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_gate_enable() local
37 gpiod_set_value(clk->gpiod, 1); clk_gpio_gate_enable()
44 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_gate_disable() local
46 gpiod_set_value(clk->gpiod, 0); clk_gpio_gate_disable()
51 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_gate_is_enabled() local
53 return gpiod_get_value(clk->gpiod); clk_gpio_gate_is_enabled()
72 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, clk_register_gpio_gate()
77 struct clk *clk = ERR_PTR(-EINVAL); clk_register_gpio_gate() local
105 clk = ERR_PTR(-ENOMEM); clk_register_gpio_gate()
118 clk = clk_register(dev, &clk_gpio->hw); clk_register_gpio_gate()
120 if (!IS_ERR(clk)) clk_register_gpio_gate()
121 return clk; clk_register_gpio_gate()
130 return clk; clk_register_gpio_gate()
143 struct clk *clk; member in struct:clk_gpio_gate_delayed_register_data
146 static struct clk *of_clk_gpio_gate_delayed_register_get( of_clk_gpio_gate_delayed_register_get()
151 struct clk *clk; of_clk_gpio_gate_delayed_register_get() local
159 if (data->clk) { of_clk_gpio_gate_delayed_register_get()
161 return data->clk; of_clk_gpio_gate_delayed_register_get()
176 clk = clk_register_gpio_gate(NULL, clk_name, parent_name, gpio, of_clk_gpio_gate_delayed_register_get()
178 if (IS_ERR(clk)) { of_clk_gpio_gate_delayed_register_get()
180 return clk; of_clk_gpio_gate_delayed_register_get()
183 data->clk = clk; of_clk_gpio_gate_delayed_register_get()
186 return clk; of_clk_gpio_gate_delayed_register_get()
|
| H A D | clk-moxart.c | 13 #include <linux/clk-provider.h>
21 struct clk *clk, *ref_clk; moxart_of_pll_clk_init() local
44 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); moxart_of_pll_clk_init()
45 if (IS_ERR(clk)) { moxart_of_pll_clk_init()
50 clk_register_clkdev(clk, NULL, name); moxart_of_pll_clk_init()
51 of_clk_add_provider(node, of_clk_src_simple_get, clk); moxart_of_pll_clk_init()
59 struct clk *clk, *pll_clk; moxart_of_apb_clk_init() local
87 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div); moxart_of_apb_clk_init()
88 if (IS_ERR(clk)) { moxart_of_apb_clk_init()
93 clk_register_clkdev(clk, NULL, name); moxart_of_apb_clk_init()
94 of_clk_add_provider(node, of_clk_src_simple_get, clk); moxart_of_apb_clk_init()
|
| H A D | clk-fixed-factor.c | 11 #include <linux/clk-provider.h>
22 * rate - rate is fixed. clk->rate = parent->rate / div * mult
44 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { clk_factor_round_rate()
48 *prate = __clk_round_rate(__clk_get_parent(hw->clk), clk_factor_round_rate()
68 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, clk_register_fixed_factor()
74 struct clk *clk; clk_register_fixed_factor() local
78 pr_err("%s: could not allocate fixed factor clk\n", __func__); clk_register_fixed_factor()
93 clk = clk_register(dev, &fix->hw); clk_register_fixed_factor()
95 if (IS_ERR(clk)) clk_register_fixed_factor()
98 return clk; clk_register_fixed_factor()
108 struct clk *clk; of_fixed_factor_clk_setup() local
128 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, of_fixed_factor_clk_setup()
130 if (!IS_ERR(clk)) of_fixed_factor_clk_setup()
131 of_clk_add_provider(node, of_clk_src_simple_get, clk); of_fixed_factor_clk_setup()
|
| H A D | clk-fixed-rate.c | 12 #include <linux/clk-provider.h>
59 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, clk_register_fixed_rate_with_accuracy()
64 struct clk *clk; clk_register_fixed_rate_with_accuracy() local
70 pr_err("%s: could not allocate fixed clk\n", __func__); clk_register_fixed_rate_with_accuracy()
86 clk = clk_register(dev, &fixed->hw); clk_register_fixed_rate_with_accuracy()
87 if (IS_ERR(clk)) clk_register_fixed_rate_with_accuracy()
90 return clk; clk_register_fixed_rate_with_accuracy()
102 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, clk_register_fixed_rate()
117 struct clk *clk; of_fixed_clk_setup() local
129 clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL, of_fixed_clk_setup()
132 if (!IS_ERR(clk)) of_fixed_clk_setup()
133 of_clk_add_provider(node, of_clk_src_simple_get, clk); of_fixed_clk_setup()
|
| /linux-4.1.27/include/linux/ |
| H A D | clkdev.h | 10 * Helper for the clk API to assist looking up a struct clk.
17 struct clk;
24 struct clk *clk; member in struct:clk_lookup
31 .clk = c, \
34 struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
43 int clk_register_clkdev(struct clk *, const char *, const char *, ...);
44 int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
47 int __clk_get(struct clk *clk);
48 void __clk_put(struct clk *clk);
|
| H A D | sh_clk.h | 9 #include <linux/clk.h>
12 struct clk;
23 void (*init)(struct clk *clk);
25 int (*enable)(struct clk *clk);
26 void (*disable)(struct clk *clk);
27 unsigned long (*recalc)(struct clk *clk);
28 int (*set_rate)(struct clk *clk, unsigned long rate);
29 int (*set_parent)(struct clk *clk, struct clk *parent);
30 long (*round_rate)(struct clk *clk, unsigned long rate);
37 struct clk { struct
39 struct clk *parent;
40 struct clk **parent_table; /* list of parents to */
79 /* drivers/sh/clk.c */
80 unsigned long followparent_recalc(struct clk *);
82 void propagate_rate(struct clk *);
83 int clk_reparent(struct clk *child, struct clk *parent);
84 int clk_register(struct clk *);
85 void clk_unregister(struct clk *);
96 void clk_rate_table_build(struct clk *clk,
102 long clk_rate_table_round(struct clk *clk,
106 int clk_rate_table_find(struct clk *clk,
110 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
113 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
116 long clk_round_parent(struct clk *clk, unsigned long target,
141 int sh_clk_mstp_register(struct clk *clks, int nr);
149 static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) sh_clk_mstp32_register()
166 void (*kick)(struct clk *clk);
171 int sh_clk_div4_register(struct clk *clks, int nr,
173 int sh_clk_div4_enable_register(struct clk *clks, int nr,
175 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
200 int sh_clk_div6_register(struct clk *clks, int nr);
201 int sh_clk_div6_reparent_register(struct clk *clks, int nr);
203 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
205 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
214 int sh_clk_fsidiv_register(struct clk *clks, int nr);
|
| H A D | clk.h | 2 * linux/include/linux/clk.h
21 struct clk;
26 * DOC: clk notifier callback types
28 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
36 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
39 * POST_RATE_CHANGE - called after the clk rate change has successfully
48 * struct clk_notifier - associate a clk with a notifier
49 * @clk: struct clk * to associate the notifier with
50 * @notifier_head: a blocking_notifier_head for this clk
55 * particular @clk. Future notifiers on that @clk are added to the
59 struct clk *clk; member in struct:clk_notifier
66 * @clk: struct clk * being changed
67 * @old_rate: previous rate of this clk
68 * @new_rate: new rate of this clk
70 * For a pre-notifier, old_rate is the clk's rate before this rate
72 * post-notifier, old_rate and new_rate are both set to the clk's
76 struct clk *clk; member in struct:clk_notifier_data
83 * @clk: clock whose rate we are interested in
90 int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
94 * @clk: clock whose rate we are no longer interested in
97 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
102 * @clk: clock source
107 long clk_get_accuracy(struct clk *clk);
111 * @clk: clock signal source
117 int clk_set_phase(struct clk *clk, int degrees);
121 * @clk: clock signal source
126 int clk_get_phase(struct clk *clk);
129 * clk_is_match - check if two clk's point to the same hardware clock
130 * @p: clk compared against q
131 * @q: clk compared against p
133 * Returns true if the two struct clk pointers both point to the same hardware
134 * clock node. Put differently, returns true if struct clk *p and struct clk *q
139 bool clk_is_match(const struct clk *p, const struct clk *q);
143 static inline long clk_get_accuracy(struct clk *clk) clk_get_accuracy() argument
148 static inline long clk_set_phase(struct clk *clk, int phase) clk_set_phase() argument
153 static inline long clk_get_phase(struct clk *clk) clk_get_phase() argument
158 static inline bool clk_is_match(const struct clk *p, const struct clk *q) clk_is_match()
167 * @clk: clock source
174 int clk_prepare(struct clk *clk);
176 static inline int clk_prepare(struct clk *clk) clk_prepare() argument
185 * @clk: clock source
193 void clk_unprepare(struct clk *clk);
195 static inline void clk_unprepare(struct clk *clk) clk_unprepare() argument
207 * Returns a struct clk corresponding to the clock producer, or
217 struct clk *clk_get(struct device *dev, const char *id);
224 * Returns a struct clk corresponding to the clock producer, or
237 struct clk *devm_clk_get(struct device *dev, const char *id);
241 * @clk: clock source
249 int clk_enable(struct clk *clk);
253 * @clk: clock source
265 void clk_disable(struct clk *clk);
270 * @clk: clock source
272 unsigned long clk_get_rate(struct clk *clk);
276 * @clk: clock source
284 void clk_put(struct clk *clk);
289 * @clk: clock source acquired with devm_clk_get()
297 void devm_clk_put(struct device *dev, struct clk *clk);
306 * @clk: clock source
311 long clk_round_rate(struct clk *clk, unsigned long rate);
315 * @clk: clock source
320 int clk_set_rate(struct clk *clk, unsigned long rate);
324 * @clk: clock source
330 * Returns true if @parent is a possible parent for @clk, false otherwise.
332 bool clk_has_parent(struct clk *clk, struct clk *parent);
336 * @clk: clock source
342 int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
346 * @clk: clock source
351 int clk_set_min_rate(struct clk *clk, unsigned long rate);
355 * @clk: clock source
360 int clk_set_max_rate(struct clk *clk, unsigned long rate);
364 * @clk: clock source
369 int clk_set_parent(struct clk *clk, struct clk *parent);
373 * @clk: clock source
375 * Returns struct clk corresponding to parent clock source, or
378 struct clk *clk_get_parent(struct clk *clk);
385 * Returns a struct clk corresponding to the clock producer, or
395 struct clk *clk_get_sys(const char *dev_id, const char *con_id);
399 static inline struct clk *clk_get(struct device *dev, const char *id) clk_get()
404 static inline struct clk *devm_clk_get(struct device *dev, const char *id) devm_clk_get()
409 static inline void clk_put(struct clk *clk) {} clk_put() argument
411 static inline void devm_clk_put(struct device *dev, struct clk *clk) {} devm_clk_put() argument
413 static inline int clk_enable(struct clk *clk) clk_enable() argument
418 static inline void clk_disable(struct clk *clk) {} clk_disable() argument
420 static inline unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
425 static inline int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
430 static inline long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
435 static inline bool clk_has_parent(struct clk *clk, struct clk *parent) clk_has_parent() argument
440 static inline int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
445 static inline struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
453 static inline int clk_prepare_enable(struct clk *clk) clk_prepare_enable() argument
457 ret = clk_prepare(clk); clk_prepare_enable()
460 ret = clk_enable(clk); clk_prepare_enable()
462 clk_unprepare(clk); clk_prepare_enable()
468 static inline void clk_disable_unprepare(struct clk *clk) clk_disable_unprepare() argument
470 clk_disable(clk); clk_disable_unprepare()
471 clk_unprepare(clk); clk_disable_unprepare()
491 struct clk *of_clk_get(struct device_node *np, int index);
492 struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
493 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);
495 static inline struct clk *of_clk_get(struct device_node *np, int index) of_clk_get()
499 static inline struct clk *of_clk_get_by_name(struct device_node *np, of_clk_get_by_name()
|
| /linux-4.1.27/arch/arm/mach-davinci/include/mach/ |
| H A D | clock.h | 16 struct clk;
18 extern int clk_register(struct clk *clk);
19 extern void clk_unregister(struct clk *clk);
21 int davinci_clk_reset_assert(struct clk *c);
22 int davinci_clk_reset_deassert(struct clk *c);
|
| /linux-4.1.27/drivers/clk/spear/ |
| H A D | spear6xx_clock.c | 12 #include <linux/clk.h>
16 #include "clk.h"
119 struct clk *clk, *clk1; spear6xx_clk_init() local
121 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear6xx_clk_init()
123 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear6xx_clk_init()
125 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, spear6xx_clk_init()
127 clk_register_clkdev(clk, "osc_30m_clk", NULL); spear6xx_clk_init()
129 /* clock derived from 32 KHz osc clk */ spear6xx_clk_init()
130 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, spear6xx_clk_init()
132 clk_register_clkdev(clk, NULL, "rtc-spear"); spear6xx_clk_init()
134 /* clock derived from 30 MHz osc clk */ spear6xx_clk_init()
135 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, spear6xx_clk_init()
137 clk_register_clkdev(clk, "pll3_clk", NULL); spear6xx_clk_init()
139 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", spear6xx_clk_init()
142 clk_register_clkdev(clk, "vco1_clk", NULL); spear6xx_clk_init()
145 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", spear6xx_clk_init()
148 clk_register_clkdev(clk, "vco2_clk", NULL); spear6xx_clk_init()
151 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, spear6xx_clk_init()
153 clk_register_clkdev(clk, NULL, "wdt"); spear6xx_clk_init()
155 /* clock derived from pll1 clk */ spear6xx_clk_init()
156 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", spear6xx_clk_init()
158 clk_register_clkdev(clk, "cpu_clk", NULL); spear6xx_clk_init()
160 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", spear6xx_clk_init()
163 clk_register_clkdev(clk, "ahb_clk", NULL); spear6xx_clk_init()
165 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, spear6xx_clk_init()
168 clk_register_clkdev(clk, "uart_syn_clk", NULL); spear6xx_clk_init()
171 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, spear6xx_clk_init()
175 clk_register_clkdev(clk, "uart_mclk", NULL); spear6xx_clk_init()
177 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
179 clk_register_clkdev(clk, NULL, "d0000000.serial"); spear6xx_clk_init()
181 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
183 clk_register_clkdev(clk, NULL, "d0080000.serial"); spear6xx_clk_init()
185 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", spear6xx_clk_init()
188 clk_register_clkdev(clk, "firda_syn_clk", NULL); spear6xx_clk_init()
191 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, spear6xx_clk_init()
195 clk_register_clkdev(clk, "firda_mclk", NULL); spear6xx_clk_init()
197 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, spear6xx_clk_init()
199 clk_register_clkdev(clk, NULL, "firda"); spear6xx_clk_init()
201 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", spear6xx_clk_init()
204 clk_register_clkdev(clk, "clcd_syn_clk", NULL); spear6xx_clk_init()
207 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, spear6xx_clk_init()
211 clk_register_clkdev(clk, "clcd_mclk", NULL); spear6xx_clk_init()
213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, spear6xx_clk_init()
215 clk_register_clkdev(clk, NULL, "clcd"); spear6xx_clk_init()
218 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, spear6xx_clk_init()
220 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); spear6xx_clk_init()
222 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, spear6xx_clk_init()
225 clk_register_clkdev(clk, NULL, "gpt0"); spear6xx_clk_init()
227 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, spear6xx_clk_init()
230 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear6xx_clk_init()
232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, spear6xx_clk_init()
234 clk_register_clkdev(clk, NULL, "gpt1"); spear6xx_clk_init()
236 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, spear6xx_clk_init()
238 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); spear6xx_clk_init()
240 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, spear6xx_clk_init()
243 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear6xx_clk_init()
245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, spear6xx_clk_init()
247 clk_register_clkdev(clk, NULL, "gpt2"); spear6xx_clk_init()
249 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, spear6xx_clk_init()
251 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); spear6xx_clk_init()
253 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, spear6xx_clk_init()
256 clk_register_clkdev(clk, "gpt3_mclk", NULL); spear6xx_clk_init()
258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, spear6xx_clk_init()
260 clk_register_clkdev(clk, NULL, "gpt3"); spear6xx_clk_init()
262 /* clock derived from pll3 clk */ spear6xx_clk_init()
263 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, spear6xx_clk_init()
265 clk_register_clkdev(clk, NULL, "e1800000.ehci"); spear6xx_clk_init()
266 clk_register_clkdev(clk, NULL, "e1900000.ohci"); spear6xx_clk_init()
268 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, spear6xx_clk_init()
270 clk_register_clkdev(clk, NULL, "e2000000.ehci"); spear6xx_clk_init()
271 clk_register_clkdev(clk, NULL, "e2100000.ohci"); spear6xx_clk_init()
273 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
275 clk_register_clkdev(clk, NULL, "designware_udc"); spear6xx_clk_init()
277 /* clock derived from ahb clk */ spear6xx_clk_init()
278 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, spear6xx_clk_init()
280 clk_register_clkdev(clk, "ahbmult2_clk", NULL); spear6xx_clk_init()
282 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, spear6xx_clk_init()
285 clk_register_clkdev(clk, "ddr_clk", NULL); spear6xx_clk_init()
287 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", spear6xx_clk_init()
290 clk_register_clkdev(clk, "apb_clk", NULL); spear6xx_clk_init()
292 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
294 clk_register_clkdev(clk, NULL, "fc400000.dma"); spear6xx_clk_init()
296 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
298 clk_register_clkdev(clk, NULL, "d1800000.flash"); spear6xx_clk_init()
300 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
302 clk_register_clkdev(clk, NULL, "e0800000.ethernet"); spear6xx_clk_init()
304 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
306 clk_register_clkdev(clk, NULL, "d0200000.i2c"); spear6xx_clk_init()
308 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
310 clk_register_clkdev(clk, NULL, "jpeg"); spear6xx_clk_init()
312 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
314 clk_register_clkdev(clk, NULL, "fc000000.flash"); spear6xx_clk_init()
316 /* clock derived from apb clk */ spear6xx_clk_init()
317 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
319 clk_register_clkdev(clk, NULL, "adc"); spear6xx_clk_init()
321 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); spear6xx_clk_init()
322 clk_register_clkdev(clk, NULL, "f0100000.gpio"); spear6xx_clk_init()
324 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
326 clk_register_clkdev(clk, NULL, "fc980000.gpio"); spear6xx_clk_init()
328 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
330 clk_register_clkdev(clk, NULL, "d8100000.gpio"); spear6xx_clk_init()
332 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
334 clk_register_clkdev(clk, NULL, "ssp-pl022.0"); spear6xx_clk_init()
336 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
338 clk_register_clkdev(clk, NULL, "ssp-pl022.1"); spear6xx_clk_init()
340 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
342 clk_register_clkdev(clk, NULL, "ssp-pl022.2"); spear6xx_clk_init()
|
| H A D | spear3xx_clock.c | 12 #include <linux/clk.h>
18 #include "clk.h"
143 struct clk *clk; spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); spear300_clk_init()
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, spear300_clk_init()
159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); spear300_clk_init()
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, spear300_clk_init()
163 clk_register_clkdev(clk, NULL, "a0000000.kbd"); spear300_clk_init()
173 struct clk *clk; spear310_clk_init() local
175 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, spear310_clk_init()
177 clk_register_clkdev(clk, "emi", NULL); spear310_clk_init()
179 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, spear310_clk_init()
181 clk_register_clkdev(clk, NULL, "44000000.flash"); spear310_clk_init()
183 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1, spear310_clk_init()
185 clk_register_clkdev(clk, NULL, "tdm"); spear310_clk_init()
187 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
189 clk_register_clkdev(clk, NULL, "b2000000.serial"); spear310_clk_init()
191 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
193 clk_register_clkdev(clk, NULL, "b2080000.serial"); spear310_clk_init()
195 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
197 clk_register_clkdev(clk, NULL, "b2100000.serial"); spear310_clk_init()
199 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
201 clk_register_clkdev(clk, NULL, "b2180000.serial"); spear310_clk_init()
203 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
205 clk_register_clkdev(clk, NULL, "b2200000.serial"); spear310_clk_init()
249 struct clk *ras_apb_clk) spear320_clk_init()
251 struct clk *clk; spear320_clk_init() local
253 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, spear320_clk_init()
255 clk_register_clkdev(clk, "smii_125m_pad", NULL); spear320_clk_init()
257 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, spear320_clk_init()
259 clk_register_clkdev(clk, NULL, "90000000.clcd"); spear320_clk_init()
261 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
263 clk_register_clkdev(clk, "emi", NULL); spear320_clk_init()
265 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
267 clk_register_clkdev(clk, NULL, "4c000000.flash"); spear320_clk_init()
269 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
271 clk_register_clkdev(clk, NULL, "a7000000.i2c"); spear320_clk_init()
273 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
275 clk_register_clkdev(clk, NULL, "a8000000.pwm"); spear320_clk_init()
277 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
279 clk_register_clkdev(clk, NULL, "a5000000.spi"); spear320_clk_init()
281 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
283 clk_register_clkdev(clk, NULL, "a6000000.spi"); spear320_clk_init()
285 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
287 clk_register_clkdev(clk, NULL, "c_can_platform.0"); spear320_clk_init()
289 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
291 clk_register_clkdev(clk, NULL, "c_can_platform.1"); spear320_clk_init()
293 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
295 clk_register_clkdev(clk, NULL, "a9400000.i2s"); spear320_clk_init()
297 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, spear320_clk_init()
302 clk_register_clkdev(clk, "i2s_ref_clk", NULL); spear320_clk_init()
304 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", spear320_clk_init()
307 clk_register_clkdev(clk, "i2s_sclk", NULL); spear320_clk_init()
309 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
311 clk_register_clkdev(clk, "hclk", "aa000000.eth"); spear320_clk_init()
313 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
315 clk_register_clkdev(clk, "hclk", "ab000000.eth"); spear320_clk_init()
317 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, spear320_clk_init()
322 clk_register_clkdev(clk, NULL, "a9300000.serial"); spear320_clk_init()
324 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, spear320_clk_init()
329 clk_register_clkdev(clk, NULL, "70000000.sdhci"); spear320_clk_init()
331 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, spear320_clk_init()
335 clk_register_clkdev(clk, NULL, "smii_pclk"); spear320_clk_init()
337 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); spear320_clk_init()
338 clk_register_clkdev(clk, NULL, "smii"); spear320_clk_init()
340 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, spear320_clk_init()
345 clk_register_clkdev(clk, NULL, "a3000000.serial"); spear320_clk_init()
347 clk_set_parent(clk, ras_apb_clk); spear320_clk_init()
349 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, spear320_clk_init()
354 clk_register_clkdev(clk, NULL, "a4000000.serial"); spear320_clk_init()
356 clk_set_parent(clk, ras_apb_clk); spear320_clk_init()
358 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, spear320_clk_init()
363 clk_register_clkdev(clk, NULL, "a9100000.serial"); spear320_clk_init()
365 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, spear320_clk_init()
370 clk_register_clkdev(clk, NULL, "a9200000.serial"); spear320_clk_init()
372 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, spear320_clk_init()
377 clk_register_clkdev(clk, NULL, "60000000.serial"); spear320_clk_init()
379 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, spear320_clk_init()
384 clk_register_clkdev(clk, NULL, "60100000.serial"); spear320_clk_init()
387 static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } spear320_clk_init()
392 struct clk *clk, *clk1, *ras_apb_clk; spear3xx_clk_init() local
394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear3xx_clk_init()
396 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear3xx_clk_init()
398 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, spear3xx_clk_init()
400 clk_register_clkdev(clk, "osc_24m_clk", NULL); spear3xx_clk_init()
402 /* clock derived from 32 KHz osc clk */ spear3xx_clk_init()
403 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, spear3xx_clk_init()
405 clk_register_clkdev(clk, NULL, "fc900000.rtc"); spear3xx_clk_init()
407 /* clock derived from 24 MHz osc clk */ spear3xx_clk_init()
408 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, spear3xx_clk_init()
410 clk_register_clkdev(clk, "pll3_clk", NULL); spear3xx_clk_init()
412 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, spear3xx_clk_init()
414 clk_register_clkdev(clk, NULL, "fc880000.wdt"); spear3xx_clk_init()
416 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, spear3xx_clk_init()
419 clk_register_clkdev(clk, "vco1_clk", NULL); spear3xx_clk_init()
422 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, spear3xx_clk_init()
425 clk_register_clkdev(clk, "vco2_clk", NULL); spear3xx_clk_init()
428 /* clock derived from pll1 clk */ spear3xx_clk_init()
429 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", spear3xx_clk_init()
431 clk_register_clkdev(clk, "cpu_clk", NULL); spear3xx_clk_init()
433 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", spear3xx_clk_init()
436 clk_register_clkdev(clk, "ahb_clk", NULL); spear3xx_clk_init()
438 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, spear3xx_clk_init()
441 clk_register_clkdev(clk, "uart_syn_clk", NULL); spear3xx_clk_init()
444 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, spear3xx_clk_init()
449 clk_register_clkdev(clk, "uart0_mclk", NULL); spear3xx_clk_init()
451 clk = clk_register_gate(NULL, "uart0", "uart0_mclk", spear3xx_clk_init()
454 clk_register_clkdev(clk, NULL, "d0000000.serial"); spear3xx_clk_init()
456 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, spear3xx_clk_init()
459 clk_register_clkdev(clk, "firda_syn_clk", NULL); spear3xx_clk_init()
462 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, spear3xx_clk_init()
467 clk_register_clkdev(clk, "firda_mclk", NULL); spear3xx_clk_init()
469 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", spear3xx_clk_init()
472 clk_register_clkdev(clk, NULL, "firda"); spear3xx_clk_init()
477 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, spear3xx_clk_init()
481 clk_register_clkdev(clk, NULL, "gpt0"); spear3xx_clk_init()
485 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, spear3xx_clk_init()
489 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear3xx_clk_init()
490 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", spear3xx_clk_init()
493 clk_register_clkdev(clk, NULL, "gpt1"); spear3xx_clk_init()
497 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, spear3xx_clk_init()
501 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear3xx_clk_init()
502 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", spear3xx_clk_init()
505 clk_register_clkdev(clk, NULL, "gpt2"); spear3xx_clk_init()
508 clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", spear3xx_clk_init()
511 clk_register_clkdev(clk, "gen0_syn_clk", NULL); spear3xx_clk_init()
514 clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", spear3xx_clk_init()
517 clk_register_clkdev(clk, "gen1_syn_clk", NULL); spear3xx_clk_init()
520 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, spear3xx_clk_init()
524 clk_register_clkdev(clk, "gen2_3_par_clk", NULL); spear3xx_clk_init()
526 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", spear3xx_clk_init()
529 clk_register_clkdev(clk, "gen2_syn_clk", NULL); spear3xx_clk_init()
532 clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", spear3xx_clk_init()
535 clk_register_clkdev(clk, "gen3_syn_clk", NULL); spear3xx_clk_init()
538 /* clock derived from pll3 clk */ spear3xx_clk_init()
539 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
541 clk_register_clkdev(clk, NULL, "e1800000.ehci"); spear3xx_clk_init()
542 clk_register_clkdev(clk, NULL, "e1900000.ohci"); spear3xx_clk_init()
543 clk_register_clkdev(clk, NULL, "e2100000.ohci"); spear3xx_clk_init()
545 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, spear3xx_clk_init()
547 clk_register_clkdev(clk, "usbh.0_clk", NULL); spear3xx_clk_init()
549 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, spear3xx_clk_init()
551 clk_register_clkdev(clk, "usbh.1_clk", NULL); spear3xx_clk_init()
553 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
555 clk_register_clkdev(clk, NULL, "e1100000.usbd"); spear3xx_clk_init()
557 /* clock derived from ahb clk */ spear3xx_clk_init()
558 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, spear3xx_clk_init()
560 clk_register_clkdev(clk, "ahbmult2_clk", NULL); spear3xx_clk_init()
562 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, spear3xx_clk_init()
565 clk_register_clkdev(clk, "ddr_clk", NULL); spear3xx_clk_init()
567 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", spear3xx_clk_init()
570 clk_register_clkdev(clk, "apb_clk", NULL); spear3xx_clk_init()
572 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, spear3xx_clk_init()
574 clk_register_clkdev(clk, "amem_clk", NULL); spear3xx_clk_init()
576 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
578 clk_register_clkdev(clk, NULL, "c3_clk"); spear3xx_clk_init()
580 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
582 clk_register_clkdev(clk, NULL, "fc400000.dma"); spear3xx_clk_init()
584 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
586 clk_register_clkdev(clk, NULL, "e0800000.eth"); spear3xx_clk_init()
588 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
590 clk_register_clkdev(clk, NULL, "d0180000.i2c"); spear3xx_clk_init()
592 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
594 clk_register_clkdev(clk, NULL, "jpeg"); spear3xx_clk_init()
596 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
598 clk_register_clkdev(clk, NULL, "fc000000.flash"); spear3xx_clk_init()
600 /* clock derived from apb clk */ spear3xx_clk_init()
601 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
603 clk_register_clkdev(clk, NULL, "d0080000.adc"); spear3xx_clk_init()
605 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
607 clk_register_clkdev(clk, NULL, "fc980000.gpio"); spear3xx_clk_init()
609 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
611 clk_register_clkdev(clk, NULL, "d0100000.spi"); spear3xx_clk_init()
613 /* RAS clk enable */ spear3xx_clk_init()
614 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, spear3xx_clk_init()
616 clk_register_clkdev(clk, "ras_ahb_clk", NULL); spear3xx_clk_init()
618 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, spear3xx_clk_init()
620 clk_register_clkdev(clk, "ras_apb_clk", NULL); spear3xx_clk_init()
621 ras_apb_clk = clk; spear3xx_clk_init()
623 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, spear3xx_clk_init()
625 clk_register_clkdev(clk, "ras_32k_clk", NULL); spear3xx_clk_init()
627 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, spear3xx_clk_init()
629 clk_register_clkdev(clk, "ras_24m_clk", NULL); spear3xx_clk_init()
631 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, spear3xx_clk_init()
633 clk_register_clkdev(clk, "ras_pll1_clk", NULL); spear3xx_clk_init()
635 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, spear3xx_clk_init()
637 clk_register_clkdev(clk, "ras_pll2_clk", NULL); spear3xx_clk_init()
639 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, spear3xx_clk_init()
641 clk_register_clkdev(clk, "ras_pll3_clk", NULL); spear3xx_clk_init()
643 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", spear3xx_clk_init()
646 clk_register_clkdev(clk, "ras_syn0_gclk", NULL); spear3xx_clk_init()
648 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", spear3xx_clk_init()
651 clk_register_clkdev(clk, "ras_syn1_gclk", NULL); spear3xx_clk_init()
653 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", spear3xx_clk_init()
656 clk_register_clkdev(clk, "ras_syn2_gclk", NULL); spear3xx_clk_init()
658 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", spear3xx_clk_init()
661 clk_register_clkdev(clk, "ras_syn3_gclk", NULL); spear3xx_clk_init()
|
| H A D | spear1310_clock.c | 14 #include <linux/clk.h>
20 #include "clk.h"
266 /* For gmac phy input clk */
314 /* For parent clk = 49.152 MHz */
321 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
322 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
326 /* For parent clk = 49.152 MHz */
388 struct clk *clk, *clk1; spear1310_clk_init() local
390 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
392 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear1310_clk_init()
394 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
396 clk_register_clkdev(clk, "osc_24m_clk", NULL); spear1310_clk_init()
398 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
400 clk_register_clkdev(clk, "osc_25m_clk", NULL); spear1310_clk_init()
402 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
404 clk_register_clkdev(clk, "gmii_pad_clk", NULL); spear1310_clk_init()
406 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, spear1310_clk_init()
408 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); spear1310_clk_init()
410 /* clock derived from 32 KHz osc clk */ spear1310_clk_init()
411 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, spear1310_clk_init()
414 clk_register_clkdev(clk, NULL, "e0580000.rtc"); spear1310_clk_init()
416 /* clock derived from 24 or 25 MHz osc clk */ spear1310_clk_init()
418 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, spear1310_clk_init()
422 clk_register_clkdev(clk, "vco1_mclk", NULL); spear1310_clk_init()
423 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", spear1310_clk_init()
426 clk_register_clkdev(clk, "vco1_clk", NULL); spear1310_clk_init()
429 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, spear1310_clk_init()
433 clk_register_clkdev(clk, "vco2_mclk", NULL); spear1310_clk_init()
434 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", spear1310_clk_init()
437 clk_register_clkdev(clk, "vco2_clk", NULL); spear1310_clk_init()
440 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, spear1310_clk_init()
444 clk_register_clkdev(clk, "vco3_mclk", NULL); spear1310_clk_init()
445 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", spear1310_clk_init()
448 clk_register_clkdev(clk, "vco3_clk", NULL); spear1310_clk_init()
451 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", spear1310_clk_init()
454 clk_register_clkdev(clk, "vco4_clk", NULL); spear1310_clk_init()
457 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, spear1310_clk_init()
459 clk_register_clkdev(clk, "pll5_clk", NULL); spear1310_clk_init()
461 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, spear1310_clk_init()
463 clk_register_clkdev(clk, "pll6_clk", NULL); spear1310_clk_init()
466 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, spear1310_clk_init()
468 clk_register_clkdev(clk, "vco1div2_clk", NULL); spear1310_clk_init()
470 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, spear1310_clk_init()
472 clk_register_clkdev(clk, "vco1div4_clk", NULL); spear1310_clk_init()
474 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, spear1310_clk_init()
476 clk_register_clkdev(clk, "vco2div2_clk", NULL); spear1310_clk_init()
478 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, spear1310_clk_init()
480 clk_register_clkdev(clk, "vco3div2_clk", NULL); spear1310_clk_init()
485 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, spear1310_clk_init()
488 clk_register_clkdev(clk, NULL, "spear_thermal"); spear1310_clk_init()
490 /* clock derived from pll4 clk */ spear1310_clk_init()
491 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, spear1310_clk_init()
493 clk_register_clkdev(clk, "ddr_clk", NULL); spear1310_clk_init()
495 /* clock derived from pll1 clk */ spear1310_clk_init()
496 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", spear1310_clk_init()
498 clk_register_clkdev(clk, "cpu_clk", NULL); spear1310_clk_init()
500 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, spear1310_clk_init()
502 clk_register_clkdev(clk, NULL, "ec800620.wdt"); spear1310_clk_init()
504 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, spear1310_clk_init()
506 clk_register_clkdev(clk, NULL, "smp_twd"); spear1310_clk_init()
508 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, spear1310_clk_init()
510 clk_register_clkdev(clk, "ahb_clk", NULL); spear1310_clk_init()
512 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, spear1310_clk_init()
514 clk_register_clkdev(clk, "apb_clk", NULL); spear1310_clk_init()
517 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, spear1310_clk_init()
521 clk_register_clkdev(clk, "gpt0_mclk", NULL); spear1310_clk_init()
522 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, spear1310_clk_init()
525 clk_register_clkdev(clk, NULL, "gpt0"); spear1310_clk_init()
527 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, spear1310_clk_init()
531 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear1310_clk_init()
532 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, spear1310_clk_init()
535 clk_register_clkdev(clk, NULL, "gpt1"); spear1310_clk_init()
537 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, spear1310_clk_init()
541 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear1310_clk_init()
542 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, spear1310_clk_init()
545 clk_register_clkdev(clk, NULL, "gpt2"); spear1310_clk_init()
547 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, spear1310_clk_init()
551 clk_register_clkdev(clk, "gpt3_mclk", NULL); spear1310_clk_init()
552 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, spear1310_clk_init()
555 clk_register_clkdev(clk, NULL, "gpt3"); spear1310_clk_init()
558 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", spear1310_clk_init()
561 clk_register_clkdev(clk, "uart_syn_clk", NULL); spear1310_clk_init()
564 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, spear1310_clk_init()
569 clk_register_clkdev(clk, "uart0_mclk", NULL); spear1310_clk_init()
571 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", spear1310_clk_init()
574 clk_register_clkdev(clk, NULL, "e0000000.serial"); spear1310_clk_init()
576 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", spear1310_clk_init()
579 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); spear1310_clk_init()
582 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", spear1310_clk_init()
585 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); spear1310_clk_init()
587 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", spear1310_clk_init()
590 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); spear1310_clk_init()
593 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", spear1310_clk_init()
596 clk_register_clkdev(clk, NULL, "b2800000.cf"); spear1310_clk_init()
597 clk_register_clkdev(clk, NULL, "arasan_xd"); spear1310_clk_init()
599 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", spear1310_clk_init()
602 clk_register_clkdev(clk, "c3_syn_clk", NULL); spear1310_clk_init()
605 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, spear1310_clk_init()
610 clk_register_clkdev(clk, "c3_mclk", NULL); spear1310_clk_init()
612 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, spear1310_clk_init()
615 clk_register_clkdev(clk, NULL, "c3"); spear1310_clk_init()
618 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, spear1310_clk_init()
623 clk_register_clkdev(clk, "phy_input_mclk", NULL); spear1310_clk_init()
625 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", spear1310_clk_init()
628 clk_register_clkdev(clk, "phy_syn_clk", NULL); spear1310_clk_init()
631 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, spear1310_clk_init()
635 clk_register_clkdev(clk, "stmmacphy.0", NULL); spear1310_clk_init()
638 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, spear1310_clk_init()
643 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); spear1310_clk_init()
645 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, spear1310_clk_init()
648 clk_register_clkdev(clk, "clcd_syn_clk", NULL); spear1310_clk_init()
650 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, spear1310_clk_init()
655 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); spear1310_clk_init()
657 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, spear1310_clk_init()
660 clk_register_clkdev(clk, NULL, "e1000000.clcd"); spear1310_clk_init()
663 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, spear1310_clk_init()
667 clk_register_clkdev(clk, "i2s_src_mclk", NULL); spear1310_clk_init()
669 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, spear1310_clk_init()
672 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); spear1310_clk_init()
674 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, spear1310_clk_init()
679 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); spear1310_clk_init()
681 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, spear1310_clk_init()
684 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); spear1310_clk_init()
686 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", spear1310_clk_init()
690 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); spear1310_clk_init()
693 /* clock derived from ahb clk */ spear1310_clk_init()
694 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, spear1310_clk_init()
697 clk_register_clkdev(clk, NULL, "e0280000.i2c"); spear1310_clk_init()
699 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, spear1310_clk_init()
702 clk_register_clkdev(clk, NULL, "ea800000.dma"); spear1310_clk_init()
703 clk_register_clkdev(clk, NULL, "eb000000.dma"); spear1310_clk_init()
705 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, spear1310_clk_init()
708 clk_register_clkdev(clk, NULL, "b2000000.jpeg"); spear1310_clk_init()
710 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, spear1310_clk_init()
713 clk_register_clkdev(clk, NULL, "e2000000.eth"); spear1310_clk_init()
715 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, spear1310_clk_init()
718 clk_register_clkdev(clk, NULL, "b0000000.flash"); spear1310_clk_init()
720 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, spear1310_clk_init()
723 clk_register_clkdev(clk, NULL, "ea000000.flash"); spear1310_clk_init()
725 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, spear1310_clk_init()
728 clk_register_clkdev(clk, NULL, "e4000000.ohci"); spear1310_clk_init()
729 clk_register_clkdev(clk, NULL, "e4800000.ehci"); spear1310_clk_init()
731 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, spear1310_clk_init()
734 clk_register_clkdev(clk, NULL, "e5000000.ohci"); spear1310_clk_init()
735 clk_register_clkdev(clk, NULL, "e5800000.ehci"); spear1310_clk_init()
737 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, spear1310_clk_init()
740 clk_register_clkdev(clk, NULL, "e3800000.otg"); spear1310_clk_init()
742 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, spear1310_clk_init()
745 clk_register_clkdev(clk, NULL, "b1000000.pcie"); spear1310_clk_init()
746 clk_register_clkdev(clk, NULL, "b1000000.ahci"); spear1310_clk_init()
748 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, spear1310_clk_init()
751 clk_register_clkdev(clk, NULL, "b1800000.pcie"); spear1310_clk_init()
752 clk_register_clkdev(clk, NULL, "b1800000.ahci"); spear1310_clk_init()
754 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, spear1310_clk_init()
757 clk_register_clkdev(clk, NULL, "b4000000.pcie"); spear1310_clk_init()
758 clk_register_clkdev(clk, NULL, "b4000000.ahci"); spear1310_clk_init()
760 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, spear1310_clk_init()
763 clk_register_clkdev(clk, "sysram0_clk", NULL); spear1310_clk_init()
765 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, spear1310_clk_init()
768 clk_register_clkdev(clk, "sysram1_clk", NULL); spear1310_clk_init()
770 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", spear1310_clk_init()
773 clk_register_clkdev(clk, "adc_syn_clk", NULL); spear1310_clk_init()
776 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", spear1310_clk_init()
779 clk_register_clkdev(clk, NULL, "e0080000.adc"); spear1310_clk_init()
781 /* clock derived from apb clk */ spear1310_clk_init()
782 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, spear1310_clk_init()
785 clk_register_clkdev(clk, NULL, "e0100000.spi"); spear1310_clk_init()
787 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, spear1310_clk_init()
790 clk_register_clkdev(clk, NULL, "e0600000.gpio"); spear1310_clk_init()
792 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, spear1310_clk_init()
795 clk_register_clkdev(clk, NULL, "e0680000.gpio"); spear1310_clk_init()
797 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, spear1310_clk_init()
800 clk_register_clkdev(clk, NULL, "e0180000.i2s"); spear1310_clk_init()
802 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, spear1310_clk_init()
805 clk_register_clkdev(clk, NULL, "e0200000.i2s"); spear1310_clk_init()
807 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, spear1310_clk_init()
810 clk_register_clkdev(clk, NULL, "e0300000.kbd"); spear1310_clk_init()
813 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, spear1310_clk_init()
818 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); spear1310_clk_init()
820 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, spear1310_clk_init()
825 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); spear1310_clk_init()
827 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, spear1310_clk_init()
830 clk_register_clkdev(clk, "gen_syn0_clk", NULL); spear1310_clk_init()
832 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, spear1310_clk_init()
835 clk_register_clkdev(clk, "gen_syn1_clk", NULL); spear1310_clk_init()
837 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, spear1310_clk_init()
840 clk_register_clkdev(clk, "gen_syn2_clk", NULL); spear1310_clk_init()
842 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, spear1310_clk_init()
845 clk_register_clkdev(clk, "gen_syn3_clk", NULL); spear1310_clk_init()
847 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, spear1310_clk_init()
850 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); spear1310_clk_init()
852 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, spear1310_clk_init()
855 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); spear1310_clk_init()
857 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, spear1310_clk_init()
860 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); spear1310_clk_init()
862 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, spear1310_clk_init()
865 clk_register_clkdev(clk, "ras_pll2_clk", NULL); spear1310_clk_init()
867 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, spear1310_clk_init()
870 clk_register_clkdev(clk, "ras_pll3_clk", NULL); spear1310_clk_init()
872 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, spear1310_clk_init()
875 clk_register_clkdev(clk, "ras_tx125_clk", NULL); spear1310_clk_init()
877 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, spear1310_clk_init()
879 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, spear1310_clk_init()
882 clk_register_clkdev(clk, "ras_30m_clk", NULL); spear1310_clk_init()
884 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, spear1310_clk_init()
886 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, spear1310_clk_init()
889 clk_register_clkdev(clk, "ras_48m_clk", NULL); spear1310_clk_init()
891 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, spear1310_clk_init()
894 clk_register_clkdev(clk, "ras_ahb_clk", NULL); spear1310_clk_init()
896 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, spear1310_clk_init()
899 clk_register_clkdev(clk, "ras_apb_clk", NULL); spear1310_clk_init()
901 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
904 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
907 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, spear1310_clk_init()
910 clk_register_clkdev(clk, NULL, "c_can_platform.0"); spear1310_clk_init()
912 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, spear1310_clk_init()
915 clk_register_clkdev(clk, NULL, "c_can_platform.1"); spear1310_clk_init()
917 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, spear1310_clk_init()
920 clk_register_clkdev(clk, NULL, "5c400000.eth"); spear1310_clk_init()
922 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, spear1310_clk_init()
925 clk_register_clkdev(clk, NULL, "5c500000.eth"); spear1310_clk_init()
927 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, spear1310_clk_init()
930 clk_register_clkdev(clk, NULL, "5c600000.eth"); spear1310_clk_init()
932 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, spear1310_clk_init()
935 clk_register_clkdev(clk, NULL, "5c700000.eth"); spear1310_clk_init()
937 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", spear1310_clk_init()
943 clk_register_clkdev(clk, "stmmacphy.1", NULL); spear1310_clk_init()
944 clk_register_clkdev(clk, "stmmacphy.2", NULL); spear1310_clk_init()
945 clk_register_clkdev(clk, "stmmacphy.4", NULL); spear1310_clk_init()
947 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, spear1310_clk_init()
951 clk_register_clkdev(clk, "stmmacphy.3", NULL); spear1310_clk_init()
953 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, spear1310_clk_init()
957 clk_register_clkdev(clk, "uart1_mclk", NULL); spear1310_clk_init()
959 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, spear1310_clk_init()
962 clk_register_clkdev(clk, NULL, "5c800000.serial"); spear1310_clk_init()
964 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, spear1310_clk_init()
968 clk_register_clkdev(clk, "uart2_mclk", NULL); spear1310_clk_init()
970 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, spear1310_clk_init()
973 clk_register_clkdev(clk, NULL, "5c900000.serial"); spear1310_clk_init()
975 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, spear1310_clk_init()
979 clk_register_clkdev(clk, "uart3_mclk", NULL); spear1310_clk_init()
981 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, spear1310_clk_init()
984 clk_register_clkdev(clk, NULL, "5ca00000.serial"); spear1310_clk_init()
986 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, spear1310_clk_init()
990 clk_register_clkdev(clk, "uart4_mclk", NULL); spear1310_clk_init()
992 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, spear1310_clk_init()
995 clk_register_clkdev(clk, NULL, "5cb00000.serial"); spear1310_clk_init()
997 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, spear1310_clk_init()
1001 clk_register_clkdev(clk, "uart5_mclk", NULL); spear1310_clk_init()
1003 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, spear1310_clk_init()
1006 clk_register_clkdev(clk, NULL, "5cc00000.serial"); spear1310_clk_init()
1008 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, spear1310_clk_init()
1012 clk_register_clkdev(clk, "i2c1_mclk", NULL); spear1310_clk_init()
1014 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, spear1310_clk_init()
1017 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); spear1310_clk_init()
1019 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, spear1310_clk_init()
1023 clk_register_clkdev(clk, "i2c2_mclk", NULL); spear1310_clk_init()
1025 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, spear1310_clk_init()
1028 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); spear1310_clk_init()
1030 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, spear1310_clk_init()
1034 clk_register_clkdev(clk, "i2c3_mclk", NULL); spear1310_clk_init()
1036 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, spear1310_clk_init()
1039 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); spear1310_clk_init()
1041 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, spear1310_clk_init()
1045 clk_register_clkdev(clk, "i2c4_mclk", NULL); spear1310_clk_init()
1047 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, spear1310_clk_init()
1050 clk_register_clkdev(clk, NULL, "5d000000.i2c"); spear1310_clk_init()
1052 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, spear1310_clk_init()
1056 clk_register_clkdev(clk, "i2c5_mclk", NULL); spear1310_clk_init()
1058 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, spear1310_clk_init()
1061 clk_register_clkdev(clk, NULL, "5d100000.i2c"); spear1310_clk_init()
1063 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, spear1310_clk_init()
1067 clk_register_clkdev(clk, "i2c6_mclk", NULL); spear1310_clk_init()
1069 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, spear1310_clk_init()
1072 clk_register_clkdev(clk, NULL, "5d200000.i2c"); spear1310_clk_init()
1074 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, spear1310_clk_init()
1078 clk_register_clkdev(clk, "i2c7_mclk", NULL); spear1310_clk_init()
1080 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, spear1310_clk_init()
1083 clk_register_clkdev(clk, NULL, "5d300000.i2c"); spear1310_clk_init()
1085 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, spear1310_clk_init()
1089 clk_register_clkdev(clk, "ssp1_mclk", NULL); spear1310_clk_init()
1091 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, spear1310_clk_init()
1094 clk_register_clkdev(clk, NULL, "5d400000.spi"); spear1310_clk_init()
1096 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, spear1310_clk_init()
1100 clk_register_clkdev(clk, "pci_mclk", NULL); spear1310_clk_init()
1102 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, spear1310_clk_init()
1105 clk_register_clkdev(clk, NULL, "pci"); spear1310_clk_init()
1107 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, spear1310_clk_init()
1111 clk_register_clkdev(clk, "tdm1_mclk", NULL); spear1310_clk_init()
1113 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, spear1310_clk_init()
1116 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); spear1310_clk_init()
1118 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, spear1310_clk_init()
1122 clk_register_clkdev(clk, "tdm2_mclk", NULL); spear1310_clk_init()
1124 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, spear1310_clk_init()
1127 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); spear1310_clk_init()
|
| H A D | spear1340_clock.c | 14 #include <linux/clk.h>
20 #include "clk.h"
295 /* For gmac phy input clk */
353 /* For parent clk = 49.152 MHz */
360 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
361 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
365 /* For parent clk = 49.152 MHz */
445 struct clk *clk, *clk1; spear1340_clk_init() local
447 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
449 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear1340_clk_init()
451 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
453 clk_register_clkdev(clk, "osc_24m_clk", NULL); spear1340_clk_init()
455 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
457 clk_register_clkdev(clk, "osc_25m_clk", NULL); spear1340_clk_init()
459 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
461 clk_register_clkdev(clk, "gmii_pad_clk", NULL); spear1340_clk_init()
463 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, spear1340_clk_init()
465 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); spear1340_clk_init()
467 /* clock derived from 32 KHz osc clk */ spear1340_clk_init()
468 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, spear1340_clk_init()
471 clk_register_clkdev(clk, NULL, "e0580000.rtc"); spear1340_clk_init()
473 /* clock derived from 24 or 25 MHz osc clk */ spear1340_clk_init()
475 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, spear1340_clk_init()
479 clk_register_clkdev(clk, "vco1_mclk", NULL); spear1340_clk_init()
480 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, spear1340_clk_init()
483 clk_register_clkdev(clk, "vco1_clk", NULL); spear1340_clk_init()
486 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, spear1340_clk_init()
490 clk_register_clkdev(clk, "vco2_mclk", NULL); spear1340_clk_init()
491 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, spear1340_clk_init()
494 clk_register_clkdev(clk, "vco2_clk", NULL); spear1340_clk_init()
497 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, spear1340_clk_init()
501 clk_register_clkdev(clk, "vco3_mclk", NULL); spear1340_clk_init()
502 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, spear1340_clk_init()
505 clk_register_clkdev(clk, "vco3_clk", NULL); spear1340_clk_init()
508 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", spear1340_clk_init()
511 clk_register_clkdev(clk, "vco4_clk", NULL); spear1340_clk_init()
514 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, spear1340_clk_init()
516 clk_register_clkdev(clk, "pll5_clk", NULL); spear1340_clk_init()
518 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, spear1340_clk_init()
520 clk_register_clkdev(clk, "pll6_clk", NULL); spear1340_clk_init()
523 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, spear1340_clk_init()
525 clk_register_clkdev(clk, "vco1div2_clk", NULL); spear1340_clk_init()
527 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, spear1340_clk_init()
529 clk_register_clkdev(clk, "vco1div4_clk", NULL); spear1340_clk_init()
531 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, spear1340_clk_init()
533 clk_register_clkdev(clk, "vco2div2_clk", NULL); spear1340_clk_init()
535 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, spear1340_clk_init()
537 clk_register_clkdev(clk, "vco3div2_clk", NULL); spear1340_clk_init()
542 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, spear1340_clk_init()
545 clk_register_clkdev(clk, NULL, "e07008c4.thermal"); spear1340_clk_init()
547 /* clock derived from pll4 clk */ spear1340_clk_init()
548 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, spear1340_clk_init()
550 clk_register_clkdev(clk, "ddr_clk", NULL); spear1340_clk_init()
552 /* clock derived from pll1 clk */ spear1340_clk_init()
553 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0, spear1340_clk_init()
556 clk_register_clkdev(clk, "sys_syn_clk", NULL); spear1340_clk_init()
558 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0, spear1340_clk_init()
561 clk_register_clkdev(clk, "amba_syn_clk", NULL); spear1340_clk_init()
563 clk = clk_register_mux(NULL, "sys_mclk", sys_parents, spear1340_clk_init()
567 clk_register_clkdev(clk, "sys_mclk", NULL); spear1340_clk_init()
569 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, spear1340_clk_init()
571 clk_register_clkdev(clk, "cpu_clk", NULL); spear1340_clk_init()
573 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, spear1340_clk_init()
575 clk_register_clkdev(clk, "cpu_div3_clk", NULL); spear1340_clk_init()
577 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, spear1340_clk_init()
579 clk_register_clkdev(clk, NULL, "ec800620.wdt"); spear1340_clk_init()
581 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, spear1340_clk_init()
583 clk_register_clkdev(clk, NULL, "smp_twd"); spear1340_clk_init()
585 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, spear1340_clk_init()
589 clk_register_clkdev(clk, "ahb_clk", NULL); spear1340_clk_init()
591 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, spear1340_clk_init()
593 clk_register_clkdev(clk, "apb_clk", NULL); spear1340_clk_init()
596 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, spear1340_clk_init()
600 clk_register_clkdev(clk, "gpt0_mclk", NULL); spear1340_clk_init()
601 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, spear1340_clk_init()
604 clk_register_clkdev(clk, NULL, "gpt0"); spear1340_clk_init()
606 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, spear1340_clk_init()
610 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear1340_clk_init()
611 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, spear1340_clk_init()
614 clk_register_clkdev(clk, NULL, "gpt1"); spear1340_clk_init()
616 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, spear1340_clk_init()
620 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear1340_clk_init()
621 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, spear1340_clk_init()
624 clk_register_clkdev(clk, NULL, "gpt2"); spear1340_clk_init()
626 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, spear1340_clk_init()
630 clk_register_clkdev(clk, "gpt3_mclk", NULL); spear1340_clk_init()
631 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, spear1340_clk_init()
634 clk_register_clkdev(clk, NULL, "gpt3"); spear1340_clk_init()
637 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk", spear1340_clk_init()
640 clk_register_clkdev(clk, "uart0_syn_clk", NULL); spear1340_clk_init()
643 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, spear1340_clk_init()
648 clk_register_clkdev(clk, "uart0_mclk", NULL); spear1340_clk_init()
650 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", spear1340_clk_init()
653 clk_register_clkdev(clk, NULL, "e0000000.serial"); spear1340_clk_init()
655 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", spear1340_clk_init()
658 clk_register_clkdev(clk, "uart1_syn_clk", NULL); spear1340_clk_init()
661 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, spear1340_clk_init()
665 clk_register_clkdev(clk, "uart1_mclk", NULL); spear1340_clk_init()
667 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, spear1340_clk_init()
670 clk_register_clkdev(clk, NULL, "b4100000.serial"); spear1340_clk_init()
672 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", spear1340_clk_init()
675 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); spear1340_clk_init()
678 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", spear1340_clk_init()
681 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); spear1340_clk_init()
683 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", spear1340_clk_init()
686 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); spear1340_clk_init()
689 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", spear1340_clk_init()
692 clk_register_clkdev(clk, NULL, "b2800000.cf"); spear1340_clk_init()
693 clk_register_clkdev(clk, NULL, "arasan_xd"); spear1340_clk_init()
695 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, spear1340_clk_init()
698 clk_register_clkdev(clk, "c3_syn_clk", NULL); spear1340_clk_init()
701 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, spear1340_clk_init()
706 clk_register_clkdev(clk, "c3_mclk", NULL); spear1340_clk_init()
708 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, spear1340_clk_init()
711 clk_register_clkdev(clk, NULL, "e1800000.c3"); spear1340_clk_init()
714 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, spear1340_clk_init()
719 clk_register_clkdev(clk, "phy_input_mclk", NULL); spear1340_clk_init()
721 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", spear1340_clk_init()
724 clk_register_clkdev(clk, "phy_syn_clk", NULL); spear1340_clk_init()
727 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, spear1340_clk_init()
731 clk_register_clkdev(clk, "stmmacphy.0", NULL); spear1340_clk_init()
734 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, spear1340_clk_init()
739 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); spear1340_clk_init()
741 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, spear1340_clk_init()
744 clk_register_clkdev(clk, "clcd_syn_clk", NULL); spear1340_clk_init()
746 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, spear1340_clk_init()
751 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); spear1340_clk_init()
753 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, spear1340_clk_init()
756 clk_register_clkdev(clk, NULL, "e1000000.clcd"); spear1340_clk_init()
759 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, spear1340_clk_init()
763 clk_register_clkdev(clk, "i2s_src_mclk", NULL); spear1340_clk_init()
765 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", spear1340_clk_init()
769 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); spear1340_clk_init()
771 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, spear1340_clk_init()
776 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); spear1340_clk_init()
778 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, spear1340_clk_init()
781 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); spear1340_clk_init()
783 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", spear1340_clk_init()
787 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); spear1340_clk_init()
790 /* clock derived from ahb clk */ spear1340_clk_init()
791 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, spear1340_clk_init()
794 clk_register_clkdev(clk, NULL, "e0280000.i2c"); spear1340_clk_init()
796 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, spear1340_clk_init()
799 clk_register_clkdev(clk, NULL, "b4000000.i2c"); spear1340_clk_init()
801 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, spear1340_clk_init()
804 clk_register_clkdev(clk, NULL, "ea800000.dma"); spear1340_clk_init()
805 clk_register_clkdev(clk, NULL, "eb000000.dma"); spear1340_clk_init()
807 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, spear1340_clk_init()
810 clk_register_clkdev(clk, NULL, "e2000000.eth"); spear1340_clk_init()
812 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, spear1340_clk_init()
815 clk_register_clkdev(clk, NULL, "b0000000.flash"); spear1340_clk_init()
817 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, spear1340_clk_init()
820 clk_register_clkdev(clk, NULL, "ea000000.flash"); spear1340_clk_init()
822 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, spear1340_clk_init()
825 clk_register_clkdev(clk, NULL, "e4000000.ohci"); spear1340_clk_init()
826 clk_register_clkdev(clk, NULL, "e4800000.ehci"); spear1340_clk_init()
828 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, spear1340_clk_init()
831 clk_register_clkdev(clk, NULL, "e5000000.ohci"); spear1340_clk_init()
832 clk_register_clkdev(clk, NULL, "e5800000.ehci"); spear1340_clk_init()
834 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, spear1340_clk_init()
837 clk_register_clkdev(clk, NULL, "e3800000.otg"); spear1340_clk_init()
839 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, spear1340_clk_init()
842 clk_register_clkdev(clk, NULL, "b1000000.pcie"); spear1340_clk_init()
843 clk_register_clkdev(clk, NULL, "b1000000.ahci"); spear1340_clk_init()
845 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, spear1340_clk_init()
848 clk_register_clkdev(clk, "sysram0_clk", NULL); spear1340_clk_init()
850 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, spear1340_clk_init()
853 clk_register_clkdev(clk, "sysram1_clk", NULL); spear1340_clk_init()
855 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", spear1340_clk_init()
858 clk_register_clkdev(clk, "adc_syn_clk", NULL); spear1340_clk_init()
861 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", spear1340_clk_init()
864 clk_register_clkdev(clk, NULL, "e0080000.adc"); spear1340_clk_init()
866 /* clock derived from apb clk */ spear1340_clk_init()
867 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, spear1340_clk_init()
870 clk_register_clkdev(clk, NULL, "e0100000.spi"); spear1340_clk_init()
872 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, spear1340_clk_init()
875 clk_register_clkdev(clk, NULL, "e0600000.gpio"); spear1340_clk_init()
877 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, spear1340_clk_init()
880 clk_register_clkdev(clk, NULL, "e0680000.gpio"); spear1340_clk_init()
882 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, spear1340_clk_init()
885 clk_register_clkdev(clk, NULL, "b2400000.i2s-play"); spear1340_clk_init()
887 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, spear1340_clk_init()
890 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec"); spear1340_clk_init()
892 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, spear1340_clk_init()
895 clk_register_clkdev(clk, NULL, "e0300000.kbd"); spear1340_clk_init()
898 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, spear1340_clk_init()
903 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); spear1340_clk_init()
905 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, spear1340_clk_init()
910 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); spear1340_clk_init()
912 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0, spear1340_clk_init()
915 clk_register_clkdev(clk, "gen_syn0_clk", NULL); spear1340_clk_init()
917 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0, spear1340_clk_init()
920 clk_register_clkdev(clk, "gen_syn1_clk", NULL); spear1340_clk_init()
922 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0, spear1340_clk_init()
925 clk_register_clkdev(clk, "gen_syn2_clk", NULL); spear1340_clk_init()
927 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0, spear1340_clk_init()
930 clk_register_clkdev(clk, "gen_syn3_clk", NULL); spear1340_clk_init()
932 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", spear1340_clk_init()
935 clk_register_clkdev(clk, NULL, "mali"); spear1340_clk_init()
937 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, spear1340_clk_init()
940 clk_register_clkdev(clk, NULL, "spear_cec.0"); spear1340_clk_init()
942 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0, spear1340_clk_init()
945 clk_register_clkdev(clk, NULL, "spear_cec.1"); spear1340_clk_init()
947 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, spear1340_clk_init()
952 clk_register_clkdev(clk, "spdif_out_mclk", NULL); spear1340_clk_init()
954 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", spear1340_clk_init()
957 clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); spear1340_clk_init()
959 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, spear1340_clk_init()
964 clk_register_clkdev(clk, "spdif_in_mclk", NULL); spear1340_clk_init()
966 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", spear1340_clk_init()
969 clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); spear1340_clk_init()
971 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0, spear1340_clk_init()
974 clk_register_clkdev(clk, NULL, "acp_clk"); spear1340_clk_init()
976 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0, spear1340_clk_init()
979 clk_register_clkdev(clk, NULL, "e2800000.gpio"); spear1340_clk_init()
981 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0, spear1340_clk_init()
984 clk_register_clkdev(clk, NULL, "video_dec"); spear1340_clk_init()
986 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0, spear1340_clk_init()
989 clk_register_clkdev(clk, NULL, "video_enc"); spear1340_clk_init()
991 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0, spear1340_clk_init()
994 clk_register_clkdev(clk, NULL, "spear_vip"); spear1340_clk_init()
996 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0, spear1340_clk_init()
999 clk_register_clkdev(clk, NULL, "d0200000.cam0"); spear1340_clk_init()
1001 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0, spear1340_clk_init()
1004 clk_register_clkdev(clk, NULL, "d0300000.cam1"); spear1340_clk_init()
1006 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0, spear1340_clk_init()
1009 clk_register_clkdev(clk, NULL, "d0400000.cam2"); spear1340_clk_init()
1011 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0, spear1340_clk_init()
1014 clk_register_clkdev(clk, NULL, "d0500000.cam3"); spear1340_clk_init()
1016 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0, spear1340_clk_init()
1019 clk_register_clkdev(clk, NULL, "e0180000.pwm"); spear1340_clk_init()
|
| /linux-4.1.27/arch/sh/kernel/ |
| H A D | localtimer.c | 35 struct clock_event_device *clk = this_cpu_ptr(&local_clockevent); local_timer_interrupt() local
38 clk->event_handler(clk); local_timer_interrupt()
43 struct clock_event_device *clk) dummy_timer_set_mode()
49 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); local_timer_setup() local
51 clk->name = "dummy_timer"; local_timer_setup()
52 clk->features = CLOCK_EVT_FEAT_ONESHOT | local_timer_setup()
55 clk->rating = 400; local_timer_setup()
56 clk->mult = 1; local_timer_setup()
57 clk->set_mode = dummy_timer_set_mode; local_timer_setup()
58 clk->broadcast = smp_timer_broadcast; local_timer_setup()
59 clk->cpumask = cpumask_of(cpu); local_timer_setup()
61 clockevents_register_device(clk); local_timer_setup()
42 dummy_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *clk) dummy_timer_set_mode() argument
|
| /linux-4.1.27/arch/blackfin/include/asm/ |
| H A D | clocks.h | 51 #include <linux/clk.h>
54 unsigned long (*get_rate)(struct clk *clk);
55 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
56 int (*set_rate)(struct clk *clk, unsigned long rate);
57 int (*enable)(struct clk *clk);
58 int (*disable)(struct clk *clk);
61 struct clk { struct
62 struct clk *parent;
|
| H A D | clkdev.h | 12 #define __clk_put(clk)
13 #define __clk_get(clk) ({ 1; })
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh4/ |
| H A D | clock-sh4-202.c | 25 static unsigned long emi_clk_recalc(struct clk *clk) emi_clk_recalc() argument
28 return clk->parent->rate / frqcr3_divisors[idx]; emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; frqcr3_lookup()
48 static struct clk sh4202_emi_clk = {
53 static unsigned long femi_clk_recalc(struct clk *clk) femi_clk_recalc() argument
56 return clk->parent->rate / frqcr3_divisors[idx]; femi_clk_recalc()
63 static struct clk sh4202_femi_clk = {
68 static void shoc_clk_init(struct clk *clk) shoc_clk_init() argument
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) shoc_clk_init()
91 static unsigned long shoc_clk_recalc(struct clk *clk) shoc_clk_recalc() argument
94 return clk->parent->rate / frqcr3_divisors[idx]; shoc_clk_recalc()
97 static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) shoc_clk_verify_rate() argument
99 struct clk *bclk = clk_get(NULL, "bus_clk"); shoc_clk_verify_rate()
112 static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) shoc_clk_set_rate() argument
118 if (shoc_clk_verify_rate(clk, rate) != 0) shoc_clk_set_rate()
121 tmp = frqcr3_lookup(clk, rate); shoc_clk_set_rate()
128 clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; shoc_clk_set_rate()
139 static struct clk sh4202_shoc_clk = {
144 static struct clk *sh4202_onchip_clocks[] = {
159 struct clk *clk; arch_clk_init() local
164 clk = clk_get(NULL, "master_clk"); arch_clk_init()
166 struct clk *clkp = sh4202_onchip_clocks[i]; arch_clk_init()
168 clkp->parent = clk; arch_clk_init()
172 clk_put(clk); arch_clk_init()
|
| H A D | clock-sh4.c | 29 static void master_clk_init(struct clk *clk) master_clk_init() argument
31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; master_clk_init()
38 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
41 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
48 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
51 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
58 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
61 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| /linux-4.1.27/arch/m68k/include/asm/ |
| H A D | mcfclk.h | 9 struct clk;
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
16 struct clk { struct
24 extern struct clk *mcf_clks[];
33 static struct clk __clk_##clk_bank##_##clk_slot = { \
40 void __clk_init_enabled(struct clk *);
41 void __clk_init_disabled(struct clk *);
44 static struct clk clk_##clk_ref = { \
|
| /linux-4.1.27/arch/arm/mach-w90x900/ |
| H A D | clock.c | 19 #include <linux/clk.h>
32 int clk_enable(struct clk *clk) clk_enable() argument
37 if (clk->enabled++ == 0) clk_enable()
38 (clk->enable)(clk, 1); clk_enable()
45 void clk_disable(struct clk *clk) clk_disable() argument
49 WARN_ON(clk->enabled == 0); clk_disable()
52 if (--clk->enabled == 0) clk_disable()
53 (clk->enable)(clk, 0); clk_disable()
58 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
64 void nuc900_clk_enable(struct clk *clk, int enable) nuc900_clk_enable() argument
66 unsigned int clocks = clk->cken; nuc900_clk_enable()
79 void nuc900_subclk_enable(struct clk *clk, int enable) nuc900_subclk_enable() argument
81 unsigned int clocks = clk->cken; nuc900_subclk_enable()
|
| H A D | clock.h | 15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
18 struct clk { struct
21 void (*enable)(struct clk *, int enable);
25 struct clk clk_##_name = { \
31 struct clk clk_##_name = { \
39 .clk = _clk, \
|
| /linux-4.1.27/arch/arm/plat-versatile/include/plat/ |
| H A D | clock.h | 7 long (*round)(struct clk *, unsigned long);
8 int (*set)(struct clk *, unsigned long);
9 void (*setvco)(struct clk *, struct icst_vco);
12 int icst_clk_set(struct clk *, unsigned long);
13 long icst_clk_round(struct clk *, unsigned long);
|
| /linux-4.1.27/kernel/time/ |
| H A D | posix-clock.c | 35 struct posix_clock *clk = fp->private_data; get_posix_clock() local
37 down_read(&clk->rwsem); get_posix_clock()
39 if (!clk->zombie) get_posix_clock()
40 return clk; get_posix_clock()
42 up_read(&clk->rwsem); get_posix_clock()
47 static void put_posix_clock(struct posix_clock *clk) put_posix_clock() argument
49 up_read(&clk->rwsem); put_posix_clock()
55 struct posix_clock *clk = get_posix_clock(fp); posix_clock_read() local
58 if (!clk) posix_clock_read()
61 if (clk->ops.read) posix_clock_read()
62 err = clk->ops.read(clk, fp->f_flags, buf, count); posix_clock_read()
64 put_posix_clock(clk); posix_clock_read()
71 struct posix_clock *clk = get_posix_clock(fp); posix_clock_poll() local
74 if (!clk) posix_clock_poll()
77 if (clk->ops.poll) posix_clock_poll()
78 result = clk->ops.poll(clk, fp, wait); posix_clock_poll()
80 put_posix_clock(clk); posix_clock_poll()
87 struct posix_clock *clk = get_posix_clock(fp); posix_clock_fasync() local
90 if (!clk) posix_clock_fasync()
93 if (clk->ops.fasync) posix_clock_fasync()
94 err = clk->ops.fasync(clk, fd, fp, on); posix_clock_fasync()
96 put_posix_clock(clk); posix_clock_fasync()
103 struct posix_clock *clk = get_posix_clock(fp); posix_clock_mmap() local
106 if (!clk) posix_clock_mmap()
109 if (clk->ops.mmap) posix_clock_mmap()
110 err = clk->ops.mmap(clk, vma); posix_clock_mmap()
112 put_posix_clock(clk); posix_clock_mmap()
120 struct posix_clock *clk = get_posix_clock(fp); posix_clock_ioctl() local
123 if (!clk) posix_clock_ioctl()
126 if (clk->ops.ioctl) posix_clock_ioctl()
127 err = clk->ops.ioctl(clk, cmd, arg); posix_clock_ioctl()
129 put_posix_clock(clk); posix_clock_ioctl()
138 struct posix_clock *clk = get_posix_clock(fp); posix_clock_compat_ioctl() local
141 if (!clk) posix_clock_compat_ioctl()
144 if (clk->ops.ioctl) posix_clock_compat_ioctl()
145 err = clk->ops.ioctl(clk, cmd, arg); posix_clock_compat_ioctl()
147 put_posix_clock(clk); posix_clock_compat_ioctl()
156 struct posix_clock *clk = posix_clock_open() local
159 down_read(&clk->rwsem); posix_clock_open()
161 if (clk->zombie) { posix_clock_open()
165 if (clk->ops.open) posix_clock_open()
166 err = clk->ops.open(clk, fp->f_mode); posix_clock_open()
171 kref_get(&clk->kref); posix_clock_open()
172 fp->private_data = clk; posix_clock_open()
175 up_read(&clk->rwsem); posix_clock_open()
181 struct posix_clock *clk = fp->private_data; posix_clock_release() local
184 if (clk->ops.release) posix_clock_release()
185 err = clk->ops.release(clk); posix_clock_release()
187 kref_put(&clk->kref, delete_clock); posix_clock_release()
209 int posix_clock_register(struct posix_clock *clk, dev_t devid) posix_clock_register() argument
213 kref_init(&clk->kref); posix_clock_register()
214 init_rwsem(&clk->rwsem); posix_clock_register()
216 cdev_init(&clk->cdev, &posix_clock_file_operations); posix_clock_register()
217 clk->cdev.owner = clk->ops.owner; posix_clock_register()
218 err = cdev_add(&clk->cdev, devid, 1); posix_clock_register()
226 struct posix_clock *clk = container_of(kref, struct posix_clock, kref); delete_clock() local
228 if (clk->release) delete_clock()
229 clk->release(clk); delete_clock()
232 void posix_clock_unregister(struct posix_clock *clk) posix_clock_unregister() argument
234 cdev_del(&clk->cdev); posix_clock_unregister()
236 down_write(&clk->rwsem); posix_clock_unregister()
237 clk->zombie = true; posix_clock_unregister()
238 up_write(&clk->rwsem); posix_clock_unregister()
240 kref_put(&clk->kref, delete_clock); posix_clock_unregister()
246 struct posix_clock *clk; member in struct:posix_clock_desc
261 cd->clk = get_posix_clock(fp); get_clock_desc()
263 err = cd->clk ? 0 : -ENODEV; get_clock_desc()
272 put_posix_clock(cd->clk); put_clock_desc()
290 if (cd.clk->ops.clock_adjtime) pc_clock_adjtime()
291 err = cd.clk->ops.clock_adjtime(cd.clk, tx); pc_clock_adjtime()
309 if (cd.clk->ops.clock_gettime) pc_clock_gettime()
310 err = cd.clk->ops.clock_gettime(cd.clk, ts); pc_clock_gettime()
328 if (cd.clk->ops.clock_getres) pc_clock_getres()
329 err = cd.clk->ops.clock_getres(cd.clk, ts); pc_clock_getres()
352 if (cd.clk->ops.clock_settime) pc_clock_settime()
353 err = cd.clk->ops.clock_settime(cd.clk, ts); pc_clock_settime()
372 if (cd.clk->ops.timer_create) pc_timer_create()
373 err = cd.clk->ops.timer_create(cd.clk, kit); pc_timer_create()
392 if (cd.clk->ops.timer_delete) pc_timer_delete()
393 err = cd.clk->ops.timer_delete(cd.clk, kit); pc_timer_delete()
410 if (cd.clk->ops.timer_gettime) pc_timer_gettime()
411 cd.clk->ops.timer_gettime(cd.clk, kit, ts); pc_timer_gettime()
427 if (cd.clk->ops.timer_settime) pc_timer_settime()
428 err = cd.clk->ops.timer_settime(cd.clk, kit, flags, ts, old); pc_timer_settime()
|
| /linux-4.1.27/drivers/gpu/drm/armada/ |
| H A D | armada_510.c | 10 #include <linux/clk.h>
20 struct clk *clk; armada510_crtc_init() local
22 clk = devm_clk_get(dev, "ext_ref_clk1"); armada510_crtc_init()
23 if (IS_ERR(clk)) armada510_crtc_init()
24 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); armada510_crtc_init()
26 dcrtc->extclk[0] = clk; armada510_crtc_init()
47 struct clk *clk = dcrtc->extclk[0]; armada510_crtc_compute_clock() local
53 if (IS_ERR(clk)) armada510_crtc_compute_clock()
54 return PTR_ERR(clk); armada510_crtc_compute_clock()
56 if (dcrtc->clk != clk) { armada510_crtc_compute_clock()
57 ret = clk_prepare_enable(clk); armada510_crtc_compute_clock()
60 dcrtc->clk = clk; armada510_crtc_compute_clock()
67 ref = clk_round_rate(clk, rate); armada510_crtc_compute_clock()
72 clk_set_rate(clk, ref); armada510_crtc_compute_clock()
|
| /linux-4.1.27/arch/arm/mach-versatile/include/mach/ |
| H A D | clkdev.h | 6 struct clk { struct
13 #define __clk_get(clk) ({ 1; })
14 #define __clk_put(clk) do { } while (0)
|
| /linux-4.1.27/drivers/clk/versatile/ |
| H A D | clk-realview.c | 9 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
18 #include "clk-icst.h"
53 struct clk *clk; realview_clk_init() local
56 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); realview_clk_init()
57 clk_register_clkdev(clk, "apb_pclk", NULL); realview_clk_init()
60 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, realview_clk_init()
62 clk_register_clkdev(clk, NULL, "dev:uart0"); realview_clk_init()
63 clk_register_clkdev(clk, NULL, "dev:uart1"); realview_clk_init()
64 clk_register_clkdev(clk, NULL, "dev:uart2"); realview_clk_init()
65 clk_register_clkdev(clk, NULL, "fpga:kmi0"); realview_clk_init()
66 clk_register_clkdev(clk, NULL, "fpga:kmi1"); realview_clk_init()
67 clk_register_clkdev(clk, NULL, "fpga:mmc0"); realview_clk_init()
68 clk_register_clkdev(clk, NULL, "dev:ssp0"); realview_clk_init()
74 clk_register_clkdev(clk, NULL, "dev:uart3"); realview_clk_init()
75 clk_register_clkdev(clk, NULL, "dev:uart4"); realview_clk_init()
77 clk_register_clkdev(clk, NULL, "fpga:uart3"); realview_clk_init()
81 clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, realview_clk_init()
83 clk_register_clkdev(clk, NULL, "sp804"); realview_clk_init()
87 clk = icst_clk_register(NULL, &realview_osc0_desc, realview_clk_init()
90 clk = icst_clk_register(NULL, &realview_osc4_desc, realview_clk_init()
93 clk_register_clkdev(clk, NULL, "dev:clcd"); realview_clk_init()
94 clk_register_clkdev(clk, NULL, "issp:clcd"); realview_clk_init()
|
| H A D | clk-impd1.c | 9 #include <linux/clk-provider.h>
10 #include <linux/clk.h>
14 #include <linux/platform_data/clk-integrator.h>
16 #include "clk-icst.h"
24 struct clk *pclk;
26 struct clk *vco1clk;
28 struct clk *vco2clk;
29 struct clk *mmciclk;
31 struct clk *uartclk;
33 struct clk *spiclk;
35 struct clk *scclk;
90 struct clk *clk; integrator_impd1_clk_init() local
91 struct clk *pclk; integrator_impd1_clk_init()
107 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, integrator_impd1_clk_init()
109 imc->vco1clk = clk; integrator_impd1_clk_init()
111 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id); integrator_impd1_clk_init()
115 clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, NULL, integrator_impd1_clk_init()
117 imc->vco2clk = clk; integrator_impd1_clk_init()
121 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id); integrator_impd1_clk_init()
125 clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name, integrator_impd1_clk_init()
127 imc->uartclk = clk; integrator_impd1_clk_init()
129 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id); integrator_impd1_clk_init()
131 imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id); integrator_impd1_clk_init()
135 clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name, integrator_impd1_clk_init()
138 imc->clks[9] = clkdev_alloc(clk, NULL, "lm%x:00300", id); integrator_impd1_clk_init()
147 clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name, integrator_impd1_clk_init()
149 imc->scclk = clk; integrator_impd1_clk_init()
151 imc->clks[14] = clkdev_alloc(clk, NULL, "lm%x:00600", id); integrator_impd1_clk_init()
|
| /linux-4.1.27/drivers/clk/pistachio/ |
| H A D | clk.c | 9 #include <linux/clk-provider.h>
15 #include "clk.h"
26 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); pistachio_clk_alloc_provider()
63 struct clk *clk; pistachio_clk_register_gate() local
67 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, pistachio_clk_register_gate()
71 p->clk_data.clks[gate[i].id] = clk; pistachio_clk_register_gate()
79 struct clk *clk; pistachio_clk_register_mux() local
83 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, pistachio_clk_register_mux()
89 p->clk_data.clks[mux[i].id] = clk; pistachio_clk_register_mux()
97 struct clk *clk; pistachio_clk_register_div() local
101 clk = clk_register_divider(NULL, div[i].name, div[i].parent, pistachio_clk_register_div()
105 p->clk_data.clks[div[i].id] = clk; pistachio_clk_register_div()
113 struct clk *clk; pistachio_clk_register_fixed_factor() local
117 clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent, pistachio_clk_register_fixed_factor()
119 p->clk_data.clks[ff[i].id] = clk; pistachio_clk_register_fixed_factor()
130 struct clk *clk = p->clk_data.clks[clk_ids[i]]; pistachio_clk_force_enable() local
132 if (IS_ERR(clk)) pistachio_clk_force_enable()
135 err = clk_prepare_enable(clk); pistachio_clk_force_enable()
138 __clk_get_name(clk), err); pistachio_clk_force_enable()
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-sh7780.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
37 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
54 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
57 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
77 static unsigned long shyway_clk_recalc(struct clk *clk) shyway_clk_recalc() argument
80 return clk->parent->rate / cfc_divisors[idx]; shyway_clk_recalc()
87 static struct clk sh7780_shyway_clk = {
96 static struct clk *sh7780_onchip_clocks[] = {
107 struct clk *clk; arch_clk_init() local
112 clk = clk_get(NULL, "master_clk"); arch_clk_init()
114 struct clk *clkp = sh7780_onchip_clocks[i]; arch_clk_init()
116 clkp->parent = clk; arch_clk_init()
120 clk_put(clk); arch_clk_init()
|
| H A D | clock-sh7763.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
37 return clk->parent->rate / p0fc_divisors[idx]; module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
71 static unsigned long shyway_clk_recalc(struct clk *clk) shyway_clk_recalc() argument
74 return clk->parent->rate / cfc_divisors[idx]; shyway_clk_recalc()
81 static struct clk sh7763_shyway_clk = {
90 static struct clk *sh7763_onchip_clocks[] = {
101 struct clk *clk; arch_clk_init() local
106 clk = clk_get(NULL, "master_clk"); arch_clk_init()
108 struct clk *clkp = sh7763_onchip_clocks[i]; arch_clk_init()
110 clkp->parent = clk; arch_clk_init()
114 clk_put(clk); arch_clk_init()
|
| H A D | clock-sh7770.c | 22 static void master_clk_init(struct clk *clk) master_clk_init() argument
24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; master_clk_init()
31 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
44 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
51 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
54 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| /linux-4.1.27/arch/mips/bcm63xx/ |
| H A D | clk.c | 12 #include <linux/clk.h>
19 struct clk { struct
20 void (*set)(struct clk *, int);
29 static void clk_enable_unlocked(struct clk *clk) clk_enable_unlocked() argument
31 if (clk->set && (clk->usage++) == 0) clk_enable_unlocked()
32 clk->set(clk, 1); clk_enable_unlocked()
35 static void clk_disable_unlocked(struct clk *clk) clk_disable_unlocked() argument
37 if (clk->set && (--clk->usage) == 0) clk_disable_unlocked()
38 clk->set(clk, 0); clk_disable_unlocked()
56 static void enet_misc_set(struct clk *clk, int enable) enet_misc_set() argument
72 static struct clk clk_enet_misc = {
80 static void enetx_set(struct clk *clk, int enable) enetx_set() argument
90 if (clk->id == 0) enetx_set()
98 static struct clk clk_enet0 = {
103 static struct clk clk_enet1 = {
111 static void ephy_set(struct clk *clk, int enable) ephy_set() argument
118 static struct clk clk_ephy = {
125 static void enetsw_set(struct clk *clk, int enable) enetsw_set() argument
148 static struct clk clk_enetsw = {
155 static void pcm_set(struct clk *clk, int enable) pcm_set() argument
163 static struct clk clk_pcm = {
170 static void usbh_set(struct clk *clk, int enable) usbh_set() argument
182 static struct clk clk_usbh = {
189 static void usbd_set(struct clk *clk, int enable) usbd_set() argument
199 static struct clk clk_usbd = {
206 static void spi_set(struct clk *clk, int enable) spi_set() argument
224 static struct clk clk_spi = {
231 static void hsspi_set(struct clk *clk, int enable) hsspi_set() argument
245 static struct clk clk_hsspi = {
253 static void xtm_set(struct clk *clk, int enable) xtm_set() argument
271 static struct clk clk_xtm = {
278 static void ipsec_set(struct clk *clk, int enable) ipsec_set() argument
286 static struct clk clk_ipsec = {
294 static void pcie_set(struct clk *clk, int enable) pcie_set() argument
302 static struct clk clk_pcie = {
309 static struct clk clk_periph = {
317 int clk_enable(struct clk *clk) clk_enable() argument
320 clk_enable_unlocked(clk); clk_enable()
327 void clk_disable(struct clk *clk) clk_disable() argument
330 clk_disable_unlocked(clk); clk_disable()
336 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
338 return clk->rate; clk_get_rate()
343 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
349 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
355 struct clk *clk_get(struct device *dev, const char *id) clk_get()
388 void clk_put(struct clk *clk) clk_put() argument
|
| /linux-4.1.27/arch/arm/mach-omap2/ |
| H A D | clkt_iclk.c | 14 #include <linux/clk-provider.h>
26 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) omap2_clkt_iclk_allow_idle() argument
32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); omap2_clkt_iclk_allow_idle()
34 v = omap2_clk_readl(clk, r); omap2_clkt_iclk_allow_idle()
35 v |= (1 << clk->enable_bit); omap2_clkt_iclk_allow_idle()
36 omap2_clk_writel(v, clk, r); omap2_clkt_iclk_allow_idle()
40 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) omap2_clkt_iclk_deny_idle() argument
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); omap2_clkt_iclk_deny_idle()
48 v = omap2_clk_readl(clk, r); omap2_clkt_iclk_deny_idle()
49 v &= ~(1 << clk->enable_bit); omap2_clkt_iclk_deny_idle()
50 omap2_clk_writel(v, clk, r); omap2_clkt_iclk_deny_idle()
|
| H A D | clkt_clksel.c | 44 #include <linux/clk-provider.h>
53 * _get_clksel_by_parent() - return clksel struct for a given clk & parent
54 * @clk: OMAP struct clk ptr to inspect
55 * @src_clk: OMAP struct clk ptr of the parent clk to search for
61 static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, _get_clksel_by_parent() argument
62 struct clk *src_clk) _get_clksel_by_parent()
69 for (clks = clk->clksel; clks->parent; clks++) _get_clksel_by_parent()
76 __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); _get_clksel_by_parent()
85 * @clk: struct clk * to program
96 static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) _write_clksel_reg() argument
100 v = omap2_clk_readl(clk, clk->clksel_reg); _write_clksel_reg()
101 v &= ~clk->clksel_mask; _write_clksel_reg()
102 v |= field_val << __ffs(clk->clksel_mask); _write_clksel_reg()
103 omap2_clk_writel(v, clk, clk->clksel_reg); _write_clksel_reg()
105 v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ _write_clksel_reg()
110 * @clk: OMAP struct clk to use
113 * Given a struct clk of a rate-selectable clksel clock, and a register field
119 static u32 _clksel_to_divisor(struct clk_hw_omap *clk, u32 field_val) _clksel_to_divisor() argument
123 struct clk *parent; _clksel_to_divisor()
125 parent = __clk_get_parent(clk->hw.clk); _clksel_to_divisor()
127 clks = _get_clksel_by_parent(clk, parent); _clksel_to_divisor()
142 __clk_get_name(clk->hw.clk), field_val, _clksel_to_divisor()
152 * @clk: OMAP struct clk to use
155 * Given a struct clk of a rate-selectable clksel clock, and a clock
160 static u32 _divisor_to_clksel(struct clk_hw_omap *clk, u32 div) _divisor_to_clksel() argument
164 struct clk *parent; _divisor_to_clksel()
169 parent = __clk_get_parent(clk->hw.clk); _divisor_to_clksel()
170 clks = _get_clksel_by_parent(clk, parent); _divisor_to_clksel()
184 __clk_get_name(clk->hw.clk), div, _divisor_to_clksel()
194 * @clk: OMAP struct clk to use.
196 * Read the current divisor register value for @clk that is programmed
200 static u32 _read_divisor(struct clk_hw_omap *clk) _read_divisor() argument
204 if (!clk->clksel || !clk->clksel_mask) _read_divisor()
207 v = omap2_clk_readl(clk, clk->clksel_reg); _read_divisor()
208 v &= clk->clksel_mask; _read_divisor()
209 v >>= __ffs(clk->clksel_mask); _read_divisor()
211 return _clksel_to_divisor(clk, v); _read_divisor()
218 * @clk: OMAP struct clk to use
228 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk, omap2_clksel_round_rate_div() argument
236 struct clk *parent; omap2_clksel_round_rate_div()
240 parent = __clk_get_parent(clk->hw.clk); omap2_clksel_round_rate_div()
241 clk_name = __clk_get_name(clk->hw.clk); omap2_clksel_round_rate_div()
244 if (!clk->clksel || !clk->clksel_mask) omap2_clksel_round_rate_div()
252 clks = _get_clksel_by_parent(clk, parent); omap2_clksel_round_rate_div()
289 * (i.e., those used in struct clk field function pointers, etc.)
308 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_clksel_find_parent_index() local
312 struct clk *parent; omap2_clksel_find_parent_index()
316 parent = __clk_get_parent(hw->clk); omap2_clksel_find_parent_index()
317 clk_name = __clk_get_name(hw->clk); omap2_clksel_find_parent_index()
320 WARN((!clk->clksel || !clk->clksel_mask), omap2_clksel_find_parent_index()
323 r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask; omap2_clksel_find_parent_index()
324 r >>= __ffs(clk->clksel_mask); omap2_clksel_find_parent_index()
326 for (clks = clk->clksel; clks->parent && !found; clks++) { omap2_clksel_find_parent_index()
348 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
349 * @clk: struct clk *
352 * Each clksel clock should have its struct clk .recalc field set to this
360 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_clksel_recalc() local
365 div = _read_divisor(clk); omap2_clksel_recalc()
372 __clk_get_name(hw->clk), rate, div); omap2_clksel_recalc()
379 * @clk: OMAP struct clk to use
391 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_clksel_round_rate() local
394 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); omap2_clksel_round_rate()
399 * @clk: struct clk * to program rate
403 * Program @clk's rate to @rate in the hardware. The clock can be
415 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_clksel_set_rate() local
418 if (!clk->clksel || !clk->clksel_mask) omap2_clksel_set_rate()
421 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); omap2_clksel_set_rate()
425 field_val = _divisor_to_clksel(clk, new_div); omap2_clksel_set_rate()
429 _write_clksel_reg(clk, field_val); omap2_clksel_set_rate()
431 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(hw->clk), omap2_clksel_set_rate()
432 __clk_get_rate(hw->clk)); omap2_clksel_set_rate()
438 * Clksel parent setting function - not passed in struct clk function
446 * @clk: struct clk * of the child clock
447 * @new_parent: struct clk * of the new parent clock
450 * Change the parent clock of clock @clk to @new_parent. This is
451 * intended to be used while @clk is disabled. This function does not
459 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_clksel_set_parent() local
461 if (!clk->clksel || !clk->clksel_mask) omap2_clksel_set_parent()
464 _write_clksel_reg(clk, field_val); omap2_clksel_set_parent()
|
| H A D | dpll3xxx.c | 26 #include <linux/clk.h>
43 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) _omap3_dpll_write_clken() argument
48 dd = clk->dpll_data; _omap3_dpll_write_clken()
50 v = omap2_clk_readl(clk, dd->control_reg); _omap3_dpll_write_clken()
53 omap2_clk_writel(v, clk, dd->control_reg); _omap3_dpll_write_clken()
57 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) _omap3_wait_dpll_status() argument
64 dd = clk->dpll_data; _omap3_wait_dpll_status()
65 clk_name = __clk_get_name(clk->hw.clk); _omap3_wait_dpll_status()
69 while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) _omap3_wait_dpll_status()
89 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) _omap3_dpll_compute_freqsel() argument
94 fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; _omap3_dpll_compute_freqsel()
126 * @clk: pointer to a DPLL struct clk
134 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) _omap3_noncore_dpll_lock() argument
141 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk)); _omap3_noncore_dpll_lock()
143 dd = clk->dpll_data; _omap3_noncore_dpll_lock()
147 if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) _omap3_noncore_dpll_lock()
150 ai = omap3_dpll_autoidle_read(clk); _omap3_noncore_dpll_lock()
153 omap3_dpll_deny_idle(clk); _omap3_noncore_dpll_lock()
155 _omap3_dpll_write_clken(clk, DPLL_LOCKED); _omap3_noncore_dpll_lock()
157 r = _omap3_wait_dpll_status(clk, 1); _omap3_noncore_dpll_lock()
160 omap3_dpll_allow_idle(clk); _omap3_noncore_dpll_lock()
168 * @clk: pointer to a DPLL struct clk
179 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) _omap3_noncore_dpll_bypass() argument
184 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) _omap3_noncore_dpll_bypass()
188 __clk_get_name(clk->hw.clk)); _omap3_noncore_dpll_bypass()
190 ai = omap3_dpll_autoidle_read(clk); _omap3_noncore_dpll_bypass()
192 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); _omap3_noncore_dpll_bypass()
194 r = _omap3_wait_dpll_status(clk, 0); _omap3_noncore_dpll_bypass()
197 omap3_dpll_allow_idle(clk); _omap3_noncore_dpll_bypass()
204 * @clk: pointer to a DPLL struct clk
211 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) _omap3_noncore_dpll_stop() argument
215 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) _omap3_noncore_dpll_stop()
218 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk)); _omap3_noncore_dpll_stop()
220 ai = omap3_dpll_autoidle_read(clk); _omap3_noncore_dpll_stop()
222 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); _omap3_noncore_dpll_stop()
225 omap3_dpll_allow_idle(clk); _omap3_noncore_dpll_stop()
232 * @clk: pointer to a DPLL struct clk
242 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) _lookup_dco() argument
246 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); _lookup_dco()
257 * @clk: pointer to a DPLL struct clk
267 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) _lookup_sddiv() argument
272 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); _lookup_sddiv()
291 * @clk: struct clk * of DPLL to set
297 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) omap3_noncore_dpll_program() argument
299 struct dpll_data *dd = clk->dpll_data; omap3_noncore_dpll_program()
304 _omap3_noncore_dpll_bypass(clk); omap3_noncore_dpll_program()
311 v = omap2_clk_readl(clk, dd->control_reg); omap3_noncore_dpll_program()
314 omap2_clk_writel(v, clk, dd->control_reg); omap3_noncore_dpll_program()
318 v = omap2_clk_readl(clk, dd->mult_div1_reg); omap3_noncore_dpll_program()
334 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); omap3_noncore_dpll_program()
339 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, omap3_noncore_dpll_program()
345 omap2_clk_writel(v, clk, dd->mult_div1_reg); omap3_noncore_dpll_program()
349 v = omap2_clk_readl(clk, dd->control_reg); omap3_noncore_dpll_program()
365 omap2_clk_writel(v, clk, dd->control_reg); omap3_noncore_dpll_program()
372 _omap3_noncore_dpll_lock(clk); omap3_noncore_dpll_program()
381 * @clk: DPLL struct clk
387 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_dpll_recalc() local
389 return omap2_get_dpll_rate(clk); omap3_dpll_recalc()
396 * @clk: pointer to a DPLL struct clk
403 * to enter the target state. Intended to be used as the struct clk's
410 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_enable() local
415 dd = clk->dpll_data; omap3_noncore_dpll_enable()
419 if (clk->clkdm) { omap3_noncore_dpll_enable()
420 r = clkdm_clk_enable(clk->clkdm, hw->clk); omap3_noncore_dpll_enable()
424 __func__, __clk_get_name(hw->clk), omap3_noncore_dpll_enable()
425 clk->clkdm->name, r); omap3_noncore_dpll_enable()
430 parent = __clk_get_hw(__clk_get_parent(hw->clk)); omap3_noncore_dpll_enable()
432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { omap3_noncore_dpll_enable()
434 r = _omap3_noncore_dpll_bypass(clk); omap3_noncore_dpll_enable()
437 r = _omap3_noncore_dpll_lock(clk); omap3_noncore_dpll_enable()
445 * @clk: pointer to a DPLL struct clk
452 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_disable() local
454 _omap3_noncore_dpll_stop(clk); omap3_noncore_dpll_disable()
455 if (clk->clkdm) omap3_noncore_dpll_disable()
456 clkdm_clk_disable(clk->clkdm, hw->clk); omap3_noncore_dpll_disable()
481 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_determine_rate() local
487 dd = clk->dpll_data; omap3_noncore_dpll_determine_rate()
514 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_set_parent() local
521 ret = _omap3_noncore_dpll_bypass(clk); omap3_noncore_dpll_set_parent()
523 ret = _omap3_noncore_dpll_lock(clk); omap3_noncore_dpll_set_parent()
542 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_set_rate() local
550 dd = clk->dpll_data; omap3_noncore_dpll_set_rate()
554 if (__clk_get_hw(__clk_get_parent(hw->clk)) != omap3_noncore_dpll_set_rate()
563 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); omap3_noncore_dpll_set_rate()
568 __clk_get_name(hw->clk), rate); omap3_noncore_dpll_set_rate()
570 ret = omap3_noncore_dpll_program(clk, freqsel); omap3_noncore_dpll_set_rate()
599 * clk-ref at index[0], in which case we only need to set rate, omap3_noncore_dpll_set_rate_and_parent()
601 * With clk-bypass case we only need to change parent. omap3_noncore_dpll_set_rate_and_parent()
615 * @clk: struct clk * of the DPLL to read
618 * -EINVAL if passed a null pointer or if the struct clk does not
621 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) omap3_dpll_autoidle_read() argument
626 if (!clk || !clk->dpll_data) omap3_dpll_autoidle_read()
629 dd = clk->dpll_data; omap3_dpll_autoidle_read()
634 v = omap2_clk_readl(clk, dd->autoidle_reg); omap3_dpll_autoidle_read()
643 * @clk: struct clk * of the DPLL to operate on
650 void omap3_dpll_allow_idle(struct clk_hw_omap *clk) omap3_dpll_allow_idle() argument
655 if (!clk || !clk->dpll_data) omap3_dpll_allow_idle()
658 dd = clk->dpll_data; omap3_dpll_allow_idle()
668 v = omap2_clk_readl(clk, dd->autoidle_reg); omap3_dpll_allow_idle()
671 omap2_clk_writel(v, clk, dd->autoidle_reg); omap3_dpll_allow_idle()
677 * @clk: struct clk * of the DPLL to operate on
681 void omap3_dpll_deny_idle(struct clk_hw_omap *clk) omap3_dpll_deny_idle() argument
686 if (!clk || !clk->dpll_data) omap3_dpll_deny_idle()
689 dd = clk->dpll_data; omap3_dpll_deny_idle()
694 v = omap2_clk_readl(clk, dd->autoidle_reg); omap3_dpll_deny_idle()
697 omap2_clk_writel(v, clk, dd->autoidle_reg); omap3_dpll_deny_idle()
707 struct clk *parent; omap3_find_clkoutx2_dpll()
709 /* Walk up the parents of clk, looking for a DPLL */ omap3_find_clkoutx2_dpll()
712 parent = __clk_get_parent(hw->clk); omap3_find_clkoutx2_dpll()
714 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC)); omap3_find_clkoutx2_dpll()
720 /* clk does not have a DPLL as a parent? error in the clock data */ omap3_find_clkoutx2_dpll()
731 * @clk: DPLL output struct clk
790 *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate); omap3_clkoutx2_round_rate()
803 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { omap3_clkoutx2_round_rate()
807 *prate = __clk_round_rate(__clk_get_parent(hw->clk), omap3_clkoutx2_round_rate()
|
| H A D | clock3xxx.h | 12 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
15 extern struct clk *sdrc_ick_p;
16 extern struct clk *arm_fck_p;
|
| H A D | omap_hwmod_33xx_43xx_interconnect_data.c | 25 .clk = "dpll_mpu_m2_ck",
33 .clk = "l3s_gclk",
41 .clk = "l3s_gclk",
49 .clk = "l3s_gclk",
57 .clk = "l3s_gclk",
65 .clk = "dpll_mpu_m2_ck",
73 .clk = "l3s_gclk",
81 .clk = "l3_gclk",
89 .clk = "dpll_core_m4_ck",
97 .clk = "dpll_core_m4_ck",
105 .clk = "clkdiv32k_ick",
113 .clk = "l4ls_gclk",
121 .clk = "l4ls_gclk",
129 .clk = "l4ls_gclk",
137 .clk = "l4ls_gclk",
145 .clk = "l4ls_gclk",
167 .clk = "l4ls_gclk",
184 .clk = "l4ls_gclk",
192 .clk = "l4ls_gclk",
199 .clk = "l4ls_gclk",
206 .clk = "l4ls_gclk",
223 .clk = "l4ls_gclk",
231 .clk = "l4ls_gclk",
238 .clk = "l4ls_gclk",
245 .clk = "l4ls_gclk",
261 .clk = "l4ls_gclk",
269 .clk = "l4ls_gclk",
276 .clk = "l4ls_gclk",
283 .clk = "l4ls_gclk",
300 .clk = "l3s_gclk",
309 .clk = "l4ls_gclk",
316 .clk = "l4ls_gclk",
324 .clk = "l4ls_gclk",
332 .clk = "l4ls_gclk",
349 .clk = "l4ls_gclk",
367 .clk = "l4ls_gclk",
385 .clk = "l4ls_gclk",
403 .clk = "l4ls_gclk",
421 .clk = "l3s_gclk",
430 .clk = "l4ls_gclk",
438 .clk = "l4ls_gclk",
446 .clk = "l4ls_gclk",
454 .clk = "l4ls_gclk",
462 .clk = "l4ls_gclk",
470 .clk = "l4ls_gclk",
478 .clk = "l4ls_gclk",
486 .clk = "l4ls_gclk",
494 .clk = "l3_gclk",
511 .clk = "l3_gclk",
529 .clk = "l3_gclk",
547 .clk = "l3_gclk",
556 .clk = "l4ls_gclk",
564 .clk = "l4ls_gclk",
572 .clk = "l4ls_gclk",
580 .clk = "l4ls_gclk",
588 .clk = "l4ls_gclk",
612 .clk = "sha0_fck",
630 .clk = "aes0_fck",
|
| H A D | clkt2xxx_dpll.c | 14 #include <linux/clk.h>
25 * @clk: struct clk * of the DPLL to operate on
32 static void _allow_idle(struct clk_hw_omap *clk) _allow_idle() argument
34 if (!clk || !clk->dpll_data) _allow_idle()
42 * @clk: struct clk * of the DPLL to operate on
46 static void _deny_idle(struct clk_hw_omap *clk) _deny_idle() argument
48 if (!clk || !clk->dpll_data) _deny_idle()
|
| H A D | dpll44xx.c | 14 #include <linux/clk.h>
39 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) omap4_dpllmx_allow_gatectrl() argument
44 if (!clk || !clk->clksel_reg) omap4_dpllmx_allow_gatectrl()
47 mask = clk->flags & CLOCK_CLKOUTX2 ? omap4_dpllmx_allow_gatectrl()
51 v = omap2_clk_readl(clk, clk->clksel_reg); omap4_dpllmx_allow_gatectrl()
54 omap2_clk_writel(v, clk, clk->clksel_reg); omap4_dpllmx_allow_gatectrl()
57 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) omap4_dpllmx_deny_gatectrl() argument
62 if (!clk || !clk->clksel_reg) omap4_dpllmx_deny_gatectrl()
65 mask = clk->flags & CLOCK_CLKOUTX2 ? omap4_dpllmx_deny_gatectrl()
69 v = omap2_clk_readl(clk, clk->clksel_reg); omap4_dpllmx_deny_gatectrl()
72 omap2_clk_writel(v, clk, clk->clksel_reg); omap4_dpllmx_deny_gatectrl()
107 * @clk: struct clk * of the DPLL to compute the rate for
109 * Compute the output rate for the OMAP4 DPLL represented by @clk.
117 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap4_dpll_regm4xen_recalc() local
122 if (!clk || !clk->dpll_data) omap4_dpll_regm4xen_recalc()
125 dd = clk->dpll_data; omap4_dpll_regm4xen_recalc()
127 rate = omap2_get_dpll_rate(clk); omap4_dpll_regm4xen_recalc()
130 v = omap2_clk_readl(clk, dd->control_reg); omap4_dpll_regm4xen_recalc()
139 * @clk: struct clk * of the DPLL to round a rate for
143 * for @clk if set_rate() were to be provided with the rate
146 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
153 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap4_dpll_regm4xen_round_rate() local
157 if (!clk || !clk->dpll_data) omap4_dpll_regm4xen_round_rate()
160 dd = clk->dpll_data; omap4_dpll_regm4xen_round_rate()
210 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap4_dpll_regm4xen_determine_rate() local
216 dd = clk->dpll_data; omap4_dpll_regm4xen_determine_rate()
|
| H A D | clock36xx.c | 22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
33 * @clk: DPLL output struct clk
41 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) omap36xx_pwrdn_clk_enable_with_hsdiv_restore() argument
46 struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk); omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
50 ret = omap2_dflt_clk_enable(clk); omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
52 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); omap36xx_pwrdn_clk_enable_with_hsdiv_restore()
|
| H A D | omap_hwmod_2xxx_interconnect_data.c | 65 .clk = "uart1_ick",
73 .clk = "uart2_ick",
81 .clk = "uart3_ick",
89 .clk = "mcspi1_ick",
97 .clk = "mcspi2_ick",
105 .clk = "gpt2_ick",
113 .clk = "gpt3_ick",
121 .clk = "gpt4_ick",
129 .clk = "gpt5_ick",
137 .clk = "gpt6_ick",
145 .clk = "gpt7_ick",
153 .clk = "gpt8_ick",
161 .clk = "gpt9_ick",
169 .clk = "gpt10_ick",
177 .clk = "gpt11_ick",
185 .clk = "gpt12_ick",
193 .clk = "dss_ick",
208 .clk = "dss_ick",
223 .clk = "dss_ick",
238 .clk = "dss_ick",
254 .clk = "rng_ick",
262 .clk = "sha_ick",
270 .clk = "aes_ick",
|
| H A D | clock.c | 23 #include <linux/clk-provider.h>
111 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) omap2_clk_writel() argument
113 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) omap2_clk_writel()
119 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) omap2_clk_readl() argument
121 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) omap2_clk_readl()
193 * @clk: module clock to wait for (needed for register offsets)
205 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, _wait_idlest_generic() argument
212 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), _wait_idlest_generic()
227 * @clk: struct clk * belonging to the module
230 * corresponds to clock @clk are enabled, then wait for the module to
235 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) _omap2_module_wait_ready() argument
243 if (clk->ops->find_companion) { _omap2_module_wait_ready()
244 clk->ops->find_companion(clk, &companion_reg, &other_bit); _omap2_module_wait_ready()
245 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) _omap2_module_wait_ready()
249 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); _omap2_module_wait_ready()
253 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), _omap2_module_wait_ready()
254 idlest_val, __clk_get_name(clk->hw.clk)); _omap2_module_wait_ready()
264 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
265 * @clk: OMAP clock struct ptr to use
267 * Convert a clockdomain name stored in a struct clk 'clk' into a
268 * clockdomain pointer, and save it into the struct clk. Intended to be
273 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_init_clk_clkdm() local
277 if (!clk->clkdm_name) omap2_init_clk_clkdm()
280 clk_name = __clk_get_name(hw->clk); omap2_init_clk_clkdm()
282 clkdm = clkdm_lookup(clk->clkdm_name); omap2_init_clk_clkdm()
284 pr_debug("clock: associated clk %s to clkdm %s\n", omap2_init_clk_clkdm()
285 clk_name, clk->clkdm_name); omap2_init_clk_clkdm()
286 clk->clkdm = clkdm; omap2_init_clk_clkdm()
288 pr_debug("clock: could not associate clk %s to clkdm %s\n", omap2_init_clk_clkdm()
289 clk_name, clk->clkdm_name); omap2_init_clk_clkdm()
294 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
307 * omap2_clk_dflt_find_companion - find companion clock to @clk
308 * @clk: struct clk * to find the companion clock of
327 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, omap2_clk_dflt_find_companion() argument
336 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); omap2_clk_dflt_find_companion()
339 *other_bit = clk->enable_bit; omap2_clk_dflt_find_companion()
343 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
344 * @clk: struct clk * to find IDLEST info for
356 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, omap2_clk_dflt_find_idlest() argument
361 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); omap2_clk_dflt_find_idlest()
363 *idlest_bit = clk->enable_bit; omap2_clk_dflt_find_idlest()
387 struct clk_hw_omap *clk; omap2_dflt_clk_enable() local
391 clk = to_clk_hw_omap(hw); omap2_dflt_clk_enable()
393 if (clkdm_control && clk->clkdm) { omap2_dflt_clk_enable()
394 ret = clkdm_clk_enable(clk->clkdm, hw->clk); omap2_dflt_clk_enable()
397 __func__, __clk_get_name(hw->clk), omap2_dflt_clk_enable()
398 clk->clkdm->name, ret); omap2_dflt_clk_enable()
403 if (unlikely(clk->enable_reg == NULL)) { omap2_dflt_clk_enable()
405 __clk_get_name(hw->clk)); omap2_dflt_clk_enable()
411 v = omap2_clk_readl(clk, clk->enable_reg); omap2_dflt_clk_enable()
412 if (clk->flags & INVERT_ENABLE) omap2_dflt_clk_enable()
413 v &= ~(1 << clk->enable_bit); omap2_dflt_clk_enable()
415 v |= (1 << clk->enable_bit); omap2_dflt_clk_enable()
416 omap2_clk_writel(v, clk, clk->enable_reg); omap2_dflt_clk_enable()
417 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ omap2_dflt_clk_enable()
419 if (clk->ops && clk->ops->find_idlest) omap2_dflt_clk_enable()
420 _omap2_module_wait_ready(clk); omap2_dflt_clk_enable()
425 if (clkdm_control && clk->clkdm) omap2_dflt_clk_enable()
426 clkdm_clk_disable(clk->clkdm, hw->clk); omap2_dflt_clk_enable()
441 struct clk_hw_omap *clk; omap2_dflt_clk_disable() local
444 clk = to_clk_hw_omap(hw); omap2_dflt_clk_disable()
445 if (!clk->enable_reg) { omap2_dflt_clk_disable()
451 __func__, __clk_get_name(hw->clk)); omap2_dflt_clk_disable()
455 v = omap2_clk_readl(clk, clk->enable_reg); omap2_dflt_clk_disable()
456 if (clk->flags & INVERT_ENABLE) omap2_dflt_clk_disable()
457 v |= (1 << clk->enable_bit); omap2_dflt_clk_disable()
459 v &= ~(1 << clk->enable_bit); omap2_dflt_clk_disable()
460 omap2_clk_writel(v, clk, clk->enable_reg); omap2_dflt_clk_disable()
463 if (clkdm_control && clk->clkdm) omap2_dflt_clk_disable()
464 clkdm_clk_disable(clk->clkdm, hw->clk); omap2_dflt_clk_disable()
481 struct clk_hw_omap *clk; omap2_clkops_enable_clkdm() local
484 clk = to_clk_hw_omap(hw); omap2_clkops_enable_clkdm()
486 if (unlikely(!clk->clkdm)) { omap2_clkops_enable_clkdm()
488 __clk_get_name(hw->clk)); omap2_clkops_enable_clkdm()
492 if (unlikely(clk->enable_reg)) omap2_clkops_enable_clkdm()
494 __clk_get_name(hw->clk)); omap2_clkops_enable_clkdm()
498 __func__, __clk_get_name(hw->clk)); omap2_clkops_enable_clkdm()
502 ret = clkdm_clk_enable(clk->clkdm, hw->clk); omap2_clkops_enable_clkdm()
504 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); omap2_clkops_enable_clkdm()
520 struct clk_hw_omap *clk; omap2_clkops_disable_clkdm() local
522 clk = to_clk_hw_omap(hw); omap2_clkops_disable_clkdm()
524 if (unlikely(!clk->clkdm)) { omap2_clkops_disable_clkdm()
526 __clk_get_name(hw->clk)); omap2_clkops_disable_clkdm()
530 if (unlikely(clk->enable_reg)) omap2_clkops_disable_clkdm()
532 __clk_get_name(hw->clk)); omap2_clkops_disable_clkdm()
536 __func__, __clk_get_name(hw->clk)); omap2_clkops_disable_clkdm()
540 clkdm_clk_disable(clk->clkdm, hw->clk); omap2_clkops_disable_clkdm()
553 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_dflt_clk_is_enabled() local
556 v = omap2_clk_readl(clk, clk->enable_reg); omap2_dflt_clk_is_enabled()
558 if (clk->flags & INVERT_ENABLE) omap2_dflt_clk_is_enabled()
559 v ^= BIT(clk->enable_bit); omap2_dflt_clk_is_enabled()
561 v &= BIT(clk->enable_bit); omap2_dflt_clk_is_enabled()
588 * @clk: struct clk * to initialize
590 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used
595 void omap2_init_clk_hw_omap_clocks(struct clk *clk) omap2_init_clk_hw_omap_clocks() argument
599 if (__clk_get_flags(clk) & CLK_IS_BASIC) omap2_init_clk_hw_omap_clocks()
602 c = to_clk_hw_omap(__clk_get_hw(clk)); omap2_init_clk_hw_omap_clocks()
652 * @clk: struct clk * to disable autoidle for
656 int omap2_clk_deny_idle(struct clk *clk) omap2_clk_deny_idle() argument
660 if (__clk_get_flags(clk) & CLK_IS_BASIC) omap2_clk_deny_idle()
663 c = to_clk_hw_omap(__clk_get_hw(clk)); omap2_clk_deny_idle()
671 * @clk: struct clk * to enable autoidle for
675 int omap2_clk_allow_idle(struct clk *clk) omap2_clk_allow_idle() argument
679 if (__clk_get_flags(clk) & CLK_IS_BASIC) omap2_clk_allow_idle()
682 c = to_clk_hw_omap(__clk_get_hw(clk)); omap2_clk_allow_idle()
700 struct clk *init_clk; omap2_clk_enable_init_clocks()
719 * @mpurate_ck_name: clk name of the clock to change rate
729 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
734 struct clk *mpurate_ck; omap2_clk_switch_mpurate_at_boot()
760 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
761 * @core_ck_name: clk name for the on-chip CORE_CLK
762 * @mpu_ck_name: clk name for the ARM MPU clock
774 struct clk *hfclkin_ck, *core_ck, *mpu_ck; omap2_clk_print_new_rates()
|
| H A D | clock.h | 23 #include <linux/clk-provider.h>
24 #include <linux/clk/ti.h>
36 .clk = ck, \
50 static struct clk _name = { \
64 static struct clk _name = { \
71 .clk = &_name, \
79 static struct clk _name; \
82 .clk = &_name, \
95 static struct clk _name; \
98 .clk = &_name, \
132 * struct clksel_rate - register bitfield values corresponding to clk divisors
137 * @val should match the value of a read from struct clk.clksel_reg
138 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
151 * @parent: struct clk * to a possible parent clock
158 struct clk *parent;
183 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
184 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
185 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
186 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
187 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
192 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
204 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
205 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
207 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
209 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
212 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
216 int omap2_clk_allow_idle(struct clk *clk);
217 int omap2_clk_deny_idle(struct clk *clk);
223 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
224 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
|
| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| H A D | clock.c | 16 #include <linux/clk.h>
30 struct clk { struct
31 struct clk *parent;
38 unsigned long (*get_rate)(struct clk *clk);
39 int (*set_rate)(struct clk *clk, unsigned long rate);
43 static unsigned long get_uart_rate(struct clk *clk);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
50 static struct clk clk_xtali = {
53 static struct clk clk_uart1 = {
60 static struct clk clk_uart2 = {
67 static struct clk clk_uart3 = {
74 static struct clk clk_pll1 = {
77 static struct clk clk_f = {
80 static struct clk clk_h = {
83 static struct clk clk_p = {
86 static struct clk clk_pll2 = {
89 static struct clk clk_usb_host = {
94 static struct clk clk_keypad = {
101 static struct clk clk_spi = {
105 static struct clk clk_pwm = {
110 static struct clk clk_video = {
117 static struct clk clk_i2s_mclk = {
124 static struct clk clk_i2s_sclk = {
132 static struct clk clk_i2s_lrclk = {
141 static struct clk clk_m2p0 = {
146 static struct clk clk_m2p1 = {
151 static struct clk clk_m2p2 = {
156 static struct clk clk_m2p3 = {
161 static struct clk clk_m2p4 = {
166 static struct clk clk_m2p5 = {
171 static struct clk clk_m2p6 = {
176 static struct clk clk_m2p7 = {
181 static struct clk clk_m2p8 = {
186 static struct clk clk_m2p9 = {
191 static struct clk clk_m2m0 = {
196 static struct clk clk_m2m1 = {
203 { .dev_id = dev, .con_id = con, .clk = ck }
239 static void __clk_enable(struct clk *clk) __clk_enable() argument
241 if (!clk->users++) { __clk_enable()
242 if (clk->parent) __clk_enable()
243 __clk_enable(clk->parent); __clk_enable()
245 if (clk->enable_reg) { __clk_enable()
248 v = __raw_readl(clk->enable_reg); __clk_enable()
249 v |= clk->enable_mask; __clk_enable()
250 if (clk->sw_locked) __clk_enable()
251 ep93xx_syscon_swlocked_write(v, clk->enable_reg); __clk_enable()
253 __raw_writel(v, clk->enable_reg); __clk_enable()
258 int clk_enable(struct clk *clk) clk_enable() argument
262 if (!clk) clk_enable()
266 __clk_enable(clk); clk_enable()
273 static void __clk_disable(struct clk *clk) __clk_disable() argument
275 if (!--clk->users) { __clk_disable()
276 if (clk->enable_reg) { __clk_disable()
279 v = __raw_readl(clk->enable_reg); __clk_disable()
280 v &= ~clk->enable_mask; __clk_disable()
281 if (clk->sw_locked) __clk_disable()
282 ep93xx_syscon_swlocked_write(v, clk->enable_reg); __clk_disable()
284 __raw_writel(v, clk->enable_reg); __clk_disable()
287 if (clk->parent) __clk_disable()
288 __clk_disable(clk->parent); __clk_disable()
292 void clk_disable(struct clk *clk) clk_disable() argument
296 if (!clk) clk_disable()
300 __clk_disable(clk); clk_disable()
305 static unsigned long get_uart_rate(struct clk *clk) get_uart_rate() argument
307 unsigned long rate = clk_get_rate(clk->parent); get_uart_rate()
317 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
319 if (clk->get_rate) clk_get_rate()
320 return clk->get_rate(clk); clk_get_rate()
322 return clk->rate; clk_get_rate()
326 static int set_keytchclk_rate(struct clk *clk, unsigned long rate) set_keytchclk_rate() argument
331 val = __raw_readl(clk->enable_reg); set_keytchclk_rate()
340 div_bit = clk->enable_mask >> 15; set_keytchclk_rate()
349 ep93xx_syscon_swlocked_write(val, clk->enable_reg); set_keytchclk_rate()
350 clk->rate = rate; set_keytchclk_rate()
354 static int calc_clk_div(struct clk *clk, unsigned long rate, calc_clk_div() argument
357 struct clk *mclk; calc_clk_div()
396 clk->parent = mclk; calc_clk_div()
397 clk->rate = actual_rate; calc_clk_div()
410 static int set_div_rate(struct clk *clk, unsigned long rate) set_div_rate() argument
415 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); set_div_rate()
420 val = __raw_readl(clk->enable_reg); set_div_rate()
427 ep93xx_syscon_swlocked_write(val, clk->enable_reg); set_div_rate()
431 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) set_i2s_sclk_rate() argument
433 unsigned val = __raw_readl(clk->enable_reg); set_i2s_sclk_rate()
437 clk->enable_reg); set_i2s_sclk_rate()
440 clk->enable_reg); set_i2s_sclk_rate()
448 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) set_i2s_lrclk_rate() argument
450 unsigned val = __raw_readl(clk->enable_reg) & set_i2s_lrclk_rate()
455 clk->enable_reg); set_i2s_lrclk_rate()
458 clk->enable_reg); set_i2s_lrclk_rate()
461 clk->enable_reg); set_i2s_lrclk_rate()
469 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
471 if (clk->set_rate) clk_set_rate()
472 return clk->set_rate(clk, rate); clk_set_rate()
|
| /linux-4.1.27/drivers/cpufreq/ |
| H A D | ls1x-cpufreq.c | 11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
25 struct clk *clk; /* CPU clk */ member in struct:__anon3772
26 struct clk *mux_clk; /* MUX of CPU clk */
27 struct clk *pll_clk; /* PLL clk */
28 struct clk *osc_clk; /* OSC clk */
55 * The procedure of reconfiguring CPU clk is as below. ls1x_cpufreq_target()
57 * - Reparent CPU clk to OSC clk ls1x_cpufreq_target()
60 * - Reparent CPU clk back to CPU DIV clk ls1x_cpufreq_target()
64 clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk); ls1x_cpufreq_target()
70 clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk); ls1x_cpufreq_target()
105 policy->clk = ls1x_cpufreq.clk; ls1x_cpufreq_init()
142 struct clk *clk; ls1x_cpufreq_probe() local
150 clk = devm_clk_get(&pdev->dev, pdata->clk_name); ls1x_cpufreq_probe()
151 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
154 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
157 ls1x_cpufreq.clk = clk; ls1x_cpufreq_probe()
159 clk = clk_get_parent(clk); ls1x_cpufreq_probe()
160 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
162 __clk_get_name(ls1x_cpufreq.clk)); ls1x_cpufreq_probe()
163 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
166 ls1x_cpufreq.mux_clk = clk; ls1x_cpufreq_probe()
168 clk = clk_get_parent(clk); ls1x_cpufreq_probe()
169 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
172 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
175 ls1x_cpufreq.pll_clk = clk; ls1x_cpufreq_probe()
177 clk = devm_clk_get(&pdev->dev, pdata->osc_clk_name); ls1x_cpufreq_probe()
178 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
181 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
184 ls1x_cpufreq.osc_clk = clk; ls1x_cpufreq_probe()
|
| /linux-4.1.27/drivers/clk/tegra/ |
| H A D | clk-tegra-fixed.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
24 #include <linux/clk/tegra.h>
26 #include "clk.h"
27 #include "clk-id.h"
38 struct clk *clk, *osc; tegra_osc_clk_init() local
39 struct clk **dt_clk; tegra_osc_clk_init()
63 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", tegra_osc_clk_init()
65 *dt_clk = clk; tegra_osc_clk_init()
74 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc", tegra_osc_clk_init()
76 *dt_clk = clk; tegra_osc_clk_init()
86 struct clk *clk; tegra_fixed_clk_init() local
87 struct clk **dt_clk; tegra_fixed_clk_init()
92 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, tegra_fixed_clk_init()
94 *dt_clk = clk; tegra_fixed_clk_init()
100 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", tegra_fixed_clk_init()
102 *dt_clk = clk; tegra_fixed_clk_init()
108 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", tegra_fixed_clk_init()
110 *dt_clk = clk; tegra_fixed_clk_init()
|
| H A D | clk-tegra-super-gen4.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
24 #include <linux/clk/tegra.h>
26 #include "clk.h"
27 #include "clk-id.h"
56 struct clk *clk; tegra_sclk_init() local
57 struct clk **dt_clk; tegra_sclk_init()
62 clk = tegra_clk_register_super_mux("sclk", sclk_parents, tegra_sclk_init()
67 *dt_clk = clk; tegra_sclk_init()
73 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, tegra_sclk_init()
76 clk = clk_register_gate(NULL, "hclk", "hclk_div", tegra_sclk_init()
80 *dt_clk = clk; tegra_sclk_init()
88 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, tegra_sclk_init()
91 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | tegra_sclk_init()
94 *dt_clk = clk; tegra_sclk_init()
102 struct clk *clk; tegra_super_clk_gen4_init() local
103 struct clk **dt_clk; tegra_super_clk_gen4_init()
108 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, tegra_super_clk_gen4_init()
113 *dt_clk = clk; tegra_super_clk_gen4_init()
119 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, tegra_super_clk_gen4_init()
124 *dt_clk = clk; tegra_super_clk_gen4_init()
135 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, tegra_super_clk_gen4_init()
137 *dt_clk = clk; tegra_super_clk_gen4_init()
144 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", tegra_super_clk_gen4_init()
146 *dt_clk = clk; tegra_super_clk_gen4_init()
|
| H A D | clk-tegra-pmc.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
25 #include <linux/clk/tegra.h>
27 #include "clk.h"
28 #include "clk-id.h"
85 struct clk *clk; tegra_pmc_clk_init() local
86 struct clk **dt_clk; tegra_pmc_clk_init()
98 clk = clk_register_mux(NULL, data->mux_name, data->parents, tegra_pmc_clk_init()
102 *dt_clk = clk; tegra_pmc_clk_init()
109 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, tegra_pmc_clk_init()
112 *dt_clk = clk; tegra_pmc_clk_init()
113 clk_register_clkdev(clk, data->dev_name, data->gate_name); tegra_pmc_clk_init()
118 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, tegra_pmc_clk_init()
126 clk = clk_register_gate(NULL, "blink", "blink_override", 0, tegra_pmc_clk_init()
129 clk_register_clkdev(clk, "blink", NULL); tegra_pmc_clk_init()
130 *dt_clk = clk; tegra_pmc_clk_init()
|
| H A D | clk-tegra-audio.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
24 #include <linux/clk/tegra.h>
26 #include "clk.h"
27 #include "clk-id.h"
131 struct clk *clk; tegra_audio_clk_init() local
132 struct clk **dt_clk; tegra_audio_clk_init()
138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, tegra_audio_clk_init()
140 *dt_clk = clk; tegra_audio_clk_init()
146 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", tegra_audio_clk_init()
149 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", tegra_audio_clk_init()
152 *dt_clk = clk; tegra_audio_clk_init()
164 clk = tegra_clk_register_sync_source(data->name, tegra_audio_clk_init()
166 *dt_clk = clk; tegra_audio_clk_init()
177 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk, tegra_audio_clk_init()
182 *dt_clk = clk; tegra_audio_clk_init()
188 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, tegra_audio_clk_init()
191 *dt_clk = clk; tegra_audio_clk_init()
202 clk = clk_register_fixed_factor(NULL, data->name_2x, tegra_audio_clk_init()
204 clk = tegra_clk_register_divider(data->div_name, tegra_audio_clk_init()
208 clk = tegra_clk_register_periph_gate(data->gate_name, tegra_audio_clk_init()
212 *dt_clk = clk; tegra_audio_clk_init()
|
| /linux-4.1.27/arch/mips/lantiq/falcon/ |
| H A D | sysctrl.c | 18 #include "../clk.h"
82 static inline void sysctl_wait(struct clk *clk, sysctl_wait() argument
87 do {} while (--err && ((sysctl_r32(clk->module, reg) sysctl_wait()
88 & clk->bits) != test)); sysctl_wait()
91 clk->module, clk->bits, test, sysctl_wait()
92 sysctl_r32(clk->module, reg) & clk->bits); sysctl_wait()
95 static int sysctl_activate(struct clk *clk) sysctl_activate() argument
97 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); sysctl_activate()
98 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_activate()
99 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); sysctl_activate()
103 static void sysctl_deactivate(struct clk *clk) sysctl_deactivate() argument
105 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); sysctl_deactivate()
106 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); sysctl_deactivate()
107 sysctl_wait(clk, 0, SYSCTL_ACTS); sysctl_deactivate()
110 static int sysctl_clken(struct clk *clk) sysctl_clken() argument
112 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); sysctl_clken()
113 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_clken()
114 sysctl_wait(clk, clk->bits, SYSCTL_CLKS); sysctl_clken()
118 static void sysctl_clkdis(struct clk *clk) sysctl_clkdis() argument
120 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); sysctl_clkdis()
121 sysctl_wait(clk, 0, SYSCTL_CLKS); sysctl_clkdis()
124 static void sysctl_reboot(struct clk *clk) sysctl_reboot() argument
129 act = sysctl_r32(clk->module, SYSCTL_ACT); sysctl_reboot()
130 bits = ~act & clk->bits; sysctl_reboot()
132 sysctl_w32(clk->module, bits, SYSCTL_CLKEN); sysctl_reboot()
133 sysctl_w32(clk->module, bits, SYSCTL_ACT); sysctl_reboot()
134 sysctl_wait(clk, bits, SYSCTL_ACTS); sysctl_reboot()
136 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT); sysctl_reboot()
137 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); sysctl_reboot()
170 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_sys() local
172 clk->cl.dev_id = dev; clkdev_add_sys()
173 clk->cl.con_id = NULL; clkdev_add_sys()
174 clk->cl.clk = clk; clkdev_add_sys()
175 clk->module = module; clkdev_add_sys()
176 clk->bits = bits; clkdev_add_sys()
177 clk->activate = sysctl_activate; clkdev_add_sys()
178 clk->deactivate = sysctl_deactivate; clkdev_add_sys()
179 clk->enable = sysctl_clken; clkdev_add_sys()
180 clk->disable = sysctl_clkdis; clkdev_add_sys()
181 clk->reboot = sysctl_reboot; clkdev_add_sys()
182 clkdev_add(&clk->cl); clkdev_add_sys()
|
| /linux-4.1.27/include/asm-generic/ |
| H A D | clkdev.h | 11 * Helper for the clk API to assist looking up a struct clk.
19 struct clk;
21 static inline int __clk_get(struct clk *clk) { return 1; } __clk_put() argument
22 static inline void __clk_put(struct clk *clk) { } __clk_put() argument
|
| /linux-4.1.27/drivers/clk/hisilicon/ |
| H A D | clk.c | 27 #include <linux/clk-provider.h>
35 #include <linux/clk.h>
37 #include "clk.h"
45 struct clk **clk_table; hisi_clk_init()
66 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); hisi_clk_init()
84 struct clk *clk; hisi_clk_register_fixed_rate() local
88 clk = clk_register_fixed_rate(NULL, clks[i].name, hisi_clk_register_fixed_rate()
92 if (IS_ERR(clk)) { hisi_clk_register_fixed_rate()
97 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_fixed_rate()
105 struct clk *clk; hisi_clk_register_fixed_factor() local
109 clk = clk_register_fixed_factor(NULL, clks[i].name, hisi_clk_register_fixed_factor()
113 if (IS_ERR(clk)) { hisi_clk_register_fixed_factor()
118 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_fixed_factor()
125 struct clk *clk; hisi_clk_register_mux() local
132 clk = clk_register_mux_table(NULL, clks[i].name, hisi_clk_register_mux()
138 if (IS_ERR(clk)) { hisi_clk_register_mux()
145 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_mux()
147 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_mux()
154 struct clk *clk; hisi_clk_register_divider() local
159 clk = clk_register_divider_table(NULL, clks[i].name, hisi_clk_register_divider()
167 if (IS_ERR(clk)) { hisi_clk_register_divider()
174 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_divider()
176 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_divider()
183 struct clk *clk; hisi_clk_register_gate() local
188 clk = clk_register_gate(NULL, clks[i].name, hisi_clk_register_gate()
195 if (IS_ERR(clk)) { hisi_clk_register_gate()
202 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_gate()
204 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_gate()
211 struct clk *clk; hisi_clk_register_gate_sep() local
216 clk = hisi_register_clkgate_sep(NULL, clks[i].name, hisi_clk_register_gate_sep()
223 if (IS_ERR(clk)) { hisi_clk_register_gate_sep()
230 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_gate_sep()
232 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_gate_sep()
|
| H A D | clk-hix5hd2.c | 14 #include "clk.h"
174 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_ether_prepare() local
177 val = readl_relaxed(clk->ctrl_reg); clk_ether_prepare()
178 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); clk_ether_prepare()
180 val &= ~(clk->ctrl_rst_mask); clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); clk_ether_prepare()
184 val |= clk->phy_clk_mask; clk_ether_prepare()
185 val &= ~(clk->phy_rst_mask); clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
189 val &= ~(clk->phy_clk_mask); clk_ether_prepare()
190 val |= clk->phy_rst_mask; clk_ether_prepare()
191 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
194 val |= clk->phy_clk_mask; clk_ether_prepare()
195 val &= ~(clk->phy_rst_mask); clk_ether_prepare()
196 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
203 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_ether_unprepare() local
206 val = readl_relaxed(clk->ctrl_reg); clk_ether_unprepare()
207 val &= ~(clk->ctrl_clk_mask); clk_ether_unprepare()
208 writel_relaxed(val, clk->ctrl_reg); clk_ether_unprepare()
218 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_complex_enable() local
221 val = readl_relaxed(clk->ctrl_reg); clk_complex_enable()
222 val |= clk->ctrl_clk_mask; clk_complex_enable()
223 val &= ~(clk->ctrl_rst_mask); clk_complex_enable()
224 writel_relaxed(val, clk->ctrl_reg); clk_complex_enable()
226 val = readl_relaxed(clk->phy_reg); clk_complex_enable()
227 val |= clk->phy_clk_mask; clk_complex_enable()
228 val &= ~(clk->phy_rst_mask); clk_complex_enable()
229 writel_relaxed(val, clk->phy_reg); clk_complex_enable()
236 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_complex_disable() local
239 val = readl_relaxed(clk->ctrl_reg); clk_complex_disable()
240 val |= clk->ctrl_rst_mask; clk_complex_disable()
241 val &= ~(clk->ctrl_clk_mask); clk_complex_disable()
242 writel_relaxed(val, clk->ctrl_reg); clk_complex_disable()
244 val = readl_relaxed(clk->phy_reg); clk_complex_disable()
245 val |= clk->phy_rst_mask; clk_complex_disable()
246 val &= ~(clk->phy_clk_mask); clk_complex_disable()
247 writel_relaxed(val, clk->phy_reg); clk_complex_disable()
263 struct clk *clk; hix5hd2_clk_register_complex() local
289 clk = clk_register(NULL, &p_clk->hw); hix5hd2_clk_register_complex()
290 if (IS_ERR(clk)) { hix5hd2_clk_register_complex()
297 data->clk_data.clks[clks[i].id] = clk; hix5hd2_clk_register_complex()
|
| /linux-4.1.27/arch/mips/pistachio/ |
| H A D | time.c | 11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
34 struct clk *clk; plat_time_init() local
45 clk = of_clk_get(np, 0); plat_time_init()
46 if (IS_ERR(clk)) { plat_time_init()
47 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); plat_time_init()
51 mips_hpt_frequency = clk_get_rate(clk) / 2; plat_time_init()
52 clk_put(clk); plat_time_init()
|
| /linux-4.1.27/include/media/ |
| H A D | v4l2-clk.h | 25 struct clk;
33 struct clk *clk; member in struct:v4l2_clk
39 int (*enable)(struct v4l2_clk *clk);
40 void (*disable)(struct v4l2_clk *clk);
41 unsigned long (*get_rate)(struct v4l2_clk *clk);
42 int (*set_rate)(struct v4l2_clk *clk, unsigned long);
48 void v4l2_clk_unregister(struct v4l2_clk *clk);
50 void v4l2_clk_put(struct v4l2_clk *clk);
51 int v4l2_clk_enable(struct v4l2_clk *clk);
52 void v4l2_clk_disable(struct v4l2_clk *clk);
53 unsigned long v4l2_clk_get_rate(struct v4l2_clk *clk);
54 int v4l2_clk_set_rate(struct v4l2_clk *clk, unsigned long rate);
60 void v4l2_clk_unregister_fixed(struct v4l2_clk *clk);
|
| /linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.1.27/arch/arm/mach-shmobile/ |
| H A D | clock.h | 6 struct clk;
7 unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
23 struct clk name = { \
|
| H A D | clock.c | 6 * Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c.
27 unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) shmobile_fixed_ratio_clk_recalc() argument
29 struct clk_ratio *p = clk->priv; shmobile_fixed_ratio_clk_recalc()
31 return clk->parent->rate / p->div * p->mul; shmobile_fixed_ratio_clk_recalc()
|
| /linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.1.27/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh5/ |
| H A D | clock-sh5.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
28 clk->rate *= ifc_table[idx]; master_clk_init()
35 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
38 return clk->parent->rate / ifc_table[idx]; module_clk_recalc()
45 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
48 return clk->parent->rate / ifc_table[idx]; bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_table[idx]; cpu_clk_recalc()
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh2a/ |
| H A D | clock-sh7201.c | 27 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate = 10000000 * pll2_mult * master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
40 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
47 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
50 return clk->parent->rate / pfc_divisors[idx]; bus_clk_recalc()
57 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
60 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7206.c | 27 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
39 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
48 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7203.c | 30 static void master_clk_init(struct clk *clk) master_clk_init() argument
32 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; master_clk_init()
39 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
52 return clk->parent->rate / pfc_divisors[idx-2]; bus_clk_recalc()
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh3/ |
| H A D | clock-sh3.c | 29 static void master_clk_init(struct clk *clk) master_clk_init() argument
34 clk->rate *= pfc_divisors[idx]; master_clk_init()
41 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
46 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
53 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
58 return clk->parent->rate / stc_multipliers[idx]; bus_clk_recalc()
65 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
70 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7705.c | 33 static void master_clk_init(struct clk *clk) master_clk_init() argument
35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; master_clk_init()
42 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
45 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
52 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
55 return clk->parent->rate / stc_multipliers[idx]; bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
65 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7706.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
54 return clk->parent->rate / stc_multipliers[idx]; bus_clk_recalc()
61 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
66 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7709.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
55 return clk->parent->rate * stc_multipliers[idx]; bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
67 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7710.c | 27 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
39 return clk->parent->rate / md_table[idx]; module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
49 return clk->parent->rate / md_table[idx]; bus_clk_recalc()
56 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
59 return clk->parent->rate / md_table[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7712.c | 24 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate *= multipliers[idx]; master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
41 return clk->parent->rate / divisors[idx]; module_clk_recalc()
48 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
53 return clk->parent->rate / divisors[idx]; cpu_clk_recalc()
|
| /linux-4.1.27/drivers/clk/rockchip/ |
| H A D | clk.c | 7 * samsung/clk.c
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
29 #include "clk.h"
41 static struct clk *rockchip_clk_register_branch(const char *name, rockchip_clk_register_branch()
49 struct clk *clk; rockchip_clk_register_branch() local
96 clk = clk_register_composite(NULL, name, parent_names, num_parents, rockchip_clk_register_branch()
102 return clk; rockchip_clk_register_branch()
105 static struct clk *rockchip_clk_register_frac_branch(const char *name, rockchip_clk_register_frac_branch()
111 struct clk *clk; rockchip_clk_register_frac_branch() local
144 clk = clk_register_composite(NULL, name, parent_names, num_parents, rockchip_clk_register_frac_branch()
150 return clk; rockchip_clk_register_frac_branch()
154 static struct clk **clk_table;
167 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); rockchip_clk_init()
183 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) rockchip_clk_add_lookup() argument
186 clk_table[id] = clk; rockchip_clk_add_lookup()
192 struct clk *clk; rockchip_clk_register_plls() local
196 clk = rockchip_clk_register_pll(list->type, list->name, rockchip_clk_register_plls()
202 if (IS_ERR(clk)) { rockchip_clk_register_plls()
208 rockchip_clk_add_lookup(clk, list->id); rockchip_clk_register_plls()
216 struct clk *clk = NULL; rockchip_clk_register_branches() local
226 clk = clk_register_mux(NULL, list->name, rockchip_clk_register_branches()
234 clk = clk_register_divider_table(NULL, rockchip_clk_register_branches()
241 clk = clk_register_divider(NULL, list->name, rockchip_clk_register_branches()
248 clk = rockchip_clk_register_frac_branch(list->name, rockchip_clk_register_branches()
257 clk = clk_register_gate(NULL, list->name, rockchip_clk_register_branches()
263 clk = rockchip_clk_register_branch(list->name, rockchip_clk_register_branches()
273 clk = rockchip_clk_register_mmc( rockchip_clk_register_branches()
283 if (!clk) { rockchip_clk_register_branches()
289 if (IS_ERR(clk)) { rockchip_clk_register_branches()
291 __func__, list->name, PTR_ERR(clk)); rockchip_clk_register_branches()
295 rockchip_clk_add_lookup(clk, list->id); rockchip_clk_register_branches()
306 struct clk *clk; rockchip_clk_register_armclk() local
308 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, rockchip_clk_register_armclk()
311 if (IS_ERR(clk)) { rockchip_clk_register_armclk()
313 __func__, name, PTR_ERR(clk)); rockchip_clk_register_armclk()
317 rockchip_clk_add_lookup(clk, lookup_id); rockchip_clk_register_armclk()
327 struct clk *clk = __clk_lookup(clocks[i]); rockchip_clk_protect_critical() local
329 if (clk) rockchip_clk_protect_critical()
330 clk_prepare_enable(clk); rockchip_clk_protect_critical()
|
| /linux-4.1.27/arch/sh/kernel/cpu/ |
| H A D | clock-cpg.c | 1 #include <linux/clk.h>
8 static struct clk master_clk = {
13 static struct clk peripheral_clk = {
18 static struct clk bus_clk = {
23 static struct clk cpu_clk = {
31 static struct clk *onchip_clocks[] = {
51 struct clk *clk = onchip_clocks[i]; cpg_clk_init() local
52 arch_init_clk_ops(&clk->ops, i); cpg_clk_init()
53 if (clk->ops) cpg_clk_init()
54 ret |= clk_register(clk); cpg_clk_init()
|
| /linux-4.1.27/arch/arm/mach-lpc32xx/ |
| H A D | clock.h | 22 struct clk { struct
24 struct clk *parent;
28 int (*set_rate) (struct clk *, unsigned long);
29 unsigned long (*round_rate) (struct clk *, unsigned long);
30 unsigned long (*get_rate) (struct clk *clk);
31 int (*enable) (struct clk *, int);
|
| H A D | clock.c | 92 #include <linux/clk.h>
106 static struct clk clk_armpll;
107 static struct clk clk_usbpll;
114 static unsigned long local_return_parent_rate(struct clk *clk) local_return_parent_rate() argument
120 while (clk->rate == 0) local_return_parent_rate()
121 clk = clk->parent; local_return_parent_rate()
123 return clk->rate; local_return_parent_rate()
127 static struct clk osc_32KHz = {
132 static int local_pll397_enable(struct clk *clk, int enable) local_pll397_enable() argument
161 static int local_oscmain_enable(struct clk *clk, int enable) local_oscmain_enable() argument
190 static struct clk osc_pll397 = {
197 static struct clk osc_main = {
203 static struct clk clk_sys;
367 static struct clk clk_armpll = {
387 static int local_usbpll_enable(struct clk *clk, int enable) local_usbpll_enable() argument
451 static unsigned long local_usbpll_round_rate(struct clk *clk, local_usbpll_round_rate() argument
463 clkin = clk->get_rate(clk); local_usbpll_round_rate()
475 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate) local_usbpll_set_rate() argument
487 clkin = clk->get_rate(clk->parent); local_usbpll_set_rate()
499 local_usbpll_enable(clk, 0); local_usbpll_set_rate()
510 ret = local_usbpll_enable(clk, 1); local_usbpll_set_rate()
512 clk->rate = clk_check_pll_setup(clkin, &pllsetup); local_usbpll_set_rate()
517 static struct clk clk_usbpll = {
533 static struct clk clk_hclk = {
538 static struct clk clk_pclk = {
543 static int local_onoff_enable(struct clk *clk, int enable) local_onoff_enable() argument
547 tmp = __raw_readl(clk->enable_reg); local_onoff_enable()
550 tmp &= ~clk->enable_mask; local_onoff_enable()
552 tmp |= clk->enable_mask; local_onoff_enable()
554 __raw_writel(tmp, clk->enable_reg); local_onoff_enable()
560 static struct clk clk_timer0 = {
567 static struct clk clk_timer1 = {
574 static struct clk clk_timer2 = {
581 static struct clk clk_timer3 = {
588 static struct clk clk_mpwm = {
595 static struct clk clk_wdt = {
602 static struct clk clk_vfp9 = {
609 static struct clk clk_dma = {
617 static struct clk clk_pwm = {
630 static struct clk clk_uart3 = {
638 static struct clk clk_uart4 = {
646 static struct clk clk_uart5 = {
654 static struct clk clk_uart6 = {
662 static struct clk clk_i2c0 = {
670 static struct clk clk_i2c1 = {
678 static struct clk clk_i2c2 = {
686 static struct clk clk_ssp0 = {
694 static struct clk clk_ssp1 = {
702 static struct clk clk_kscan = {
710 static struct clk clk_nand = {
719 static struct clk clk_nand_mlc = {
729 static struct clk clk_i2s0 = {
737 static struct clk clk_i2s1 = {
746 static struct clk clk_net = {
756 static struct clk clk_rtc = {
762 static int local_usb_enable(struct clk *clk, int enable) local_usb_enable() argument
773 return local_onoff_enable(clk, enable); local_usb_enable()
776 static struct clk clk_usbd = {
787 static int local_usb_otg_enable(struct clk *clk, int enable) local_usb_otg_enable() argument
792 __raw_writel(clk->enable_mask, clk->enable_reg); local_usb_otg_enable()
795 clk->enable_mask) != clk->enable_mask) && (to > 0)) local_usb_otg_enable()
798 __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); local_usb_otg_enable()
811 static struct clk clk_usb_otg_dev = {
822 static struct clk clk_usb_otg_host = {
833 static int tsc_onoff_enable(struct clk *clk, int enable) tsc_onoff_enable() argument
843 __raw_writel(0, clk->enable_reg); tsc_onoff_enable()
845 __raw_writel(clk->enable_mask, clk->enable_reg); tsc_onoff_enable()
850 static struct clk clk_tsc = {
858 static int adc_onoff_enable(struct clk *clk, int enable) adc_onoff_enable() argument
870 divider = clk->get_rate(clk) / 4500000 + 1; adc_onoff_enable()
875 clk->rate = clk->get_rate(clk->parent) / divider; adc_onoff_enable()
878 __raw_writel(0, clk->enable_reg); adc_onoff_enable()
880 __raw_writel(clk->enable_mask, clk->enable_reg); adc_onoff_enable()
885 static struct clk clk_adc = {
893 static int mmc_onoff_enable(struct clk *clk, int enable) mmc_onoff_enable() argument
915 static unsigned long mmc_get_rate(struct clk *clk) mmc_get_rate() argument
927 rate = clk->parent->get_rate(clk->parent); mmc_get_rate()
938 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) mmc_round_rate() argument
943 prate = clk->parent->get_rate(clk->parent); mmc_round_rate()
955 static int mmc_set_rate(struct clk *clk, unsigned long rate) mmc_set_rate() argument
958 unsigned long prate, div, crate = mmc_round_rate(clk, rate); mmc_set_rate()
960 prate = clk->parent->get_rate(clk->parent); mmc_set_rate()
974 static struct clk clk_mmc = {
984 static unsigned long clcd_get_rate(struct clk *clk) clcd_get_rate() argument
995 rate = clk->parent->get_rate(clk->parent); clcd_get_rate()
1007 static int clcd_set_rate(struct clk *clk, unsigned long rate) clcd_set_rate() argument
1017 prate = clk->parent->get_rate(clk->parent); clcd_set_rate()
1038 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate) clcd_round_rate() argument
1042 prate = clk->parent->get_rate(clk->parent); clcd_round_rate()
1057 static struct clk clk_lcd = {
1067 static void local_clk_disable(struct clk *clk) local_clk_disable() argument
1070 if (clk->usecount > 0) { local_clk_disable()
1071 clk->usecount--; local_clk_disable()
1074 if ((clk->usecount == 0) && (clk->enable)) local_clk_disable()
1075 clk->enable(clk, 0); local_clk_disable()
1078 if (clk->parent) local_clk_disable()
1079 local_clk_disable(clk->parent); local_clk_disable()
1083 static int local_clk_enable(struct clk *clk) local_clk_enable() argument
1088 if (clk->parent) local_clk_enable()
1089 ret = local_clk_enable(clk->parent); local_clk_enable()
1093 if ((clk->usecount == 0) && (clk->enable)) local_clk_enable()
1094 ret = clk->enable(clk, 1); local_clk_enable()
1097 clk->usecount++; local_clk_enable()
1098 else if (clk->parent) local_clk_enable()
1099 local_clk_disable(clk->parent); local_clk_enable()
1108 int clk_enable(struct clk *clk) clk_enable() argument
1114 ret = local_clk_enable(clk); clk_enable()
1124 void clk_disable(struct clk *clk) clk_disable() argument
1129 local_clk_disable(clk); clk_disable()
1137 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
1139 return clk->get_rate(clk); clk_get_rate()
1146 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
1155 if (clk->set_rate) clk_set_rate()
1156 ret = clk->set_rate(clk, rate); clk_set_rate()
1165 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
1167 if (clk->round_rate) clk_round_rate()
1168 rate = clk->round_rate(clk, rate); clk_round_rate()
1170 rate = clk->get_rate(clk); clk_round_rate()
1179 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
1189 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
1191 return clk->parent; clk_get_parent()
|
| /linux-4.1.27/drivers/clk/pxa/ |
| H A D | clk-pxa.c | 13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
19 #include "clk-pxa.h"
23 static struct clk *pxa_clocks[CLK_MAX];
72 const char *dev_id, struct clk *clk) clkdev_pxa_register()
74 if (!IS_ERR(clk) && (ckid != CLK_NONE)) clkdev_pxa_register()
75 pxa_clocks[ckid] = clk; clkdev_pxa_register()
76 if (!IS_ERR(clk)) clkdev_pxa_register()
77 clk_register_clkdev(clk, con_id, dev_id); clkdev_pxa_register()
84 struct clk *clk; clk_pxa_cken_init() local
93 clk = clk_register_composite(NULL, clks[i].name, clk_pxa_cken_init()
100 clks[i].dev_id, clk); clk_pxa_cken_init()
71 clkdev_pxa_register(int ckid, const char *con_id, const char *dev_id, struct clk *clk) clkdev_pxa_register() argument
|
| /linux-4.1.27/drivers/clk/sunxi/ |
| H A D | clk-sun6i-apb0.c | 11 #include <linux/clk-provider.h>
17 * The APB0 clk has a configurable divisor.
38 struct clk *clk; sun6i_a31_apb0_clk_probe() local
51 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, sun6i_a31_apb0_clk_probe()
54 if (IS_ERR(clk)) sun6i_a31_apb0_clk_probe()
55 return PTR_ERR(clk); sun6i_a31_apb0_clk_probe()
57 return of_clk_add_provider(np, of_clk_src_simple_get, clk); sun6i_a31_apb0_clk_probe()
61 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
67 .name = "sun6i-a31-apb0-clk",
|
| H A D | clk-sun8i-apb0.c | 9 * Based on clk-sun6i-apb0.c
17 #include <linux/clk-provider.h>
29 struct clk *clk; sun8i_a23_apb0_clk_probe() local
43 clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg, sun8i_a23_apb0_clk_probe()
45 if (IS_ERR(clk)) sun8i_a23_apb0_clk_probe()
46 return PTR_ERR(clk); sun8i_a23_apb0_clk_probe()
48 return of_clk_add_provider(np, of_clk_src_simple_get, clk); sun8i_a23_apb0_clk_probe()
52 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
58 .name = "sun8i-a23-apb0-clk",
|
| H A D | clk-sun6i-ar100.c | 11 #include <linux/clk-provider.h>
39 struct ar100_clk *clk = to_ar100_clk(hw); ar100_recalc_rate() local
40 u32 val = readl(clk->reg); ar100_recalc_rate()
53 int nparents = __clk_get_num_parents(hw->clk); ar100_determine_rate()
62 struct clk *parent; ar100_determine_rate()
66 parent = clk_get_parent_by_index(hw->clk, i); ar100_determine_rate()
71 * The AR100 clk contains 2 divisors: ar100_determine_rate()
116 struct ar100_clk *clk = to_ar100_clk(hw); ar100_set_parent() local
117 u32 val = readl(clk->reg); ar100_set_parent()
124 writel(val, clk->reg); ar100_set_parent()
131 struct ar100_clk *clk = to_ar100_clk(hw); ar100_get_parent() local
132 return (readl(clk->reg) >> SUN6I_AR100_MUX_SHIFT) & ar100_get_parent()
140 struct ar100_clk *clk = to_ar100_clk(hw); ar100_set_rate() local
141 u32 val = readl(clk->reg); ar100_set_rate()
160 writel(val, clk->reg); ar100_set_rate()
181 struct clk *clk; sun6i_a31_ar100_clk_probe() local
211 clk = clk_register(&pdev->dev, &ar100->hw); sun6i_a31_ar100_clk_probe()
212 if (IS_ERR(clk)) sun6i_a31_ar100_clk_probe()
213 return PTR_ERR(clk); sun6i_a31_ar100_clk_probe()
215 return of_clk_add_provider(np, of_clk_src_simple_get, clk); sun6i_a31_ar100_clk_probe()
219 { .compatible = "allwinner,sun6i-a31-ar100-clk" },
225 .name = "sun6i-a31-ar100-clk",
|
| H A D | clk-a10-hosc.c | 17 #include <linux/clk-provider.h>
28 struct clk *clk; sun4i_osc_clk_setup() local
53 clk = clk_register_composite(NULL, clk_name, sun4i_osc_clk_setup()
60 if (IS_ERR(clk)) sun4i_osc_clk_setup()
63 of_clk_add_provider(node, of_clk_src_simple_get, clk); sun4i_osc_clk_setup()
64 clk_register_clkdev(clk, clk_name, NULL); sun4i_osc_clk_setup()
73 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
|
| /linux-4.1.27/drivers/clk/mxs/ |
| H A D | clk.h | 15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
26 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
29 struct clk *mxs_clk_ref(const char *name, const char *parent_name,
32 struct clk *mxs_clk_div(const char *name, const char *parent_name,
35 struct clk *mxs_clk_frac(const char *name, const char *parent_name,
38 static inline struct clk *mxs_clk_fixed(const char *name, int rate) mxs_clk_fixed()
43 static inline struct clk *mxs_clk_gate(const char *name, mxs_clk_gate()
51 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, mxs_clk_mux()
59 static inline struct clk *mxs_clk_fixed_factor(const char *name, mxs_clk_fixed_factor()
|
| /linux-4.1.27/drivers/clk/at91/ |
| H A D | clk-slow.c | 2 * drivers/clk/at91/clk-slow.c
13 #include <linux/clk-provider.h>
15 #include <linux/clk/at91_pmc.h>
73 static struct clk *slow_clk;
121 static struct clk * __init at91_clk_register_slow_osc()
129 struct clk *clk = NULL; at91_clk_register_slow_osc() local
153 clk = clk_register(NULL, &osc->hw); at91_clk_register_slow_osc()
154 if (IS_ERR(clk)) at91_clk_register_slow_osc()
157 return clk; at91_clk_register_slow_osc()
163 struct clk *clk; of_at91sam9x5_clk_slow_osc_setup() local
174 clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup, of_at91sam9x5_clk_slow_osc_setup()
176 if (IS_ERR(clk)) of_at91sam9x5_clk_slow_osc_setup()
179 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_slow_osc_setup()
233 static struct clk * __init at91_clk_register_slow_rc_osc()
241 struct clk *clk = NULL; at91_clk_register_slow_rc_osc() local
263 clk = clk_register(NULL, &osc->hw); at91_clk_register_slow_rc_osc()
264 if (IS_ERR(clk)) at91_clk_register_slow_rc_osc()
267 return clk; at91_clk_register_slow_rc_osc()
273 struct clk *clk; of_at91sam9x5_clk_slow_rc_osc_setup() local
284 clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy, of_at91sam9x5_clk_slow_rc_osc_setup()
286 if (IS_ERR(clk)) of_at91sam9x5_clk_slow_rc_osc_setup()
289 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_slow_rc_osc_setup()
331 static struct clk * __init at91_clk_register_sam9x5_slow()
338 struct clk *clk = NULL; at91_clk_register_sam9x5_slow() local
358 clk = clk_register(NULL, &slowck->hw); at91_clk_register_sam9x5_slow()
359 if (IS_ERR(clk)) at91_clk_register_sam9x5_slow()
362 slow_clk = clk; at91_clk_register_sam9x5_slow()
364 return clk; at91_clk_register_sam9x5_slow()
370 struct clk *clk; of_at91sam9x5_clk_slow_setup() local
388 clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names, of_at91sam9x5_clk_slow_setup()
390 if (IS_ERR(clk)) of_at91sam9x5_clk_slow_setup()
393 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_slow_setup()
407 static struct clk * __init at91_clk_register_sam9260_slow()
414 struct clk *clk = NULL; at91_clk_register_sam9260_slow() local
436 clk = clk_register(NULL, &slowck->hw); at91_clk_register_sam9260_slow()
437 if (IS_ERR(clk)) at91_clk_register_sam9260_slow()
440 slow_clk = clk; at91_clk_register_sam9260_slow()
442 return clk; at91_clk_register_sam9260_slow()
448 struct clk *clk; of_at91sam9260_clk_slow_setup() local
466 clk = at91_clk_register_sam9260_slow(pmc, name, parent_names, of_at91sam9260_clk_slow_setup()
468 if (IS_ERR(clk)) of_at91sam9260_clk_slow_setup()
471 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9260_clk_slow_setup()
475 * FIXME: All slow clk users are not properly claiming it (get + prepare +
|
| H A D | clk-utmi.c | 11 #include <linux/clk-provider.h>
13 #include <linux/clk/at91_pmc.h>
84 /* UTMI clk is a fixed clk multiplier */ clk_utmi_recalc_rate()
95 static struct clk * __init at91_clk_register_utmi()
101 struct clk *clk = NULL; at91_clk_register_utmi() local
120 IRQF_TRIGGER_HIGH, "clk-utmi", utmi); at91_clk_register_utmi()
124 clk = clk_register(NULL, &utmi->hw); at91_clk_register_utmi()
125 if (IS_ERR(clk)) at91_clk_register_utmi()
128 return clk; at91_clk_register_utmi()
135 struct clk *clk; of_at91_clk_utmi_setup() local
147 clk = at91_clk_register_utmi(pmc, irq, name, parent_name); of_at91_clk_utmi_setup()
148 if (IS_ERR(clk)) of_at91_clk_utmi_setup()
151 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91_clk_utmi_setup()
|
| H A D | clk-usb.c | 11 #include <linux/clk-provider.h>
13 #include <linux/clk/at91_pmc.h>
66 struct clk *parent = NULL; at91sam9x5_clk_usb_determine_rate()
73 for (i = 0; i < __clk_get_num_parents(hw->clk); i++) { at91sam9x5_clk_usb_determine_rate()
76 parent = clk_get_parent_by_index(hw->clk, i); at91sam9x5_clk_usb_determine_rate()
199 static struct clk * __init at91sam9x5_clk_register_usb()
204 struct clk *clk = NULL; at91sam9x5_clk_register_usb() local
221 clk = clk_register(NULL, &usb->hw); at91sam9x5_clk_register_usb()
222 if (IS_ERR(clk)) at91sam9x5_clk_register_usb()
225 return clk; at91sam9x5_clk_register_usb()
228 static struct clk * __init at91sam9n12_clk_register_usb()
233 struct clk *clk = NULL; at91sam9n12_clk_register_usb() local
249 clk = clk_register(NULL, &usb->hw); at91sam9n12_clk_register_usb()
250 if (IS_ERR(clk)) at91sam9n12_clk_register_usb()
253 return clk; at91sam9n12_clk_register_usb()
276 struct clk *parent = __clk_get_parent(hw->clk); at91rm9200_clk_usb_round_rate()
343 static struct clk * __init at91rm9200_clk_register_usb()
348 struct clk *clk = NULL; at91rm9200_clk_register_usb() local
365 clk = clk_register(NULL, &usb->hw); at91rm9200_clk_register_usb()
366 if (IS_ERR(clk)) at91rm9200_clk_register_usb()
369 return clk; at91rm9200_clk_register_usb()
375 struct clk *clk; of_at91sam9x5_clk_usb_setup() local
393 clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents); of_at91sam9x5_clk_usb_setup()
394 if (IS_ERR(clk)) of_at91sam9x5_clk_usb_setup()
397 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_usb_setup()
403 struct clk *clk; of_at91sam9n12_clk_usb_setup() local
413 clk = at91sam9n12_clk_register_usb(pmc, name, parent_name); of_at91sam9n12_clk_usb_setup()
414 if (IS_ERR(clk)) of_at91sam9n12_clk_usb_setup()
417 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9n12_clk_usb_setup()
423 struct clk *clk; of_at91rm9200_clk_usb_setup() local
432 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4); of_at91rm9200_clk_usb_setup()
438 clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors); of_at91rm9200_clk_usb_setup()
439 if (IS_ERR(clk)) of_at91rm9200_clk_usb_setup()
442 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91rm9200_clk_usb_setup()
|
| H A D | sckc.c | 2 * drivers/clk/at91/sckc.c
13 #include <linux/clk-provider.h>
24 .compatible = "atmel,at91sam9x5-clk-slow-osc",
28 .compatible = "atmel,at91sam9x5-clk-slow-rc-osc",
32 .compatible = "atmel,at91sam9x5-clk-slow",
|
| /linux-4.1.27/arch/arm/include/asm/hardware/ |
| H A D | timer-sp.h | 1 struct clk;
4 const char *, struct clk *, int);
6 struct clk *, const char *);
|
| /linux-4.1.27/arch/mips/include/asm/mach-lantiq/ |
| H A D | lantiq.h | 13 #include <linux/clk.h>
40 extern int clk_activate(struct clk *clk);
41 extern void clk_deactivate(struct clk *clk);
42 extern struct clk *clk_get_cpu(void);
43 extern struct clk *clk_get_fpi(void);
44 extern struct clk *clk_get_io(void);
45 extern struct clk *clk_get_ppe(void);
|
| /linux-4.1.27/arch/sh/include/asm/ |
| H A D | clkdev.h | 8 * Helper for the clk API to assist looking up a struct clk.
29 #define __clk_put(clk)
30 #define __clk_get(clk) ({ 1; })
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh2/ |
| H A D | clock-sh7619.c | 26 static void master_clk_init(struct clk *clk) master_clk_init() argument
28 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; master_clk_init()
35 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
38 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
45 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
47 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; bus_clk_recalc()
|
| /linux-4.1.27/arch/arm/include/asm/ |
| H A D | clkdev.h | 10 * Helper for the clk API to assist looking up a struct clk.
21 #define __clk_get(clk) ({ 1; })
22 #define __clk_put(clk) do { } while (0)
|
| /linux-4.1.27/drivers/clk/samsung/ |
| H A D | clk.c | 17 #include "clk.h"
59 struct clk **clk_table; samsung_clk_init()
66 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); samsung_clk_init()
87 panic("could not register clk provider\n"); samsung_clk_of_add_provider()
92 void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, samsung_clk_add_lookup() argument
96 ctx->clk_data.clks[id] = clk; samsung_clk_add_lookup()
104 struct clk *clk; samsung_clk_register_alias() local
119 clk = ctx->clk_data.clks[list->id]; samsung_clk_register_alias()
120 if (!clk) { samsung_clk_register_alias()
126 ret = clk_register_clkdev(clk, list->alias, list->dev_name); samsung_clk_register_alias()
137 struct clk *clk; samsung_clk_register_fixed_rate() local
141 clk = clk_register_fixed_rate(NULL, list->name, samsung_clk_register_fixed_rate()
143 if (IS_ERR(clk)) { samsung_clk_register_fixed_rate()
149 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_fixed_rate()
155 ret = clk_register_clkdev(clk, list->name, NULL); samsung_clk_register_fixed_rate()
166 struct clk *clk; samsung_clk_register_fixed_factor() local
170 clk = clk_register_fixed_factor(NULL, list->name, samsung_clk_register_fixed_factor()
172 if (IS_ERR(clk)) { samsung_clk_register_fixed_factor()
178 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_fixed_factor()
187 struct clk *clk; samsung_clk_register_mux() local
191 clk = clk_register_mux(NULL, list->name, list->parent_names, samsung_clk_register_mux()
195 if (IS_ERR(clk)) { samsung_clk_register_mux()
201 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_mux()
205 ret = clk_register_clkdev(clk, list->alias, samsung_clk_register_mux()
219 struct clk *clk; samsung_clk_register_div() local
224 clk = clk_register_divider_table(NULL, list->name, samsung_clk_register_div()
230 clk = clk_register_divider(NULL, list->name, samsung_clk_register_div()
234 if (IS_ERR(clk)) { samsung_clk_register_div()
240 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_div()
244 ret = clk_register_clkdev(clk, list->alias, samsung_clk_register_div()
258 struct clk *clk; samsung_clk_register_gate() local
262 clk = clk_register_gate(NULL, list->name, list->parent_name, samsung_clk_register_gate()
265 if (IS_ERR(clk)) { samsung_clk_register_gate()
273 ret = clk_register_clkdev(clk, list->alias, samsung_clk_register_gate()
280 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_gate()
308 struct clk *clk; _get_rate() local
310 clk = __clk_lookup(clk_name); _get_rate()
311 if (!clk) { _get_rate()
316 return clk_get_rate(clk); _get_rate()
|
| /linux-4.1.27/drivers/usb/host/ |
| H A D | ehci-st.c | 15 #include <linux/clk.h>
35 struct clk *clks[USB_MAX_CLKS];
36 struct clk *clk48;
76 int clk, ret; st_ehci_platform_power_on() local
94 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { st_ehci_platform_power_on()
95 ret = clk_prepare_enable(priv->clks[clk]); st_ehci_platform_power_on()
113 while (--clk >= 0) st_ehci_platform_power_on()
114 clk_disable_unprepare(priv->clks[clk]); st_ehci_platform_power_on()
127 int clk; st_ehci_platform_power_off() local
137 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) st_ehci_platform_power_off()
138 if (priv->clks[clk]) st_ehci_platform_power_off()
139 clk_disable_unprepare(priv->clks[clk]); st_ehci_platform_power_off()
163 int err, irq, clk = 0; st_ehci_platform_probe() local
195 for (clk = 0; clk < USB_MAX_CLKS; clk++) { st_ehci_platform_probe()
196 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); st_ehci_platform_probe()
197 if (IS_ERR(priv->clks[clk])) { st_ehci_platform_probe()
198 err = PTR_ERR(priv->clks[clk]); st_ehci_platform_probe()
201 priv->clks[clk] = NULL; st_ehci_platform_probe()
210 dev_info(&dev->dev, "48MHz clk not found\n"); st_ehci_platform_probe()
255 while (--clk >= 0) st_ehci_platform_probe()
256 clk_put(priv->clks[clk]); st_ehci_platform_probe()
271 int clk; st_ehci_platform_remove() local
278 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) st_ehci_platform_remove()
279 clk_put(priv->clks[clk]); st_ehci_platform_remove()
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| H A D | ohci-st.c | 15 #include <linux/clk.h>
34 struct clk *clks[USB_MAX_CLKS];
35 struct clk *clk48;
52 int clk, ret; st_ohci_platform_power_on() local
70 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { st_ohci_platform_power_on()
71 ret = clk_prepare_enable(priv->clks[clk]); st_ohci_platform_power_on()
89 while (--clk >= 0) st_ohci_platform_power_on()
90 clk_disable_unprepare(priv->clks[clk]); st_ohci_platform_power_on()
104 int clk; st_ohci_platform_power_off() local
114 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) st_ohci_platform_power_off()
115 if (priv->clks[clk]) st_ohci_platform_power_off()
116 clk_disable_unprepare(priv->clks[clk]); st_ohci_platform_power_off()
139 int err, irq, clk = 0; st_ohci_platform_probe() local
172 for (clk = 0; clk < USB_MAX_CLKS; clk++) { st_ohci_platform_probe()
173 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); st_ohci_platform_probe()
174 if (IS_ERR(priv->clks[clk])) { st_ohci_platform_probe()
175 err = PTR_ERR(priv->clks[clk]); st_ohci_platform_probe()
178 priv->clks[clk] = NULL; st_ohci_platform_probe()
187 dev_info(&dev->dev, "48MHz clk not found\n"); st_ohci_platform_probe()
232 while (--clk >= 0) st_ohci_platform_probe()
233 clk_put(priv->clks[clk]); st_ohci_platform_probe()
248 int clk; st_ohci_platform_remove() local
256 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) st_ohci_platform_remove()
257 clk_put(priv->clks[clk]); st_ohci_platform_remove()
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| H A D | ohci-platform.c | 18 #include <linux/clk.h>
39 struct clk *clks[OHCI_MAX_CLKS];
51 int clk, ret, phy_num; ohci_platform_power_on() local
53 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) { ohci_platform_power_on()
54 ret = clk_prepare_enable(priv->clks[clk]); ohci_platform_power_on()
82 while (--clk >= 0) ohci_platform_power_on()
83 clk_disable_unprepare(priv->clks[clk]); ohci_platform_power_on()
92 int clk, phy_num; ohci_platform_power_off() local
101 for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--) ohci_platform_power_off()
102 if (priv->clks[clk]) ohci_platform_power_off()
103 clk_disable_unprepare(priv->clks[clk]); ohci_platform_power_off()
127 int err, irq, phy_num, clk = 0; ohci_platform_probe() local
209 for (clk = 0; clk < OHCI_MAX_CLKS; clk++) { ohci_platform_probe()
210 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); ohci_platform_probe()
211 if (IS_ERR(priv->clks[clk])) { ohci_platform_probe()
212 err = PTR_ERR(priv->clks[clk]); ohci_platform_probe()
215 priv->clks[clk] = NULL; ohci_platform_probe()
292 while (--clk >= 0) ohci_platform_probe()
293 clk_put(priv->clks[clk]); ohci_platform_probe()
308 int clk; ohci_platform_remove() local
318 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) ohci_platform_remove()
319 clk_put(priv->clks[clk]); ohci_platform_remove()
|
| /linux-4.1.27/arch/unicore32/kernel/ |
| H A D | clock.c | 20 #include <linux/clk.h>
30 struct clk { struct
36 static struct clk clk_ost_clk = {
41 static struct clk clk_mclk_clk = {
45 static struct clk clk_bclk32_clk = {
49 static struct clk clk_ddr_clk = {
53 static struct clk clk_vga_clk = {
60 struct clk *clk_get(struct device *dev, const char *id) clk_get()
62 struct clk *p, *clk = ERR_PTR(-ENOENT); clk_get() local
67 clk = p; clk_get()
73 return clk; clk_get()
77 void clk_put(struct clk *clk) clk_put() argument
82 int clk_enable(struct clk *clk) clk_enable() argument
88 void clk_disable(struct clk *clk) clk_disable() argument
93 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
95 return clk->rate; clk_get_rate()
136 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
138 if (clk == &clk_vga_clk) { clk_set_rate()
181 if (clk == &clk_mclk_clk) { clk_set_rate()
217 int clk_register(struct clk *clk) clk_register() argument
220 list_add(&clk->node, &clocks); clk_register()
222 printk(KERN_DEFAULT "PKUnity PM: %s %lu.%02luM\n", clk->name, clk_register()
223 (clk->rate)/1000000, (clk->rate)/10000 % 100); clk_register()
228 void clk_unregister(struct clk *clk) clk_unregister() argument
231 list_del(&clk->node); clk_unregister()
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| /linux-4.1.27/drivers/memory/ |
| H A D | atmel-sdramc.c | 20 #include <linux/clk.h>
57 struct clk *clk; atmel_ramc_probe() local
63 clk = devm_clk_get(&pdev->dev, "ddrck"); atmel_ramc_probe()
64 if (IS_ERR(clk)) atmel_ramc_probe()
65 return PTR_ERR(clk); atmel_ramc_probe()
66 clk_prepare_enable(clk); atmel_ramc_probe()
70 clk = devm_clk_get(&pdev->dev, "mpddr"); atmel_ramc_probe()
71 if (IS_ERR(clk)) { atmel_ramc_probe()
73 return PTR_ERR(clk); atmel_ramc_probe()
75 clk_prepare_enable(clk); atmel_ramc_probe()
|
| /linux-4.1.27/arch/arm/common/ |
| H A D | timer-sp.c | 21 #include <linux/clk.h>
36 static long __init sp804_get_clock_rate(struct clk *clk) sp804_get_clock_rate() argument
41 err = clk_prepare(clk); sp804_get_clock_rate()
44 clk_put(clk); sp804_get_clock_rate()
48 err = clk_enable(clk); sp804_get_clock_rate()
51 clk_unprepare(clk); sp804_get_clock_rate()
52 clk_put(clk); sp804_get_clock_rate()
56 rate = clk_get_rate(clk); sp804_get_clock_rate()
59 clk_disable(clk); sp804_get_clock_rate()
60 clk_unprepare(clk); sp804_get_clock_rate()
61 clk_put(clk); sp804_get_clock_rate()
76 struct clk *clk, __sp804_clocksource_and_sched_clock_init()
81 if (!clk) { __sp804_clocksource_and_sched_clock_init()
82 clk = clk_get_sys("sp804", name); __sp804_clocksource_and_sched_clock_init()
83 if (IS_ERR(clk)) { __sp804_clocksource_and_sched_clock_init()
85 (int)PTR_ERR(clk)); __sp804_clocksource_and_sched_clock_init()
90 rate = sp804_get_clock_rate(clk); __sp804_clocksource_and_sched_clock_init()
183 void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) __sp804_clockevents_init() argument
188 if (!clk) __sp804_clockevents_init()
189 clk = clk_get_sys("sp804", name); __sp804_clockevents_init()
190 if (IS_ERR(clk)) { __sp804_clockevents_init()
192 (int)PTR_ERR(clk)); __sp804_clockevents_init()
196 rate = sp804_get_clock_rate(clk); __sp804_clockevents_init()
218 struct clk *clk1, *clk2; sp804_of_init()
274 struct clk *clk; integrator_cp_of_init() local
279 clk = of_clk_get(np, 0); integrator_cp_of_init()
280 if (WARN_ON(IS_ERR(clk))) integrator_cp_of_init()
290 __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); integrator_cp_of_init()
296 __sp804_clockevents_init(base, irq, clk, name); integrator_cp_of_init()
74 __sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name, struct clk *clk, int use_sched_clock) __sp804_clocksource_and_sched_clock_init() argument
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| H A D | ctrl.c | 27 #include <subdev/clk.h>
39 struct nvkm_clk *clk = nvkm_clk(object); nvkm_control_mthd_pstate_info() local
49 if (clk) { nvkm_control_mthd_pstate_info()
50 args->v0.count = clk->state_nr; nvkm_control_mthd_pstate_info()
51 args->v0.ustate_ac = clk->ustate_ac; nvkm_control_mthd_pstate_info()
52 args->v0.ustate_dc = clk->ustate_dc; nvkm_control_mthd_pstate_info()
53 args->v0.pwrsrc = clk->pwrsrc; nvkm_control_mthd_pstate_info()
54 args->v0.pstate = clk->pstate; nvkm_control_mthd_pstate_info()
72 struct nvkm_clk *clk = nvkm_clk(object); nvkm_control_mthd_pstate_attr() local
85 if (!clk) nvkm_control_mthd_pstate_attr()
89 if (args->v0.state >= clk->state_nr) nvkm_control_mthd_pstate_attr()
93 domain = clk->domains; nvkm_control_mthd_pstate_attr()
105 list_for_each_entry(pstate, &clk->states, head) { nvkm_control_mthd_pstate_attr()
119 lo = max(clk->read(clk, domain->name), 0); nvkm_control_mthd_pstate_attr()
145 struct nvkm_clk *clk = nvkm_clk(object); nvkm_control_mthd_pstate_user() local
153 if (!clk) nvkm_control_mthd_pstate_user()
159 ret |= nvkm_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc); nvkm_control_mthd_pstate_user()
161 ret |= nvkm_clk_ustate(clk, args->v0.ustate, 0); nvkm_control_mthd_pstate_user()
162 ret |= nvkm_clk_ustate(clk, args->v0.ustate, 1); nvkm_control_mthd_pstate_user()
|
| /linux-4.1.27/drivers/rtc/ |
| H A D | rtc-coh901331.c | 12 #include <linux/clk.h>
45 struct clk *clk; member in struct:coh901331_port
57 clk_enable(rtap->clk); coh901331_interrupt()
68 clk_disable(rtap->clk); coh901331_interrupt()
80 clk_enable(rtap->clk); coh901331_read_time()
84 clk_disable(rtap->clk); coh901331_read_time()
87 clk_disable(rtap->clk); coh901331_read_time()
95 clk_enable(rtap->clk); coh901331_set_mmss()
97 clk_disable(rtap->clk); coh901331_set_mmss()
106 clk_enable(rtap->clk); coh901331_read_alarm()
110 clk_disable(rtap->clk); coh901331_read_alarm()
121 clk_enable(rtap->clk); coh901331_set_alarm()
124 clk_disable(rtap->clk); coh901331_set_alarm()
133 clk_enable(rtap->clk); coh901331_alarm_irq_enable()
138 clk_disable(rtap->clk); coh901331_alarm_irq_enable()
156 clk_unprepare(rtap->clk); coh901331_remove()
183 rtap->clk = devm_clk_get(&pdev->dev, NULL); coh901331_probe()
184 if (IS_ERR(rtap->clk)) { coh901331_probe()
185 ret = PTR_ERR(rtap->clk); coh901331_probe()
191 ret = clk_prepare_enable(rtap->clk); coh901331_probe()
196 clk_disable(rtap->clk); coh901331_probe()
209 clk_unprepare(rtap->clk); coh901331_probe()
226 clk_enable(rtap->clk); coh901331_suspend()
229 clk_disable(rtap->clk); coh901331_suspend()
231 clk_unprepare(rtap->clk); coh901331_suspend()
239 clk_prepare(rtap->clk); coh901331_resume()
243 clk_enable(rtap->clk); coh901331_resume()
245 clk_disable(rtap->clk); coh901331_resume()
257 clk_enable(rtap->clk); coh901331_shutdown()
259 clk_disable_unprepare(rtap->clk); coh901331_shutdown()
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| /linux-4.1.27/drivers/clk/shmobile/ |
| H A D | clk-r8a7778.c | 11 #include <linux/clk-provider.h>
13 #include <linux/clk/shmobile.h>
51 static struct clk * __init r8a7778_cpg_register_clock()
83 struct clk **clks; r8a7778_cpg_clocks_init()
113 struct clk *clk; r8a7778_cpg_clocks_init() local
118 clk = r8a7778_cpg_register_clock(np, cpg, name); r8a7778_cpg_clocks_init()
119 if (IS_ERR(clk)) r8a7778_cpg_clocks_init()
121 __func__, np->name, name, PTR_ERR(clk)); r8a7778_cpg_clocks_init()
123 cpg->data.clks[i] = clk; r8a7778_cpg_clocks_init()
|