| /linux-4.1.27/drivers/clk/ux500/ |
| D | u8540_clk.c | 20 struct clk *clk; in u8540_clk_init() local
24 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, in u8540_clk_init()
26 clk_register_clkdev(clk, "soc0_pll", NULL); in u8540_clk_init()
28 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, in u8540_clk_init()
30 clk_register_clkdev(clk, "soc1_pll", NULL); in u8540_clk_init()
32 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, in u8540_clk_init()
34 clk_register_clkdev(clk, "ddr_pll", NULL); in u8540_clk_init()
36 clk = clk_register_fixed_rate(NULL, "rtc32k", NULL, in u8540_clk_init()
39 clk_register_clkdev(clk, "clk32k", NULL); in u8540_clk_init()
40 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); in u8540_clk_init()
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| D | u8500_clk.c | 22 struct clk *clk; in u8500_clk_init() local
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, in u8500_clk_init()
27 clk_register_clkdev(clk, "soc0_pll", NULL); in u8500_clk_init()
29 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, in u8500_clk_init()
31 clk_register_clkdev(clk, "soc1_pll", NULL); in u8500_clk_init()
33 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, in u8500_clk_init()
35 clk_register_clkdev(clk, "ddr_pll", NULL); in u8500_clk_init()
39 clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", in u8500_clk_init()
42 clk_register_clkdev(clk, "clk32k", NULL); in u8500_clk_init()
43 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); in u8500_clk_init()
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| D | u8500_of_clk.c | 21 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
22 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
23 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
25 #define PRCC_SHOW(clk, base, bit) \ argument
26 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
27 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
28 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
30 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
32 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, in ux500_twocell_get()
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| D | clk-prcmu.c | 32 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_prepare() local
34 ret = prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
36 clk->is_prepared = 1; in clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
46 __clk_get_name(hw->clk)); in clk_prcmu_unprepare()
48 clk->is_prepared = 0; in clk_prcmu_unprepare()
53 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_is_prepared() local
54 return clk->is_prepared; in clk_prcmu_is_prepared()
59 struct clk_prcmu *clk = to_clk_prcmu(hw); in clk_prcmu_enable() local
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| D | clk-sysctrl.c | 39 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_prepare() local
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
42 clk->reg_bits[0]); in clk_sysctrl_prepare()
44 if (!ret && clk->enable_delay_us) in clk_sysctrl_prepare()
45 usleep_range(clk->enable_delay_us, clk->enable_delay_us); in clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", in clk_sysctrl_unprepare()
55 __func__, __clk_get_name(hw->clk)); in clk_sysctrl_unprepare()
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_recalc_rate() local
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| D | clk-prcc.c | 38 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_pclk_enable() local
40 writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); in clk_prcc_pclk_enable()
41 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) in clk_prcc_pclk_enable()
44 clk->is_enabled = 1; in clk_prcc_pclk_enable()
50 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_pclk_disable() local
52 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); in clk_prcc_pclk_disable()
53 clk->is_enabled = 0; in clk_prcc_pclk_disable()
58 struct clk_prcc *clk = to_clk_prcc(hw); in clk_prcc_kclk_enable() local
60 writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); in clk_prcc_kclk_enable()
61 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) in clk_prcc_kclk_enable()
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| D | abx500-clk.c | 26 struct clk *clk; in ab8500_reg_clks() local
44 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, in ab8500_reg_clks()
46 clk_register_clkdev(clk, "sysclk", "ab8500-usb.0"); in ab8500_reg_clks()
47 clk_register_clkdev(clk, "sysclk", "ab-iddet.0"); in ab8500_reg_clks()
48 clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0"); in ab8500_reg_clks()
49 clk_register_clkdev(clk, "sysclk", "shrm_bus"); in ab8500_reg_clks()
52 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk", in ab8500_reg_clks()
55 clk_register_clkdev(clk, "sysclk", "0-0070"); in ab8500_reg_clks()
58 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk", in ab8500_reg_clks()
61 clk_register_clkdev(clk, "sysclk", "cg1960_core.0"); in ab8500_reg_clks()
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| D | clk.h | 17 struct clk *clk_reg_prcc_pclk(const char *name,
23 struct clk *clk_reg_prcc_kclk(const char *name,
29 struct clk *clk_reg_prcmu_scalable(const char *name,
35 struct clk *clk_reg_prcmu_gate(const char *name,
40 struct clk *clk_reg_prcmu_scalable_rate(const char *name,
46 struct clk *clk_reg_prcmu_rate(const char *name,
51 struct clk *clk_reg_prcmu_opp_gate(const char *name,
56 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
62 struct clk *clk_reg_sysctrl_gate(struct device *dev,
71 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
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| /linux-4.1.27/include/linux/ |
| D | clk.h | 21 struct clk;
59 struct clk *clk; member
76 struct clk *clk; member
90 int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
97 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
107 long clk_get_accuracy(struct clk *clk);
117 int clk_set_phase(struct clk *clk, int degrees);
126 int clk_get_phase(struct clk *clk);
139 bool clk_is_match(const struct clk *p, const struct clk *q);
143 static inline long clk_get_accuracy(struct clk *clk) in clk_get_accuracy() argument
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| D | sh_clk.h | 12 struct clk;
23 void (*init)(struct clk *clk);
25 int (*enable)(struct clk *clk);
26 void (*disable)(struct clk *clk);
27 unsigned long (*recalc)(struct clk *clk);
28 int (*set_rate)(struct clk *clk, unsigned long rate);
29 int (*set_parent)(struct clk *clk, struct clk *parent);
30 long (*round_rate)(struct clk *clk, unsigned long rate);
37 struct clk { struct
39 struct clk *parent; argument
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| D | clk-provider.h | 234 struct clk *clk; member
260 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
263 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
301 struct clk *clk_register_gate(struct device *dev, const char *name,
305 void clk_unregister_gate(struct clk *clk);
375 struct clk *clk_register_divider(struct device *dev, const char *name,
379 struct clk *clk_register_divider_table(struct device *dev, const char *name,
384 void clk_unregister_divider(struct clk *clk);
428 struct clk *clk_register_mux(struct device *dev, const char *name,
433 struct clk *clk_register_mux_table(struct device *dev, const char *name,
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| D | clkdev.h | 17 struct clk;
24 struct clk *clk; member
31 .clk = c, \
34 struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
43 int clk_register_clkdev(struct clk *, const char *, const char *, ...);
44 int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
47 int __clk_get(struct clk *clk);
48 void __clk_put(struct clk *clk);
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| /linux-4.1.27/arch/arm/mach-omap1/ |
| D | clock.h | 22 struct clk;
35 .clk = ck, \
48 #define __clk_get_name(clk) (clk->name) argument
49 #define __clk_get_parent(clk) (clk->parent) argument
50 #define __clk_get_rate(clk) (clk->rate) argument
71 int (*enable)(struct clk *);
72 void (*disable)(struct clk *);
73 void (*find_idlest)(struct clk *, void __iomem **,
75 void (*find_companion)(struct clk *, void __iomem **,
77 void (*allow_idle)(struct clk *);
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| D | clock.c | 34 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
44 unsigned long omap1_uart_recalc(struct clk *clk) in omap1_uart_recalc() argument
46 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
47 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
50 unsigned long omap1_sossi_recalc(struct clk *clk) in omap1_sossi_recalc() argument
57 return clk->parent->rate / div; in omap1_sossi_recalc()
60 static void omap1_clk_allow_idle(struct clk *clk) in omap1_clk_allow_idle() argument
62 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_allow_idle()
64 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle()
71 static void omap1_clk_deny_idle(struct clk *clk) in omap1_clk_deny_idle() argument
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| D | clock_data.c | 78 static struct clk ck_ref = {
84 static struct clk ck_dpll1 = {
95 .clk = {
108 static struct clk sossi_ck = {
111 .parent = &ck_dpll1out.clk,
119 static struct clk arm_ck = {
130 .clk = {
149 static struct clk arm_gpio_ck = {
160 .clk = {
173 .clk = {
[all …]
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| /linux-4.1.27/arch/c6x/platforms/ |
| D | pll.c | 31 static void __clk_enable(struct clk *clk) in __clk_enable() argument
33 if (clk->parent) in __clk_enable()
34 __clk_enable(clk->parent); in __clk_enable()
35 clk->usecount++; in __clk_enable()
38 static void __clk_disable(struct clk *clk) in __clk_disable() argument
40 if (WARN_ON(clk->usecount == 0)) in __clk_disable()
42 --clk->usecount; in __clk_disable()
44 if (clk->parent) in __clk_disable()
45 __clk_disable(clk->parent); in __clk_disable()
48 int clk_enable(struct clk *clk) in clk_enable() argument
[all …]
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| /linux-4.1.27/drivers/clk/ |
| D | clk.c | 40 static long clk_core_get_accuracy(struct clk_core *clk);
41 static unsigned long clk_core_get_rate(struct clk_core *clk);
42 static int clk_core_get_phase(struct clk_core *clk);
43 static bool clk_core_is_prepared(struct clk_core *clk);
44 static bool clk_core_is_enabled(struct clk_core *clk);
83 struct clk { struct
297 static int clk_debug_create_one(struct clk_core *clk, struct dentry *pdentry) in clk_debug_create_one() argument
302 if (!clk || !pdentry) { in clk_debug_create_one()
307 d = debugfs_create_dir(clk->name, pdentry); in clk_debug_create_one()
311 clk->dentry = d; in clk_debug_create_one()
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| D | clkdev.c | 31 static struct clk *__of_clk_get(struct device_node *np, int index, in __of_clk_get()
35 struct clk *clk; in __of_clk_get() local
46 clk = __of_clk_get_from_provider(&clkspec, dev_id, con_id); in __of_clk_get()
49 return clk; in __of_clk_get()
52 struct clk *of_clk_get(struct device_node *np, int index) in of_clk_get()
58 static struct clk *__of_clk_get_by_name(struct device_node *np, in __of_clk_get_by_name()
62 struct clk *clk = ERR_PTR(-ENOENT); in __of_clk_get_by_name() local
75 clk = __of_clk_get(np, index, dev_id, name); in __of_clk_get_by_name()
76 if (!IS_ERR(clk)) { in __of_clk_get_by_name()
79 if (PTR_ERR(clk) != -EPROBE_DEFER) in __of_clk_get_by_name()
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| D | Makefile | 2 obj-$(CONFIG_HAVE_CLK) += clk-devres.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
6 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
7 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
8 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
9 obj-$(CONFIG_COMMON_CLK) += clk-mux.o
10 obj-$(CONFIG_COMMON_CLK) += clk-composite.o
11 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
12 obj-$(CONFIG_COMMON_CLK) += clk-gpio-gate.o
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| D | clk-ls1x.c | 51 static struct clk *__init clk_register_pll(struct device *dev, in clk_register_pll()
57 struct clk *clk; in clk_register_pll() local
75 clk = clk_register(dev, hw); in clk_register_pll()
77 if (IS_ERR(clk)) in clk_register_pll()
80 return clk; in clk_register_pll()
89 struct clk *clk; in ls1x_clk_init() local
91 clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT, in ls1x_clk_init()
93 clk_register_clkdev(clk, "osc_33m_clk", NULL); in ls1x_clk_init()
96 clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0); in ls1x_clk_init()
97 clk_register_clkdev(clk, "pll_clk", NULL); in ls1x_clk_init()
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| D | clk-efm32gg.c | 19 static struct clk *clk[37]; variable
21 .clks = clk,
22 .clk_num = ARRAY_SIZE(clk),
30 for (i = 0; i < ARRAY_SIZE(clk); ++i) in efm32gg_cmu_init()
31 clk[i] = ERR_PTR(-ENOENT); in efm32gg_cmu_init()
39 clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL, in efm32gg_cmu_init()
42 clk[clk_HFPERCLKUSART0] = clk_register_gate(NULL, "HFPERCLK.USART0", in efm32gg_cmu_init()
44 clk[clk_HFPERCLKUSART1] = clk_register_gate(NULL, "HFPERCLK.USART1", in efm32gg_cmu_init()
46 clk[clk_HFPERCLKUSART2] = clk_register_gate(NULL, "HFPERCLK.USART2", in efm32gg_cmu_init()
48 clk[clk_HFPERCLKUART0] = clk_register_gate(NULL, "HFPERCLK.UART0", in efm32gg_cmu_init()
[all …]
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| D | clk-gpio-gate.c | 35 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_gate_enable() local
37 gpiod_set_value(clk->gpiod, 1); in clk_gpio_gate_enable()
44 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_gate_disable() local
46 gpiod_set_value(clk->gpiod, 0); in clk_gpio_gate_disable()
51 struct clk_gpio *clk = to_clk_gpio(hw); in clk_gpio_gate_is_enabled() local
53 return gpiod_get_value(clk->gpiod); in clk_gpio_gate_is_enabled()
72 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, in clk_register_gpio_gate()
77 struct clk *clk = ERR_PTR(-EINVAL); in clk_register_gpio_gate() local
105 clk = ERR_PTR(-ENOMEM); in clk_register_gpio_gate()
118 clk = clk_register(dev, &clk_gpio->hw); in clk_register_gpio_gate()
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| D | clk-nspire.c | 45 static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) in nspire_clkinfo_cx() argument
48 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
52 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN); in nspire_clkinfo_cx()
53 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); in nspire_clkinfo_cx()
56 static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) in nspire_clkinfo_classic() argument
59 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
63 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2; in nspire_clkinfo_classic()
64 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); in nspire_clkinfo_classic()
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| D | clk-bcm2835.c | 32 struct clk *clk; in bcm2835_init_clocks() local
35 clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, in bcm2835_init_clocks()
37 if (IS_ERR(clk)) in bcm2835_init_clocks()
40 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, in bcm2835_init_clocks()
42 if (IS_ERR(clk)) in bcm2835_init_clocks()
45 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT, in bcm2835_init_clocks()
47 if (IS_ERR(clk)) in bcm2835_init_clocks()
49 ret = clk_register_clkdev(clk, NULL, "20201000.uart"); in bcm2835_init_clocks()
53 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT, in bcm2835_init_clocks()
55 if (IS_ERR(clk)) in bcm2835_init_clocks()
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| D | clk.h | 15 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
20 struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
22 void __clk_free_clk(struct clk *clk);
25 static inline struct clk *
28 return (struct clk *)hw; in __clk_create_clk()
30 static inline void __clk_free_clk(struct clk *clk) { } in __clk_free_clk() argument
31 static struct clk_hw *__clk_get_hw(struct clk *clk) in __clk_get_hw() argument
33 return (struct clk_hw *)clk; in __clk_get_hw()
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| D | clk-devres.c | 14 clk_put(*(struct clk **)res); in devm_clk_release()
17 struct clk *devm_clk_get(struct device *dev, const char *id) in devm_clk_get()
19 struct clk **ptr, *clk; in devm_clk_get() local
25 clk = clk_get(dev, id); in devm_clk_get()
26 if (!IS_ERR(clk)) { in devm_clk_get()
27 *ptr = clk; in devm_clk_get()
33 return clk; in devm_clk_get()
39 struct clk **c = res; in devm_clk_match()
47 void devm_clk_put(struct device *dev, struct clk *clk) in devm_clk_put() argument
51 ret = devres_release(dev, devm_clk_release, devm_clk_match, clk); in devm_clk_put()
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| D | clk-conf.c | 21 struct clk *clk, *pclk; in __set_clk_parents() local
56 clk = of_clk_get_from_provider(&clkspec); in __set_clk_parents()
57 if (IS_ERR(clk)) { in __set_clk_parents()
60 rc = PTR_ERR(clk); in __set_clk_parents()
64 rc = clk_set_parent(clk, pclk); in __set_clk_parents()
67 __clk_get_name(clk), __clk_get_name(pclk), rc); in __set_clk_parents()
68 clk_put(clk); in __set_clk_parents()
83 struct clk *clk; in __set_clk_rates() local
100 clk = of_clk_get_from_provider(&clkspec); in __set_clk_rates()
101 if (IS_ERR(clk)) { in __set_clk_rates()
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| D | clk-moxart.c | 21 struct clk *clk, *ref_clk; in moxart_of_pll_clk_init() local
44 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); in moxart_of_pll_clk_init()
45 if (IS_ERR(clk)) { in moxart_of_pll_clk_init()
50 clk_register_clkdev(clk, NULL, name); in moxart_of_pll_clk_init()
51 of_clk_add_provider(node, of_clk_src_simple_get, clk); in moxart_of_pll_clk_init()
59 struct clk *clk, *pll_clk; in moxart_of_apb_clk_init() local
87 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div); in moxart_of_apb_clk_init()
88 if (IS_ERR(clk)) { in moxart_of_apb_clk_init()
93 clk_register_clkdev(clk, NULL, name); in moxart_of_apb_clk_init()
94 of_clk_add_provider(node, of_clk_src_simple_get, clk); in moxart_of_apb_clk_init()
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| D | clk-fixed-factor.c | 44 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { in clk_factor_round_rate()
48 *prate = __clk_round_rate(__clk_get_parent(hw->clk), in clk_factor_round_rate()
68 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, in clk_register_fixed_factor()
74 struct clk *clk; in clk_register_fixed_factor() local
93 clk = clk_register(dev, &fix->hw); in clk_register_fixed_factor()
95 if (IS_ERR(clk)) in clk_register_fixed_factor()
98 return clk; in clk_register_fixed_factor()
108 struct clk *clk; in of_fixed_factor_clk_setup() local
128 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, in of_fixed_factor_clk_setup()
130 if (!IS_ERR(clk)) in of_fixed_factor_clk_setup()
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| D | clk-fixed-rate.c | 59 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, in clk_register_fixed_rate_with_accuracy()
64 struct clk *clk; in clk_register_fixed_rate_with_accuracy() local
86 clk = clk_register(dev, &fixed->hw); in clk_register_fixed_rate_with_accuracy()
87 if (IS_ERR(clk)) in clk_register_fixed_rate_with_accuracy()
90 return clk; in clk_register_fixed_rate_with_accuracy()
102 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, in clk_register_fixed_rate()
117 struct clk *clk; in of_fixed_clk_setup() local
129 clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL, in of_fixed_clk_setup()
132 if (!IS_ERR(clk)) in of_fixed_clk_setup()
133 of_clk_add_provider(node, of_clk_src_simple_get, clk); in of_fixed_clk_setup()
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| /linux-4.1.27/arch/arm/mach-imx/ |
| D | clk-imx27.c | 42 static struct clk *clk[IMX27_CLK_MAX]; variable
49 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
50 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
51 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
52 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
53 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx27_clocks_init()
54 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx27_clocks_init()
55 …clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY… in _mx27_clocks_init()
56 …clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_… in _mx27_clocks_init()
57 clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
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| D | clk-imx6q.c | 85 static struct clk *clk[IMX6QDL_CLK_END]; variable
131 clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6q_clocks_init()
132 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in imx6q_clocks_init()
133 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); in imx6q_clocks_init()
134 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in imx6q_clocks_init()
136 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6q_clocks_init()
137 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); in imx6q_clocks_init()
151 …clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
152 …clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
153 …clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_s… in imx6q_clocks_init()
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| D | clk-imx51-imx53.c | 131 static struct clk *clk[IMX5_CLK_END]; variable
138 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx5_clocks_common_init()
139 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in mx5_clocks_common_init()
140 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in mx5_clocks_common_init()
141 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); in mx5_clocks_common_init()
142 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); in mx5_clocks_common_init()
144 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, in mx5_clocks_common_init()
146 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, in mx5_clocks_common_init()
148 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, in mx5_clocks_common_init()
150 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); in mx5_clocks_common_init()
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| D | clk-vf610.c | 115 static struct clk *clk[VF610_CLK_END]; variable
123 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
126 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
129 if (IS_ERR(clk)) in vf610_get_fixed_clock()
130 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
131 return clk; in vf610_get_fixed_clock()
139 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
140 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
141 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); in vf610_clocks_init()
142 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); in vf610_clocks_init()
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| D | clk-imx21.c | 39 static struct clk *clk[IMX21_CLK_MAX]; variable
46 clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx21_clocks_init()
47 clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); in _mx21_clocks_init()
48 clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); in _mx21_clocks_init()
49 clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); in _mx21_clocks_init()
50 clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx21_clocks_init()
52 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in _mx21_clocks_init()
53 clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx21_clocks_init()
54 clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); in _mx21_clocks_init()
55 clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx21_clocks_init()
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| D | clk-imx31.c | 48 static struct clk *clk[clk_max]; variable
56 clk[dummy] = imx_clk_fixed("dummy", 0); in mx31_clocks_init()
57 clk[ckih] = imx_clk_fixed("ckih", fref); in mx31_clocks_init()
58 clk[ckil] = imx_clk_fixed("ckil", 32768); in mx31_clocks_init()
59 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); in mx31_clocks_init()
60 clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL); in mx31_clocks_init()
61 clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL); in mx31_clocks_init()
62 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in mx31_clocks_init()
63 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in mx31_clocks_init()
64 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in mx31_clocks_init()
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| D | clk-imx35.c | 70 static struct clk *clk[clk_max]; variable
91 clk[ckih] = imx_clk_fixed("ckih", 24000000); in mx35_clocks_init()
92 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); in mx35_clocks_init()
93 clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); in mx35_clocks_init()
95 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in mx35_clocks_init()
98 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in mx35_clocks_init()
100 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in mx35_clocks_init()
102 if (clk_get_rate(clk[arm]) > 400000000) in mx35_clocks_init()
113 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in mx35_clocks_init()
115 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); in mx35_clocks_init()
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| D | clk-imx25.c | 89 static struct clk *clk[clk_max]; variable
96 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
97 clk[osc] = imx_clk_fixed("osc", osc_rate); in __mx25_clocks_init()
98 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
99 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
100 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
101 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
102 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
103 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
104 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
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| D | clk-imx1.c | 35 static struct clk *clk[IMX1_CLK_MAX]; variable
47 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx1_clocks_init()
48 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); in _mx1_clocks_init()
49 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); in _mx1_clocks_init()
50 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); in _mx1_clocks_init()
51 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); in _mx1_clocks_init()
52 …clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)… in _mx1_clocks_init()
53 clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); in _mx1_clocks_init()
54 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in _mx1_clocks_init()
55 clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); in _mx1_clocks_init()
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| D | clk.h | 9 void imx_check_clocks(struct clk *clks[], unsigned int count);
13 struct clk *imx_clk_pllv1(const char *name, const char *parent,
16 struct clk *imx_clk_pllv2(const char *name, const char *parent,
28 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
31 struct clk *clk_register_gate2(struct device *dev, const char *name,
37 struct clk * imx_obtain_fixed_clock(
40 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
43 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, in imx_clk_gate2()
50 static inline struct clk *imx_clk_gate2_shared(const char *name, in imx_clk_gate2_shared()
58 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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| D | clk.c | 10 void __init imx_check_clocks(struct clk *clks[], unsigned int count) in imx_check_clocks()
20 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) in imx_obtain_fixed_clock_from_dt()
23 struct clk *clk = ERR_PTR(-ENODEV); in imx_obtain_fixed_clock_from_dt() local
34 clk = of_clk_get_from_provider(&phandle); in imx_obtain_fixed_clock_from_dt()
37 return clk; in imx_obtain_fixed_clock_from_dt()
40 struct clk * __init imx_obtain_fixed_clock( in imx_obtain_fixed_clock()
43 struct clk *clk; in imx_obtain_fixed_clock() local
45 clk = imx_obtain_fixed_clock_from_dt(name); in imx_obtain_fixed_clock()
46 if (IS_ERR(clk)) in imx_obtain_fixed_clock()
47 clk = imx_clk_fixed(name, rate); in imx_obtain_fixed_clock()
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| D | clk-cpu.c | 18 struct clk *div;
19 struct clk *mux;
20 struct clk *pll;
21 struct clk *step;
77 struct clk *imx_clk_cpu(const char *name, const char *parent_name, in imx_clk_cpu()
78 struct clk *div, struct clk *mux, struct clk *pll, in imx_clk_cpu()
79 struct clk *step) in imx_clk_cpu()
82 struct clk *clk; in imx_clk_cpu() local
102 clk = clk_register(NULL, &cpu->hw); in imx_clk_cpu()
103 if (IS_ERR(clk)) in imx_clk_cpu()
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| D | Makefile | 3 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
4 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
6 obj-$(CONFIG_SOC_IMX25) += clk-imx25.o cpu-imx25.o mach-imx25.o
9 obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
11 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
12 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
15 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)
17 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o \
19 clk-fixup-div.o clk-fixup-mux.o \
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| /linux-4.1.27/arch/arm/mach-davinci/ |
| D | clock.c | 34 static void __clk_enable(struct clk *clk) in __clk_enable() argument
36 if (clk->parent) in __clk_enable()
37 __clk_enable(clk->parent); in __clk_enable()
38 if (clk->usecount++ == 0) { in __clk_enable()
39 if (clk->flags & CLK_PSC) in __clk_enable()
40 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, in __clk_enable()
41 true, clk->flags); in __clk_enable()
42 else if (clk->clk_enable) in __clk_enable()
43 clk->clk_enable(clk); in __clk_enable()
47 static void __clk_disable(struct clk *clk) in __clk_disable() argument
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| D | clock.h | 87 struct clk { struct
98 struct clk *parent; argument
103 unsigned long (*recalc) (struct clk *); argument
104 int (*set_rate) (struct clk *clk, unsigned long rate); argument
105 int (*round_rate) (struct clk *clk, unsigned long rate); argument
106 int (*reset) (struct clk *clk, bool reset); argument
107 void (*clk_enable) (struct clk *clk); argument
108 void (*clk_disable) (struct clk *clk); argument
124 .clk = ck, \
130 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
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| D | da850.c | 49 static int da850_set_armrate(struct clk *clk, unsigned long rate);
50 static int da850_round_armrate(struct clk *clk, unsigned long rate);
51 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
59 static struct clk ref_clk = {
65 static struct clk pll0_clk = {
73 static struct clk pll0_aux_clk = {
79 static struct clk pll0_sysclk1 = {
86 static struct clk pll0_sysclk2 = {
93 static struct clk pll0_sysclk3 = {
102 static struct clk pll0_sysclk4 = {
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| /linux-4.1.27/drivers/media/v4l2-core/ |
| D | v4l2-clk.c | 29 struct v4l2_clk *clk; in v4l2_clk_find() local
31 list_for_each_entry(clk, &clk_list, list) in v4l2_clk_find()
32 if (!strcmp(dev_id, clk->dev_id)) in v4l2_clk_find()
33 return clk; in v4l2_clk_find()
40 struct v4l2_clk *clk; in v4l2_clk_get() local
41 struct clk *ccf_clk = clk_get(dev, id); in v4l2_clk_get()
47 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in v4l2_clk_get()
48 if (!clk) { in v4l2_clk_get()
52 clk->clk = ccf_clk; in v4l2_clk_get()
54 return clk; in v4l2_clk_get()
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| /linux-4.1.27/drivers/sh/clk/ |
| D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
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| D | core.c | 39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), in clk_rate_mult_range_round()
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| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-mmp2.c | 80 struct clk *clk; in mmp2_clk_init() local
81 struct clk *vctcxo; in mmp2_clk_init()
104 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); in mmp2_clk_init()
105 clk_register_clkdev(clk, "clk32", NULL); in mmp2_clk_init()
111 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, in mmp2_clk_init()
113 clk_register_clkdev(clk, "pll1", NULL); in mmp2_clk_init()
115 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT, in mmp2_clk_init()
117 clk_register_clkdev(clk, "usb_pll", NULL); in mmp2_clk_init()
119 clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, in mmp2_clk_init()
121 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
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| D | clk-pxa168.c | 71 struct clk *clk; in pxa168_clk_init() local
72 struct clk *uart_pll; in pxa168_clk_init()
95 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); in pxa168_clk_init()
96 clk_register_clkdev(clk, "clk32", NULL); in pxa168_clk_init()
98 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, in pxa168_clk_init()
100 clk_register_clkdev(clk, "vctcxo", NULL); in pxa168_clk_init()
102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, in pxa168_clk_init()
104 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
106 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
108 clk_register_clkdev(clk, "pll1_2", NULL); in pxa168_clk_init()
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| D | clk-pxa910.c | 69 struct clk *clk; in pxa910_clk_init() local
70 struct clk *uart_pll; in pxa910_clk_init()
100 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); in pxa910_clk_init()
101 clk_register_clkdev(clk, "clk32", NULL); in pxa910_clk_init()
103 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, in pxa910_clk_init()
105 clk_register_clkdev(clk, "vctcxo", NULL); in pxa910_clk_init()
107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, in pxa910_clk_init()
109 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
111 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
113 clk_register_clkdev(clk, "pll1_2", NULL); in pxa910_clk_init()
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| D | clk.c | 13 static struct clk **clk_table; in mmp_clk_init()
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in mmp_clk_init()
31 struct clk *clk; in mmp_register_fixed_rate_clks() local
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
38 if (IS_ERR(clk)) { in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
52 struct clk *clk; in mmp_register_fixed_factor_clks() local
56 clk = clk_register_fixed_factor(NULL, clks[i].name, in mmp_register_fixed_factor_clks()
60 if (IS_ERR(clk)) { in mmp_register_fixed_factor_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
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| D | Makefile | 5 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
9 obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
10 obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
12 obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
13 obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
14 obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
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| /linux-4.1.27/arch/mips/lantiq/ |
| D | clk.c | 29 static struct clk cpu_clk_generic[4];
40 struct clk *clk_get_cpu(void) in clk_get_cpu()
45 struct clk *clk_get_fpi(void) in clk_get_fpi()
51 struct clk *clk_get_io(void) in clk_get_io()
56 struct clk *clk_get_ppe(void) in clk_get_ppe()
62 static inline int clk_good(struct clk *clk) in clk_good() argument
64 return clk && !IS_ERR(clk); in clk_good()
67 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
69 if (unlikely(!clk_good(clk))) in clk_get_rate()
72 if (clk->rate != 0) in clk_get_rate()
[all …]
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| D | clk.h | 55 struct clk { struct
62 int (*enable) (struct clk *clk); argument
63 void (*disable) (struct clk *clk); argument
64 int (*activate) (struct clk *clk); argument
65 void (*deactivate) (struct clk *clk); argument
66 void (*reboot) (struct clk *clk); argument
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| /linux-4.1.27/drivers/clk/spear/ |
| D | spear3xx_clock.c | 143 struct clk *clk; in spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); in spear300_clk_init()
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
[all …]
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| D | spear1310_clock.c | 388 struct clk *clk, *clk1; in spear1310_clk_init() local
390 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
392 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
394 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
396 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1310_clk_init()
398 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
400 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1310_clk_init()
402 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, in spear1310_clk_init()
404 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1310_clk_init()
406 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, in spear1310_clk_init()
[all …]
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| D | spear6xx_clock.c | 119 struct clk *clk, *clk1; in spear6xx_clk_init() local
121 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, in spear6xx_clk_init()
123 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
125 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, in spear6xx_clk_init()
127 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
130 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
132 clk_register_clkdev(clk, NULL, "rtc-spear"); in spear6xx_clk_init()
135 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, in spear6xx_clk_init()
137 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
139 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", in spear6xx_clk_init()
[all …]
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| D | spear1340_clock.c | 445 struct clk *clk, *clk1; in spear1340_clk_init() local
447 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
449 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1340_clk_init()
451 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
453 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1340_clk_init()
455 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
457 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1340_clk_init()
459 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, in spear1340_clk_init()
461 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1340_clk_init()
463 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, in spear1340_clk_init()
[all …]
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| /linux-4.1.27/arch/avr32/mach-at32ap/ |
| D | clock.c | 31 void at32_clk_register(struct clk *clk) in at32_clk_register() argument
35 list_add_tail(&clk->list, &at32_clock_list); in at32_clk_register()
39 static struct clk *__clk_get(struct device *dev, const char *id) in __clk_get()
41 struct clk *clk; in __clk_get() local
43 list_for_each_entry(clk, &at32_clock_list, list) { in __clk_get()
44 if (clk->dev == dev && strcmp(id, clk->name) == 0) { in __clk_get()
45 return clk; in __clk_get()
52 struct clk *clk_get(struct device *dev, const char *id) in clk_get()
54 struct clk *clk; in clk_get() local
57 clk = __clk_get(dev, id); in clk_get()
[all …]
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| D | clock.h | 18 void at32_clk_register(struct clk *clk);
20 struct clk { struct
24 struct clk *parent; /* Parent clock, if any */ argument
25 void (*mode)(struct clk *clk, int enabled); argument
26 unsigned long (*get_rate)(struct clk *clk); argument
27 long (*set_rate)(struct clk *clk, unsigned long rate, argument
29 int (*set_parent)(struct clk *clk, struct clk *parent); argument
34 unsigned long pba_clk_get_rate(struct clk *clk); argument
35 void pba_clk_mode(struct clk *clk, int enabled);
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| D | at32ap700x.c | 96 static struct clk devname##_##_name = { \
107 static struct clk osc0;
108 static struct clk osc1;
110 static unsigned long osc_get_rate(struct clk *clk) in osc_get_rate() argument
112 return at32_board_osc_rates[clk->index]; in osc_get_rate()
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control) in pll_get_rate() argument
122 rate = clk->parent->get_rate(clk->parent); in pll_get_rate()
129 static long pll_set_rate(struct clk *clk, unsigned long rate, in pll_set_rate() argument
150 base = clk->parent->get_rate(clk->parent); in pll_set_rate()
186 if (clk->parent == &osc1) in pll_set_rate()
[all …]
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| /linux-4.1.27/arch/mips/jz4740/ |
| D | clock.c | 105 struct clk clk; member
110 struct clk clk; member
116 struct clk clk; member
159 static int jz_clk_enable_gating(struct clk *clk) in jz_clk_enable_gating() argument
161 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) in jz_clk_enable_gating()
164 jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); in jz_clk_enable_gating()
168 static int jz_clk_disable_gating(struct clk *clk) in jz_clk_disable_gating() argument
170 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) in jz_clk_disable_gating()
173 jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); in jz_clk_disable_gating()
177 static int jz_clk_is_enabled_gating(struct clk *clk) in jz_clk_is_enabled_gating() argument
[all …]
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| D | clock.h | 31 struct clk;
34 unsigned long (*get_rate)(struct clk *clk);
35 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
36 int (*set_rate)(struct clk *clk, unsigned long rate);
37 int (*enable)(struct clk *clk);
38 int (*disable)(struct clk *clk);
39 int (*is_enabled)(struct clk *clk);
41 int (*set_parent)(struct clk *clk, struct clk *parent);
45 struct clk { struct
47 struct clk *parent; argument
[all …]
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| D | clock-debugfs.c | 31 struct clk *clk = data; in jz4740_clock_debugfs_show_enabled() local
32 *value = clk_is_enabled(clk); in jz4740_clock_debugfs_show_enabled()
39 struct clk *clk = data; in jz4740_clock_debugfs_set_enabled() local
42 return clk_enable(clk); in jz4740_clock_debugfs_set_enabled()
44 clk_disable(clk); in jz4740_clock_debugfs_set_enabled()
56 struct clk *clk = data; in jz4740_clock_debugfs_show_rate() local
57 *value = clk_get_rate(clk); in jz4740_clock_debugfs_show_rate()
67 void jz4740_clock_debugfs_add_clk(struct clk *clk) in jz4740_clock_debugfs_add_clk() argument
72 clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs); in jz4740_clock_debugfs_add_clk()
73 debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk, in jz4740_clock_debugfs_add_clk()
[all …]
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| /linux-4.1.27/arch/m68k/coldfire/ |
| D | clk.c | 30 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
32 clk->enabled = 1; in __clk_init_enabled()
33 clk->clk_ops->enable(clk); in __clk_init_enabled()
36 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
38 clk->enabled = 0; in __clk_init_disabled()
39 clk->clk_ops->disable(clk); in __clk_init_disabled()
42 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
44 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
47 static void __clk_disable0(struct clk *clk) in __clk_disable0() argument
49 __raw_writeb(clk->slot, MCFPM_PPMSR0); in __clk_disable0()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | base.c | 40 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
43 struct nvkm_bios *bios = nvkm_bios(clk); in nvkm_clk_adjust()
78 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) in nvkm_cstate_prog() argument
80 struct nvkm_therm *ptherm = nvkm_therm(clk); in nvkm_cstate_prog()
81 struct nvkm_volt *volt = nvkm_volt(clk); in nvkm_cstate_prog()
94 nv_error(clk, "failed to raise fan speed: %d\n", ret); in nvkm_cstate_prog()
102 nv_error(clk, "failed to raise voltage: %d\n", ret); in nvkm_cstate_prog()
107 ret = clk->calc(clk, cstate); in nvkm_cstate_prog()
109 ret = clk->prog(clk); in nvkm_cstate_prog()
110 clk->tidy(clk); in nvkm_cstate_prog()
[all …]
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| D | mcp77.c | 42 read_div(struct nvkm_clk *clk) in read_div() argument
44 return nv_rd32(clk, 0x004600); in read_div()
48 read_pll(struct nvkm_clk *clk, u32 base) in read_pll() argument
50 u32 ctrl = nv_rd32(clk, base + 0); in read_pll()
51 u32 coef = nv_rd32(clk, base + 4); in read_pll()
52 u32 ref = clk->read(clk, nv_clk_src_href); in read_pll()
59 post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); in read_pll()
62 post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; in read_pll()
79 mcp77_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) in mcp77_clk_read() argument
81 struct mcp77_clk_priv *priv = (void *)clk; in mcp77_clk_read()
[all …]
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| D | nv50.c | 54 struct nvkm_clk *clk = &priv->base; in read_pll_src() local
55 u32 coef, ref = clk->read(clk, nv_clk_src_crystal); in read_pll_src()
102 case 1: return clk->read(clk, nv_clk_src_crystal); in read_pll_src()
103 case 2: return clk->read(clk, nv_clk_src_href); in read_pll_src()
126 struct nvkm_clk *clk = &priv->base; in read_pll_ref() local
143 return clk->read(clk, nv_clk_src_crystal); in read_pll_ref()
150 return clk->read(clk, nv_clk_src_href); in read_pll_ref()
158 struct nvkm_clk *clk = &priv->base; in read_pll() local
169 return clk->read(clk, nv_clk_src_dom6); in read_pll()
190 nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) in nv50_clk_read() argument
[all …]
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| D | gf100.c | 51 struct nvkm_clk *clk = &priv->base; in read_vco() local
54 return clk->read(clk, nv_clk_src_sppll0); in read_vco()
55 return clk->read(clk, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_clk *clk = &priv->base; in read_pll() local
79 sclk = clk->read(clk, nv_clk_src_mpllsrc); in read_pll()
82 sclk = clk->read(clk, nv_clk_src_mpllsrcref); in read_pll()
124 read_clk(struct gf100_clk_priv *priv, int clk) in read_clk() argument
126 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); in read_clk()
130 if (ssel & (1 << clk)) { in read_clk()
131 if (clk < 7) in read_clk()
[all …]
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| D | gk104.c | 141 read_clk(struct gk104_clk_priv *priv, int clk) in read_clk() argument
143 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); in read_clk()
146 if (clk < 7) { in read_clk()
148 if (ssel & (1 << clk)) { in read_clk()
149 sclk = read_pll(priv, 0x137000 + (clk * 0x20)); in read_clk()
152 sclk = read_div(priv, clk, 0x137160, 0x1371d0); in read_clk()
156 u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); in read_clk()
158 sclk = read_div(priv, clk, 0x137160, 0x1371d0); in read_clk()
167 sclk = read_div(priv, clk, 0x137160, 0x1371d0); in read_clk()
184 gk104_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) in gk104_clk_read() argument
[all …]
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| D | gt215.c | 43 read_vco(struct gt215_clk_priv *priv, int clk) in read_vco() argument
45 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); in read_vco()
60 read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en) in read_clk() argument
65 if (clk >= 0x40) { in read_clk()
74 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); in read_clk()
97 sclk = read_vco(priv, clk); in read_clk()
106 read_pll(struct gt215_clk_priv *priv, int clk, u32 pll) in read_pll() argument
124 sclk = read_clk(priv, 0x00 + clk, false); in read_pll()
127 sclk = read_clk(priv, 0x10 + clk, false); in read_pll()
137 gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) in gt215_clk_read() argument
[all …]
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| D | Kbuild | 1 nvkm-y += nvkm/subdev/clk/base.o
2 nvkm-y += nvkm/subdev/clk/nv04.o
3 nvkm-y += nvkm/subdev/clk/nv40.o
4 nvkm-y += nvkm/subdev/clk/nv50.o
5 nvkm-y += nvkm/subdev/clk/g84.o
6 nvkm-y += nvkm/subdev/clk/gt215.o
7 nvkm-y += nvkm/subdev/clk/mcp77.o
8 nvkm-y += nvkm/subdev/clk/gf100.o
9 nvkm-y += nvkm/subdev/clk/gk104.o
10 nvkm-y += nvkm/subdev/clk/gk20a.o
[all …]
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| D | pllnv04.c | 29 getMNP_single(struct nvkm_subdev *subdev, struct nvbios_pll *info, int clk, in getMNP_single() argument
59 if (clk > 250000) in getMNP_single()
61 if (clk > 340000) in getMNP_single()
64 if (clk > 150000) in getMNP_single()
66 if (clk > 200000) in getMNP_single()
68 if (clk > 340000) in getMNP_single()
74 if ((clk * P) < minvco) { in getMNP_single()
75 minvco = clk * maxP; in getMNP_single()
79 if (clk + clk/200 > maxvco) /* +0.5% */ in getMNP_single()
80 maxvco = clk + clk/200; in getMNP_single()
[all …]
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| D | nv40.c | 56 u32 ref = 27000, clk = 0; in read_pll_1() local
59 clk = ref * N / M; in read_pll_1()
61 return clk >> P; in read_pll_1()
74 u32 ref = 27000, clk = 0; in read_pll_2() local
77 clk = ref * N1 / M1; in read_pll_2()
80 clk = clk * N2 / M2; in read_pll_2()
82 clk = 0; in read_pll_2()
86 return clk >> P; in read_pll_2()
105 nv40_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) in nv40_clk_read() argument
107 struct nv40_clk_priv *priv = (void *)clk; in nv40_clk_read()
[all …]
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| /linux-4.1.27/kernel/time/ |
| D | posix-clock.c | 35 struct posix_clock *clk = fp->private_data; in get_posix_clock() local
37 down_read(&clk->rwsem); in get_posix_clock()
39 if (!clk->zombie) in get_posix_clock()
40 return clk; in get_posix_clock()
42 up_read(&clk->rwsem); in get_posix_clock()
47 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
49 up_read(&clk->rwsem); in put_posix_clock()
55 struct posix_clock *clk = get_posix_clock(fp); in posix_clock_read() local
58 if (!clk) in posix_clock_read()
61 if (clk->ops.read) in posix_clock_read()
[all …]
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| /linux-4.1.27/arch/blackfin/mach-bf609/ |
| D | clock.c | 57 .clk = &_clk, \
89 int clk_enable(struct clk *clk) in clk_enable() argument
92 if (clk->ops && clk->ops->enable) in clk_enable()
93 ret = clk->ops->enable(clk); in clk_enable()
98 void clk_disable(struct clk *clk) in clk_disable() argument
100 if (clk->ops && clk->ops->disable) in clk_disable()
101 clk->ops->disable(clk); in clk_disable()
106 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
109 if (clk->ops && clk->ops->get_rate) in clk_get_rate()
110 ret = clk->ops->get_rate(clk); in clk_get_rate()
[all …]
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| /linux-4.1.27/arch/arm/mach-omap2/ |
| D | clkt_clksel.c | 61 static const struct clksel *_get_clksel_by_parent(struct clk_hw_omap *clk, in _get_clksel_by_parent() argument
62 struct clk *src_clk) in _get_clksel_by_parent()
69 for (clks = clk->clksel; clks->parent; clks++) in _get_clksel_by_parent()
76 __clk_get_name(clk->hw.clk), __clk_get_name(src_clk)); in _get_clksel_by_parent()
96 static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) in _write_clksel_reg() argument
100 v = omap2_clk_readl(clk, clk->clksel_reg); in _write_clksel_reg()
101 v &= ~clk->clksel_mask; in _write_clksel_reg()
102 v |= field_val << __ffs(clk->clksel_mask); in _write_clksel_reg()
103 omap2_clk_writel(v, clk, clk->clksel_reg); in _write_clksel_reg()
105 v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ in _write_clksel_reg()
[all …]
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| D | clock.c | 111 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) in omap2_clk_writel() argument
113 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) in omap2_clk_writel()
119 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) in omap2_clk_readl() argument
121 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) in omap2_clk_readl()
205 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, in _wait_idlest_generic() argument
212 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), in _wait_idlest_generic()
235 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) in _omap2_module_wait_ready() argument
243 if (clk->ops->find_companion) { in _omap2_module_wait_ready()
244 clk->ops->find_companion(clk, &companion_reg, &other_bit); in _omap2_module_wait_ready()
245 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) in _omap2_module_wait_ready()
[all …]
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| D | dpll3xxx.c | 43 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) in _omap3_dpll_write_clken() argument
48 dd = clk->dpll_data; in _omap3_dpll_write_clken()
50 v = omap2_clk_readl(clk, dd->control_reg); in _omap3_dpll_write_clken()
53 omap2_clk_writel(v, clk, dd->control_reg); in _omap3_dpll_write_clken()
57 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) in _omap3_wait_dpll_status() argument
64 dd = clk->dpll_data; in _omap3_wait_dpll_status()
65 clk_name = __clk_get_name(clk->hw.clk); in _omap3_wait_dpll_status()
69 while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
89 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) in _omap3_dpll_compute_freqsel() argument
94 fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; in _omap3_dpll_compute_freqsel()
[all …]
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| D | dpll44xx.c | 39 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_allow_gatectrl() argument
44 if (!clk || !clk->clksel_reg) in omap4_dpllmx_allow_gatectrl()
47 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
51 v = omap2_clk_readl(clk, clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
54 omap2_clk_writel(v, clk, clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
57 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_deny_gatectrl() argument
62 if (!clk || !clk->clksel_reg) in omap4_dpllmx_deny_gatectrl()
65 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_deny_gatectrl()
69 v = omap2_clk_readl(clk, clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
72 omap2_clk_writel(v, clk, clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
[all …]
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| D | omap_hwmod_33xx_43xx_interconnect_data.c | 25 .clk = "dpll_mpu_m2_ck",
33 .clk = "l3s_gclk",
41 .clk = "l3s_gclk",
49 .clk = "l3s_gclk",
57 .clk = "l3s_gclk",
65 .clk = "dpll_mpu_m2_ck",
73 .clk = "l3s_gclk",
81 .clk = "l3_gclk",
89 .clk = "dpll_core_m4_ck",
97 .clk = "dpll_core_m4_ck",
[all …]
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| D | omap_hwmod_2xxx_interconnect_data.c | 65 .clk = "uart1_ick",
73 .clk = "uart2_ick",
81 .clk = "uart3_ick",
89 .clk = "mcspi1_ick",
97 .clk = "mcspi2_ick",
105 .clk = "gpt2_ick",
113 .clk = "gpt3_ick",
121 .clk = "gpt4_ick",
129 .clk = "gpt5_ick",
137 .clk = "gpt6_ick",
[all …]
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| D | clock.h | 36 .clk = ck, \
50 static struct clk _name = { \
64 static struct clk _name = { \
71 .clk = &_name, \
79 static struct clk _name; \
82 .clk = &_name, \
95 static struct clk _name; \
98 .clk = &_name, \
158 struct clk *parent;
183 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
[all …]
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| D | omap_hwmod_43xx_data.c | 79 { .role = "dbclk", .clk = "gpio0_dbclk" },
281 { .role = "dbclk", .clk = "gpio4_dbclk" },
302 { .role = "dbclk", .clk = "gpio5_dbclk" },
589 .clk = "l3s_gclk",
596 .clk = "sys_clkin_ck",
603 .clk = "sys_clkin_ck",
610 .clk = "dpll_core_m4_ck",
617 .clk = "sys_clkin_ck",
624 .clk = "sys_clkin_ck",
631 .clk = "sys_clkin_ck",
[all …]
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| D | clkt_iclk.c | 26 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) in omap2_clkt_iclk_allow_idle() argument
32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_allow_idle()
34 v = omap2_clk_readl(clk, r); in omap2_clkt_iclk_allow_idle()
35 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
36 omap2_clk_writel(v, clk, r); in omap2_clkt_iclk_allow_idle()
40 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) in omap2_clkt_iclk_deny_idle() argument
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_deny_idle()
48 v = omap2_clk_readl(clk, r); in omap2_clkt_iclk_deny_idle()
49 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
50 omap2_clk_writel(v, clk, r); in omap2_clkt_iclk_deny_idle()
|
| D | omap_hwmod_44xx_data.c | 578 { .role = "sys_clk", .clk = "dss_sys_clk" },
579 { .role = "tv_clk", .clk = "dss_tv_clk" },
580 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
690 { .role = "sys_clk", .clk = "dss_sys_clk" },
724 { .role = "sys_clk", .clk = "dss_sys_clk" },
778 { .role = "sys_clk", .clk = "dss_sys_clk" },
832 { .role = "ick", .clk = "l3_div_ck" },
1031 { .role = "dbclk", .clk = "gpio1_dbclk" },
1053 { .role = "dbclk", .clk = "gpio2_dbclk" },
1076 { .role = "dbclk", .clk = "gpio3_dbclk" },
[all …]
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| D | omap_hwmod_7xx_data.c | 435 { .role = "dss_clk", .clk = "dss_dss_clk" },
436 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
437 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
438 { .role = "video2_clk", .clk = "dss_video2_clk" },
439 { .role = "video1_clk", .clk = "dss_video1_clk" },
440 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
528 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
614 { .role = "dbclk", .clk = "gpio1_dbclk" },
636 { .role = "dbclk", .clk = "gpio2_dbclk" },
659 { .role = "dbclk", .clk = "gpio3_dbclk" },
[all …]
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| D | omap_hwmod_54xx_data.c | 355 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
356 { .role = "sys_clk", .clk = "dss_sys_clk" },
357 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
402 { .role = "sys_clk", .clk = "dss_sys_clk" },
451 { .role = "sys_clk", .clk = "dss_sys_clk" },
472 { .role = "sys_clk", .clk = "dss_sys_clk" },
512 { .role = "sys_clk", .clk = "dss_sys_clk" },
553 { .role = "ick", .clk = "l3_iclk_div" },
648 { .role = "dbclk", .clk = "gpio1_dbclk" },
670 { .role = "dbclk", .clk = "gpio2_dbclk" },
[all …]
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| D | clock3517.c | 50 static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, in am35xx_clk_find_idlest() argument
55 *idlest_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_idlest()
56 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
74 static void am35xx_clk_find_companion(struct clk_hw_omap *clk, in am35xx_clk_find_companion() argument
78 *other_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_companion()
79 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
80 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
82 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
100 static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, in am35xx_clk_ipss_find_idlest() argument
107 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in am35xx_clk_ipss_find_idlest()
|
| /linux-4.1.27/arch/mips/bcm63xx/ |
| D | clk.c | 19 struct clk { struct
20 void (*set)(struct clk *, int); argument
29 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked() argument
31 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
32 clk->set(clk, 1); in clk_enable_unlocked()
35 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked() argument
37 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
38 clk->set(clk, 0); in clk_disable_unlocked()
56 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
72 static struct clk clk_enet_misc = {
[all …]
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| /linux-4.1.27/arch/mips/lantiq/xway/ |
| D | sysctrl.c | 109 static int cgu_enable(struct clk *clk) in cgu_enable() argument
111 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); in cgu_enable()
116 static void cgu_disable(struct clk *clk) in cgu_disable() argument
118 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); in cgu_disable()
122 static int pmu_enable(struct clk *clk) in pmu_enable() argument
126 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, in pmu_enable()
127 PWDCR(clk->module)); in pmu_enable()
128 do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits)); in pmu_enable()
137 static void pmu_disable(struct clk *clk) in pmu_disable() argument
139 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, in pmu_disable()
[all …]
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| D | clk.c | 58 unsigned long clk; in ltq_danube_pp32_hz() local
62 clk = CLOCK_240M; in ltq_danube_pp32_hz()
65 clk = CLOCK_222M; in ltq_danube_pp32_hz()
68 clk = CLOCK_133M; in ltq_danube_pp32_hz()
71 clk = CLOCK_266M; in ltq_danube_pp32_hz()
75 return clk; in ltq_danube_pp32_hz()
105 unsigned long clk; in ltq_vr9_cpu_hz() local
111 clk = CLOCK_600M; in ltq_vr9_cpu_hz()
114 clk = CLOCK_500M; in ltq_vr9_cpu_hz()
117 clk = CLOCK_393M; in ltq_vr9_cpu_hz()
[all …]
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| D | gptu.c | 96 static int gptu_enable(struct clk *clk) in gptu_enable() argument
98 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, in gptu_enable()
106 GPTU_CON(clk->bits)); in gptu_enable()
107 gptu_w32(1, GPTU_RLD(clk->bits)); in gptu_enable()
108 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); in gptu_enable()
109 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); in gptu_enable()
113 static void gptu_disable(struct clk *clk) in gptu_disable() argument
115 gptu_w32(0, GPTU_RUN(clk->bits)); in gptu_disable()
116 gptu_w32(0, GPTU_CON(clk->bits)); in gptu_disable()
117 gptu_w32(0, GPTU_RLD(clk->bits)); in gptu_disable()
[all …]
|
| /linux-4.1.27/arch/arm/boot/dts/ |
| D | stih410-clock.dtsi | 15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
[all …]
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| D | stih418-clock.dtsi | 15 compatible = "st,stih418-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
[all …]
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| D | stih407-clock.dtsi | 18 clk_sysin: clk-sysin {
27 arm_periph_clk: clk-m-a9-periphs {
56 clk_m_a9: clk-m-a9@92b0000 {
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
76 clock-output-names = "clk-m-a9-ext2f-div2";
90 clock-output-names = "clk-s-icn-reg-0";
97 clk_s_a0_pll: clk-s-a0-pll {
103 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clk_s_a0_flexgen: clk-s-a0-flexgen {
114 clock-output-names = "clk-ic-lmi0";
[all …]
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| D | stih416-clock.dtsi | 21 clk_sysin: clk-sysin {
33 clk_s_a0_pll: clk-s-a0-pll {
39 clock-output-names = "clk-s-a0-pll0-hs",
40 "clk-s-a0-pll0-ls",
41 "clk-s-a0-pll1";
44 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
51 clock-output-names = "clk-s-a0-osc-prediv";
54 clk_s_a0_hs: clk-s-a0-hs {
63 clock-output-names = "clk-s-fdma-0",
64 "clk-s-fdma-1",
[all …]
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| D | stih415-clock.dtsi | 20 clk_sysin: clk-sysin {
32 clk_s_a0_pll: clk-s-a0-pll {
38 clock-output-names = "clk-s-a0-pll0-hs",
39 "clk-s-a0-pll0-ls",
40 "clk-s-a0-pll1";
43 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
50 clock-output-names = "clk-s-a0-osc-prediv";
53 clk_s_a0_hs: clk-s-a0-hs {
62 clock-output-names = "clk-s-fdma-0",
63 "clk-s-fdma-1",
[all …]
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| D | socfpga.dtsi | 112 compatible = "altr,clk-mgr";
149 compatible = "altr,socfpga-perip-clk";
157 compatible = "altr,socfpga-perip-clk";
165 compatible = "altr,socfpga-perip-clk";
173 compatible = "altr,socfpga-perip-clk";
180 compatible = "altr,socfpga-perip-clk";
187 compatible = "altr,socfpga-perip-clk";
203 compatible = "altr,socfpga-perip-clk";
210 compatible = "altr,socfpga-perip-clk";
217 compatible = "altr,socfpga-perip-clk";
[all …]
|
| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| D | clock.c | 30 struct clk { struct
31 struct clk *parent; argument
38 unsigned long (*get_rate)(struct clk *clk); argument
39 int (*set_rate)(struct clk *clk, unsigned long rate); argument
43 static unsigned long get_uart_rate(struct clk *clk);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
50 static struct clk clk_xtali = {
[all …]
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| /linux-4.1.27/arch/arm/mach-mmp/ |
| D | clock.c | 19 static void apbc_clk_enable(struct clk *clk) in apbc_clk_enable() argument
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); in apbc_clk_enable()
24 __raw_writel(clk_rst, clk->clk_rst); in apbc_clk_enable()
27 static void apbc_clk_disable(struct clk *clk) in apbc_clk_disable() argument
29 __raw_writel(0, clk->clk_rst); in apbc_clk_disable()
37 static void apmu_clk_enable(struct clk *clk) in apmu_clk_enable() argument
39 __raw_writel(clk->enable_val, clk->clk_rst); in apmu_clk_enable()
42 static void apmu_clk_disable(struct clk *clk) in apmu_clk_disable() argument
44 __raw_writel(0, clk->clk_rst); in apmu_clk_disable()
54 int clk_enable(struct clk *clk) in clk_enable() argument
[all …]
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| D | clock.h | 12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
14 unsigned long (*getrate)(struct clk *);
15 int (*setrate)(struct clk *, unsigned long);
18 struct clk { struct
32 struct clk clk_##_name = { \ argument
40 struct clk clk_##_name = { \
48 struct clk clk_##_name = { \
56 struct clk clk_##_name = { \
65 .clk = _clk, \
[all …]
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| /linux-4.1.27/arch/arm/mach-sa1100/ |
| D | clock.c | 21 void (*enable)(struct clk *);
22 void (*disable)(struct clk *);
23 unsigned long (*get_rate)(struct clk *);
26 struct clk { struct
32 struct clk clk_##_name = { \ argument
38 static void clk_gpio27_enable(struct clk *clk) in clk_gpio27_enable() argument
49 static void clk_gpio27_disable(struct clk *clk) in clk_gpio27_disable() argument
56 static void clk_cpu_enable(struct clk *clk) in clk_cpu_enable() argument
60 static void clk_cpu_disable(struct clk *clk) in clk_cpu_disable() argument
64 static unsigned long clk_cpu_get_rate(struct clk *clk) in clk_cpu_get_rate() argument
[all …]
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| /linux-4.1.27/arch/mips/ralink/ |
| D | clk.c | 19 struct clk { struct
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); in ralink_clk_add() local
28 if (!clk) in ralink_clk_add()
31 clk->cl.dev_id = dev; in ralink_clk_add()
32 clk->cl.clk = clk; in ralink_clk_add()
34 clk->rate = rate; in ralink_clk_add()
36 clkdev_add(&clk->cl); in ralink_clk_add()
42 int clk_enable(struct clk *clk) in clk_enable() argument
48 void clk_disable(struct clk *clk) in clk_disable() argument
53 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
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| /linux-4.1.27/arch/arm/plat-versatile/ |
| D | clock.c | 21 int clk_enable(struct clk *clk) in clk_enable() argument
27 void clk_disable(struct clk *clk) in clk_disable() argument
32 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
34 return clk->rate; in clk_get_rate()
38 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
41 if (clk->ops && clk->ops->round) in clk_round_rate()
42 ret = clk->ops->round(clk, rate); in clk_round_rate()
47 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
50 if (clk->ops && clk->ops->set) in clk_set_rate()
51 ret = clk->ops->set(clk, rate); in clk_set_rate()
[all …]
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| /linux-4.1.27/arch/mips/lantiq/falcon/ |
| D | sysctrl.c | 82 static inline void sysctl_wait(struct clk *clk, in sysctl_wait() argument
87 do {} while (--err && ((sysctl_r32(clk->module, reg) in sysctl_wait()
88 & clk->bits) != test)); in sysctl_wait()
91 clk->module, clk->bits, test, in sysctl_wait()
92 sysctl_r32(clk->module, reg) & clk->bits); in sysctl_wait()
95 static int sysctl_activate(struct clk *clk) in sysctl_activate() argument
97 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); in sysctl_activate()
98 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); in sysctl_activate()
99 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); in sysctl_activate()
103 static void sysctl_deactivate(struct clk *clk) in sysctl_deactivate() argument
[all …]
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| /linux-4.1.27/arch/arm/mach-lpc32xx/ |
| D | clock.c | 106 static struct clk clk_armpll;
107 static struct clk clk_usbpll;
114 static unsigned long local_return_parent_rate(struct clk *clk) in local_return_parent_rate() argument
120 while (clk->rate == 0) in local_return_parent_rate()
121 clk = clk->parent; in local_return_parent_rate()
123 return clk->rate; in local_return_parent_rate()
127 static struct clk osc_32KHz = {
132 static int local_pll397_enable(struct clk *clk, int enable) in local_pll397_enable() argument
161 static int local_oscmain_enable(struct clk *clk, int enable) in local_oscmain_enable() argument
190 static struct clk osc_pll397 = {
[all …]
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| /linux-4.1.27/arch/arm/mach-pxa/ |
| D | clock.c | 15 int clk_enable(struct clk *clk) in clk_enable() argument
20 if (clk->enabled++ == 0) in clk_enable()
21 clk->ops->enable(clk); in clk_enable()
24 if (clk->delay) in clk_enable()
25 udelay(clk->delay); in clk_enable()
31 void clk_disable(struct clk *clk) in clk_disable() argument
35 WARN_ON(clk->enabled == 0); in clk_disable()
38 if (--clk->enabled == 0) in clk_disable()
39 clk->ops->disable(clk); in clk_disable()
44 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
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| D | clock.h | 5 void (*enable)(struct clk *);
6 void (*disable)(struct clk *);
7 unsigned long (*getrate)(struct clk *);
8 int (*setrate)(struct clk *, unsigned long);
11 struct clk { struct
19 void clk_dummy_enable(struct clk *); argument
20 void clk_dummy_disable(struct clk *);
23 extern struct clk clk_dummy;
27 .clk = _clk, \
33 struct clk clk_##_name = { \
[all …]
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| D | clock-pxa3xx.c | 79 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) in clk_pxa3xx_ac97_getrate() argument
98 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) in clk_pxa3xx_hsio_getrate() argument
115 static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) in clk_pxa3xx_smemc_getrate() argument
124 void clk_pxa3xx_cken_enable(struct clk *clk) in clk_pxa3xx_cken_enable() argument
126 unsigned long mask = 1ul << (clk->cken & 0x1f); in clk_pxa3xx_cken_enable()
128 if (clk->cken < 32) in clk_pxa3xx_cken_enable()
130 else if (clk->cken < 64) in clk_pxa3xx_cken_enable()
136 void clk_pxa3xx_cken_disable(struct clk *clk) in clk_pxa3xx_cken_disable() argument
138 unsigned long mask = 1ul << (clk->cken & 0x1f); in clk_pxa3xx_cken_disable()
140 if (clk->cken < 32) in clk_pxa3xx_cken_disable()
[all …]
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| /linux-4.1.27/arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 25 static unsigned long emi_clk_recalc(struct clk *clk) in emi_clk_recalc() argument
28 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
48 static struct clk sh4202_emi_clk = {
53 static unsigned long femi_clk_recalc(struct clk *clk) in femi_clk_recalc() argument
56 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
63 static struct clk sh4202_femi_clk = {
68 static void shoc_clk_init(struct clk *clk) in shoc_clk_init() argument
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
[all …]
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| D | clock-sh4.c | 29 static void master_clk_init(struct clk *clk) in master_clk_init() argument
31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
38 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
41 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
48 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
51 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
58 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
61 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
|
| /linux-4.1.27/drivers/clk/ti/ |
| D | clk.c | 46 struct clk *clk; in ti_dt_clocks_register() local
52 clk = of_clk_get_from_provider(&clkspec); in ti_dt_clocks_register()
54 if (!IS_ERR(clk)) { in ti_dt_clocks_register()
55 c->lk.clk = clk; in ti_dt_clocks_register()
199 struct clk __init *ti_clk_register_clk(struct ti_clk *setup) in ti_clk_register_clk()
201 struct clk *clk; in ti_clk_register_clk() local
206 if (setup->clk) in ti_clk_register_clk()
207 return setup->clk; in ti_clk_register_clk()
213 clk = clk_register_fixed_rate(NULL, setup->name, NULL, in ti_clk_register_clk()
217 clk = ti_clk_register_mux(setup); in ti_clk_register_clk()
[all …]
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| D | autoidle.c | 37 static void ti_allow_autoidle(struct clk_ti_autoidle *clk) in ti_allow_autoidle() argument
41 val = ti_clk_ll_ops->clk_readl(clk->reg); in ti_allow_autoidle()
43 if (clk->flags & AUTOIDLE_LOW) in ti_allow_autoidle()
44 val &= ~(1 << clk->shift); in ti_allow_autoidle()
46 val |= (1 << clk->shift); in ti_allow_autoidle()
48 ti_clk_ll_ops->clk_writel(val, clk->reg); in ti_allow_autoidle()
51 static void ti_deny_autoidle(struct clk_ti_autoidle *clk) in ti_deny_autoidle() argument
55 val = ti_clk_ll_ops->clk_readl(clk->reg); in ti_deny_autoidle()
57 if (clk->flags & AUTOIDLE_LOW) in ti_deny_autoidle()
58 val |= (1 << clk->shift); in ti_deny_autoidle()
[all …]
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| D | Makefile | 1 obj-y += clk.o autoidle.o clockdomain.o
2 clk-common = dpll.o composite.o divider.o gate.o \
4 obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
5 obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
6 obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
7 obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
8 clk-3xxx.o
9 obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
10 obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
11 obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
[all …]
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| D | composite.c | 108 static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) in _get_hw() argument
110 if (!clk) in _get_hw()
113 if (!clk->comp_clks[idx]) in _get_hw()
116 return clk->comp_clks[idx]->hw; in _get_hw()
122 struct clk *ti_clk_register_composite(struct ti_clk *setup) in ti_clk_register_composite()
130 struct clk *clk; in ti_clk_register_composite() local
149 clk = clk_register_composite(NULL, setup->name, in ti_clk_register_composite()
155 return clk; in ti_clk_register_composite()
162 struct clk *clk; in _register_composite() local
213 clk = clk_register_composite(NULL, node->name, in _register_composite()
[all …]
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| D | apll.c | 39 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in dra7_apll_enable() local
46 ad = clk->dpll_data; in dra7_apll_enable()
50 clk_name = __clk_get_name(clk->hw.clk); in dra7_apll_enable()
90 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in dra7_apll_disable() local
95 ad = clk->dpll_data; in dra7_apll_disable()
107 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in dra7_apll_is_enabled() local
111 ad = clk->dpll_data; in dra7_apll_is_enabled()
138 struct clk *clk; in omap_clk_register_apll() local
152 clk = clk_register(NULL, &clk_hw->hw); in omap_clk_register_apll()
153 if (!IS_ERR(clk)) { in omap_clk_register_apll()
[all …]
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| /linux-4.1.27/arch/mips/include/asm/ |
| D | clock.h | 9 struct clk;
12 void (*init) (struct clk *clk);
13 void (*enable) (struct clk *clk);
14 void (*disable) (struct clk *clk);
15 void (*recalc) (struct clk *clk);
16 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
17 long (*round_rate) (struct clk *clk, unsigned long rate);
20 struct clk { struct
26 struct clk *parent; argument
40 int __clk_enable(struct clk *); argument
[all …]
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| /linux-4.1.27/arch/mips/loongson/lemote-2f/ |
| D | clock.c | 44 static struct clk cpu_clk = {
50 struct clk *clk_get(struct device *dev, const char *id) in clk_get()
56 static void propagate_rate(struct clk *clk) in propagate_rate() argument
58 struct clk *clkp; in propagate_rate()
61 if (likely(clkp->parent != clk)) in propagate_rate()
70 int clk_enable(struct clk *clk) in clk_enable() argument
76 void clk_disable(struct clk *clk) in clk_disable() argument
81 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
83 return (unsigned long)clk->rate; in clk_get_rate()
87 void clk_put(struct clk *clk) in clk_put() argument
[all …]
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| /linux-4.1.27/Documentation/devicetree/bindings/clock/st/ |
| D | st,flexgen.txt | 74 clk_s_c0_flexgen: clk-s-c0-flexgen {
87 clock-output-names = "clk-icn-gpu",
88 "clk-fdma",
89 "clk-nand",
90 "clk-hva",
91 "clk-proc-stfe",
92 "clk-proc-tp",
93 "clk-rx-icn-dmu",
94 "clk-rx-icn-hva",
95 "clk-icn-cpu",
[all …]
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| /linux-4.1.27/drivers/clk/versatile/ |
| D | clk-realview.c | 53 struct clk *clk; in realview_clk_init() local
56 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); in realview_clk_init()
57 clk_register_clkdev(clk, "apb_pclk", NULL); in realview_clk_init()
60 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, in realview_clk_init()
62 clk_register_clkdev(clk, NULL, "dev:uart0"); in realview_clk_init()
63 clk_register_clkdev(clk, NULL, "dev:uart1"); in realview_clk_init()
64 clk_register_clkdev(clk, NULL, "dev:uart2"); in realview_clk_init()
65 clk_register_clkdev(clk, NULL, "fpga:kmi0"); in realview_clk_init()
66 clk_register_clkdev(clk, NULL, "fpga:kmi1"); in realview_clk_init()
67 clk_register_clkdev(clk, NULL, "fpga:mmc0"); in realview_clk_init()
[all …]
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| D | clk-impd1.c | 24 struct clk *pclk;
26 struct clk *vco1clk;
28 struct clk *vco2clk;
29 struct clk *mmciclk;
31 struct clk *uartclk;
33 struct clk *spiclk;
35 struct clk *scclk;
90 struct clk *clk; in integrator_impd1_clk_init() local
91 struct clk *pclk; in integrator_impd1_clk_init()
107 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, in integrator_impd1_clk_init()
[all …]
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| /linux-4.1.27/drivers/clk/samsung/ |
| D | Makefile | 5 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6 obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
7 obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
8 obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
9 obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
10 obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
11 obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
12 obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
13 obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o
14 obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
[all …]
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| D | clk.c | 59 struct clk **clk_table; in samsung_clk_init()
66 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in samsung_clk_init()
92 void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, in samsung_clk_add_lookup() argument
96 ctx->clk_data.clks[id] = clk; in samsung_clk_add_lookup()
104 struct clk *clk; in samsung_clk_register_alias() local
119 clk = ctx->clk_data.clks[list->id]; in samsung_clk_register_alias()
120 if (!clk) { in samsung_clk_register_alias()
126 ret = clk_register_clkdev(clk, list->alias, list->dev_name); in samsung_clk_register_alias()
137 struct clk *clk; in samsung_clk_register_fixed_rate() local
141 clk = clk_register_fixed_rate(NULL, list->name, in samsung_clk_register_fixed_rate()
[all …]
|
| /linux-4.1.27/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7780.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
37 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
54 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
57 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
77 static unsigned long shyway_clk_recalc(struct clk *clk) in shyway_clk_recalc() argument
80 return clk->parent->rate / cfc_divisors[idx]; in shyway_clk_recalc()
[all …]
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| D | clock-sh7763.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; in master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
37 return clk->parent->rate / p0fc_divisors[idx]; in module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
71 static unsigned long shyway_clk_recalc(struct clk *clk) in shyway_clk_recalc() argument
74 return clk->parent->rate / cfc_divisors[idx]; in shyway_clk_recalc()
81 static struct clk sh7763_shyway_clk = {
90 static struct clk *sh7763_onchip_clocks[] = {
[all …]
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| D | clock-sh7770.c | 22 static void master_clk_init(struct clk *clk) in master_clk_init() argument
24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
31 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
44 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
51 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
54 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
|
| /linux-4.1.27/Documentation/devicetree/bindings/clock/ |
| D | sunxi.txt | 9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
14 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
[all …]
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| D | at91-clock.txt | 13 "atmel,at91sam9x5-clk-slow-osc":
16 "atmel,at91sam9x5-clk-slow-rc-osc":
28 "atmel,at91sam9x5-clk-slow" (under sckc node)
30 "atmel,at91sam9260-clk-slow" (under pmc node):
31 at91 slow clk
33 "atmel,at91rm9200-clk-main-osc"
34 "atmel,at91sam9x5-clk-main-rc-osc"
35 at91 main clk sources
37 "atmel,at91sam9x5-clk-main"
38 "atmel,at91rm9200-clk-main":
[all …]
|
| /linux-4.1.27/arch/arm/mach-w90x900/ |
| D | clock.c | 32 int clk_enable(struct clk *clk) in clk_enable() argument
37 if (clk->enabled++ == 0) in clk_enable()
38 (clk->enable)(clk, 1); in clk_enable()
45 void clk_disable(struct clk *clk) in clk_disable() argument
49 WARN_ON(clk->enabled == 0); in clk_disable()
52 if (--clk->enabled == 0) in clk_disable()
53 (clk->enable)(clk, 0); in clk_disable()
58 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
64 void nuc900_clk_enable(struct clk *clk, int enable) in nuc900_clk_enable() argument
66 unsigned int clocks = clk->cken; in nuc900_clk_enable()
[all …]
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| D | clock.h | 15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
18 struct clk { struct
21 void (*enable)(struct clk *, int enable); argument
25 struct clk clk_##_name = { \
31 struct clk clk_##_name = { \
39 .clk = _clk, \
|
| D | time.c | 52 struct clock_event_device *clk) in nuc900_clockevent_setmode() argument
79 struct clock_event_device *clk) in nuc900_clockevent_setnextevent() argument
121 struct clk *clk = clk_get(NULL, "timer0"); in nuc900_clockevents_init() local
123 BUG_ON(IS_ERR(clk)); in nuc900_clockevents_init()
127 clk_enable(clk); in nuc900_clockevents_init()
128 rate = clk_get_rate(clk) / (PRESCALE + 1); in nuc900_clockevents_init()
145 struct clk *clk = clk_get(NULL, "timer1"); in nuc900_clocksource_init() local
147 BUG_ON(IS_ERR(clk)); in nuc900_clocksource_init()
151 clk_enable(clk); in nuc900_clocksource_init()
152 rate = clk_get_rate(clk) / (PRESCALE + 1); in nuc900_clocksource_init()
|
| /linux-4.1.27/drivers/clk/tegra/ |
| D | Makefile | 1 obj-y += clk.o
2 obj-y += clk-audio-sync.o
3 obj-y += clk-divider.o
4 obj-y += clk-periph.o
5 obj-y += clk-periph-gate.o
6 obj-y += clk-pll.o
7 obj-y += clk-pll-out.o
8 obj-y += clk-super.o
9 obj-y += clk-tegra-audio.o
10 obj-y += clk-tegra-periph.o
[all …]
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| D | clk-tegra-super-gen4.c | 56 struct clk *clk; in tegra_sclk_init() local
57 struct clk **dt_clk; in tegra_sclk_init()
62 clk = tegra_clk_register_super_mux("sclk", sclk_parents, in tegra_sclk_init()
67 *dt_clk = clk; in tegra_sclk_init()
73 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, in tegra_sclk_init()
76 clk = clk_register_gate(NULL, "hclk", "hclk_div", in tegra_sclk_init()
80 *dt_clk = clk; in tegra_sclk_init()
88 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, in tegra_sclk_init()
91 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | in tegra_sclk_init()
94 *dt_clk = clk; in tegra_sclk_init()
[all …]
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| D | clk-tegra-fixed.c | 38 struct clk *clk, *osc; in tegra_osc_clk_init() local
39 struct clk **dt_clk; in tegra_osc_clk_init()
63 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", in tegra_osc_clk_init()
65 *dt_clk = clk; in tegra_osc_clk_init()
74 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc", in tegra_osc_clk_init()
76 *dt_clk = clk; in tegra_osc_clk_init()
86 struct clk *clk; in tegra_fixed_clk_init() local
87 struct clk **dt_clk; in tegra_fixed_clk_init()
92 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, in tegra_fixed_clk_init()
94 *dt_clk = clk; in tegra_fixed_clk_init()
[all …]
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| D | clk-tegra20.c | 167 static struct clk **clks;
638 struct clk *clk; in tegra20_pll_init() local
641 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
643 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
646 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra20_pll_init()
649 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", in tegra20_pll_init()
652 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
655 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
658 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
661 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra20_pll_init()
[all …]
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| D | clk.c | 78 static struct clk **clks;
182 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) in tegra_clk_init()
196 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); in tegra_clk_init()
206 struct clk *clks[], int clk_max) in tegra_init_dup_clks()
208 struct clk *clk; in tegra_init_dup_clks() local
211 clk = clks[dup_list->clk_id]; in tegra_init_dup_clks()
212 dup_list->lookup.clk = clk; in tegra_init_dup_clks()
218 struct clk *clks[], int clk_max) in tegra_init_from_table()
220 struct clk *clk; in tegra_init_from_table() local
223 clk = clks[tbl->clk_id]; in tegra_init_from_table()
[all …]
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| D | clk-tegra-audio.c | 131 struct clk *clk; in tegra_audio_clk_init() local
132 struct clk **dt_clk; in tegra_audio_clk_init()
138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, in tegra_audio_clk_init()
140 *dt_clk = clk; in tegra_audio_clk_init()
146 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra_audio_clk_init()
149 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", in tegra_audio_clk_init()
152 *dt_clk = clk; in tegra_audio_clk_init()
164 clk = tegra_clk_register_sync_source(data->name, in tegra_audio_clk_init()
166 *dt_clk = clk; in tegra_audio_clk_init()
177 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk, in tegra_audio_clk_init()
[all …]
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| D | clk-tegra124.c | 1022 static struct clk **clks;
1109 struct clk *clk; in tegra124_periph_clk_init() local
1112 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, in tegra124_periph_clk_init()
1114 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; in tegra124_periph_clk_init()
1116 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, in tegra124_periph_clk_init()
1118 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; in tegra124_periph_clk_init()
1120 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, in tegra124_periph_clk_init()
1123 clks[TEGRA124_CLK_DSIA] = clk; in tegra124_periph_clk_init()
1125 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, in tegra124_periph_clk_init()
1128 clks[TEGRA124_CLK_DSIB] = clk; in tegra124_periph_clk_init()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/armada/ |
| D | armada_510.c | 20 struct clk *clk; in armada510_crtc_init() local
22 clk = devm_clk_get(dev, "ext_ref_clk1"); in armada510_crtc_init()
23 if (IS_ERR(clk)) in armada510_crtc_init()
24 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); in armada510_crtc_init()
26 dcrtc->extclk[0] = clk; in armada510_crtc_init()
47 struct clk *clk = dcrtc->extclk[0]; in armada510_crtc_compute_clock() local
53 if (IS_ERR(clk)) in armada510_crtc_compute_clock()
54 return PTR_ERR(clk); in armada510_crtc_compute_clock()
56 if (dcrtc->clk != clk) { in armada510_crtc_compute_clock()
57 ret = clk_prepare_enable(clk); in armada510_crtc_compute_clock()
[all …]
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| /linux-4.1.27/drivers/cpufreq/ |
| D | ls1x-cpufreq.c | 25 struct clk *clk; /* CPU clk */ member
26 struct clk *mux_clk; /* MUX of CPU clk */
27 struct clk *pll_clk; /* PLL clk */
28 struct clk *osc_clk; /* OSC clk */
64 clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk); in ls1x_cpufreq_target()
70 clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk); in ls1x_cpufreq_target()
105 policy->clk = ls1x_cpufreq.clk; in ls1x_cpufreq_init()
142 struct clk *clk; in ls1x_cpufreq_probe() local
150 clk = devm_clk_get(&pdev->dev, pdata->clk_name); in ls1x_cpufreq_probe()
151 if (IS_ERR(clk)) { in ls1x_cpufreq_probe()
[all …]
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| D | spear-cpufreq.c | 28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
76 static int spear1340_set_cpu_rate(struct clk *sys_pclk, unsigned long newfreq) in spear1340_set_cpu_rate()
78 struct clk *sys_clk; in spear1340_set_cpu_rate()
81 sys_clk = clk_get_parent(spear_cpufreq.clk); in spear1340_set_cpu_rate()
107 struct clk *srcclk; in spear_cpufreq_target()
133 srcclk = spear_cpufreq.clk; in spear_cpufreq_target()
145 ret = clk_set_rate(spear_cpufreq.clk, newfreq); in spear_cpufreq_target()
155 policy->clk = spear_cpufreq.clk; in spear_cpufreq_init()
[all …]
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| /linux-4.1.27/drivers/clk/hisilicon/ |
| D | clk-hix5hd2.c | 174 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); in clk_ether_prepare() local
177 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
178 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; in clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
180 val &= ~(clk->ctrl_rst_mask); in clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()
184 val |= clk->phy_clk_mask; in clk_ether_prepare()
185 val &= ~(clk->phy_rst_mask); in clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
[all …]
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| D | clk.c | 45 struct clk **clk_table; in hisi_clk_init()
66 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); in hisi_clk_init()
84 struct clk *clk; in hisi_clk_register_fixed_rate() local
88 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
92 if (IS_ERR(clk)) { in hisi_clk_register_fixed_rate()
97 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
105 struct clk *clk; in hisi_clk_register_fixed_factor() local
109 clk = clk_register_fixed_factor(NULL, clks[i].name, in hisi_clk_register_fixed_factor()
113 if (IS_ERR(clk)) { in hisi_clk_register_fixed_factor()
118 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_factor()
[all …]
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| /linux-4.1.27/arch/c6x/include/asm/ |
| D | clock.h | 82 struct clk { struct
89 struct clk *parent; argument
94 unsigned long (*recalc) (struct clk *); argument
95 int (*set_rate) (struct clk *clk, unsigned long rate); argument
96 int (*round_rate) (struct clk *clk, unsigned long rate); argument
116 struct clk sysclks[MAX_PLL_SYSCLKS + 1];
128 .clk = ck, \
132 extern int clk_register(struct clk *clk);
133 extern void clk_unregister(struct clk *clk);
138 extern struct clk clkin1;
[all …]
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| /linux-4.1.27/drivers/clk/qcom/ |
| D | Makefile | 1 obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
3 clk-qcom-y += common.o
4 clk-qcom-y += clk-regmap.o
5 clk-qcom-y += clk-pll.o
6 clk-qcom-y += clk-rcg.o
7 clk-qcom-y += clk-rcg2.o
8 clk-qcom-y += clk-branch.o
9 clk-qcom-y += clk-regmap-divider.o
10 clk-qcom-y += clk-regmap-mux.o
11 clk-qcom-y += reset.o
|
| /linux-4.1.27/drivers/clk/zynq/ |
| D | pll.c | 86 struct zynq_pll *clk = to_zynq_pll(hw); in zynq_pll_recalc_rate() local
93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
111 struct zynq_pll *clk = to_zynq_pll(hw); in zynq_pll_is_enabled() local
113 spin_lock_irqsave(clk->lock, flags); in zynq_pll_is_enabled()
115 reg = clk_readl(clk->pll_ctrl); in zynq_pll_is_enabled()
117 spin_unlock_irqrestore(clk->lock, flags); in zynq_pll_is_enabled()
131 struct zynq_pll *clk = to_zynq_pll(hw); in zynq_pll_enable() local
139 spin_lock_irqsave(clk->lock, flags); in zynq_pll_enable()
141 reg = clk_readl(clk->pll_ctrl); in zynq_pll_enable()
143 clk_writel(reg, clk->pll_ctrl); in zynq_pll_enable()
[all …]
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| /linux-4.1.27/arch/arm/common/ |
| D | timer-sp.c | 36 static long __init sp804_get_clock_rate(struct clk *clk) in sp804_get_clock_rate() argument
41 err = clk_prepare(clk); in sp804_get_clock_rate()
44 clk_put(clk); in sp804_get_clock_rate()
48 err = clk_enable(clk); in sp804_get_clock_rate()
51 clk_unprepare(clk); in sp804_get_clock_rate()
52 clk_put(clk); in sp804_get_clock_rate()
56 rate = clk_get_rate(clk); in sp804_get_clock_rate()
59 clk_disable(clk); in sp804_get_clock_rate()
60 clk_unprepare(clk); in sp804_get_clock_rate()
61 clk_put(clk); in sp804_get_clock_rate()
[all …]
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| /linux-4.1.27/drivers/clk/rockchip/ |
| D | clk.c | 41 static struct clk *rockchip_clk_register_branch(const char *name, in rockchip_clk_register_branch()
49 struct clk *clk; in rockchip_clk_register_branch() local
96 clk = clk_register_composite(NULL, name, parent_names, num_parents, in rockchip_clk_register_branch()
102 return clk; in rockchip_clk_register_branch()
105 static struct clk *rockchip_clk_register_frac_branch(const char *name, in rockchip_clk_register_frac_branch()
111 struct clk *clk; in rockchip_clk_register_frac_branch() local
144 clk = clk_register_composite(NULL, name, parent_names, num_parents, in rockchip_clk_register_frac_branch()
150 return clk; in rockchip_clk_register_frac_branch()
154 static struct clk **clk_table;
167 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in rockchip_clk_init()
[all …]
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| /linux-4.1.27/arch/sh/kernel/ |
| D | localtimer.c | 35 struct clock_event_device *clk = this_cpu_ptr(&local_clockevent); in local_timer_interrupt() local
38 clk->event_handler(clk); in local_timer_interrupt()
43 struct clock_event_device *clk) in dummy_timer_set_mode() argument
49 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); in local_timer_setup() local
51 clk->name = "dummy_timer"; in local_timer_setup()
52 clk->features = CLOCK_EVT_FEAT_ONESHOT | in local_timer_setup()
55 clk->rating = 400; in local_timer_setup()
56 clk->mult = 1; in local_timer_setup()
57 clk->set_mode = dummy_timer_set_mode; in local_timer_setup()
58 clk->broadcast = smp_timer_broadcast; in local_timer_setup()
[all …]
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| /linux-4.1.27/drivers/rtc/ |
| D | rtc-coh901331.c | 45 struct clk *clk; member
57 clk_enable(rtap->clk); in coh901331_interrupt()
68 clk_disable(rtap->clk); in coh901331_interrupt()
80 clk_enable(rtap->clk); in coh901331_read_time()
84 clk_disable(rtap->clk); in coh901331_read_time()
87 clk_disable(rtap->clk); in coh901331_read_time()
95 clk_enable(rtap->clk); in coh901331_set_mmss()
97 clk_disable(rtap->clk); in coh901331_set_mmss()
106 clk_enable(rtap->clk); in coh901331_read_alarm()
110 clk_disable(rtap->clk); in coh901331_read_alarm()
[all …]
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| /linux-4.1.27/drivers/clk/sunxi/ |
| D | Makefile | 5 obj-y += clk-sunxi.o clk-factors.o
6 obj-y += clk-a10-hosc.o
7 obj-y += clk-a20-gmac.o
8 obj-y += clk-mod0.o
9 obj-y += clk-sun8i-mbus.o
10 obj-y += clk-sun9i-core.o
11 obj-y += clk-sun9i-mmc.o
12 obj-y += clk-usb.o
15 clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
16 clk-sun8i-apb0.o
|
| D | clk-sun6i-ar100.c | 39 struct ar100_clk *clk = to_ar100_clk(hw); in ar100_recalc_rate() local
40 u32 val = readl(clk->reg); in ar100_recalc_rate()
53 int nparents = __clk_get_num_parents(hw->clk); in ar100_determine_rate()
62 struct clk *parent; in ar100_determine_rate()
66 parent = clk_get_parent_by_index(hw->clk, i); in ar100_determine_rate()
116 struct ar100_clk *clk = to_ar100_clk(hw); in ar100_set_parent() local
117 u32 val = readl(clk->reg); in ar100_set_parent()
124 writel(val, clk->reg); in ar100_set_parent()
131 struct ar100_clk *clk = to_ar100_clk(hw); in ar100_get_parent() local
132 return (readl(clk->reg) >> SUN6I_AR100_MUX_SHIFT) & in ar100_get_parent()
[all …]
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| /linux-4.1.27/drivers/clk/at91/ |
| D | clk-slow.c | 73 static struct clk *slow_clk;
121 static struct clk * __init
129 struct clk *clk = NULL; in at91_clk_register_slow_osc() local
153 clk = clk_register(NULL, &osc->hw); in at91_clk_register_slow_osc()
154 if (IS_ERR(clk)) in at91_clk_register_slow_osc()
157 return clk; in at91_clk_register_slow_osc()
163 struct clk *clk; in of_at91sam9x5_clk_slow_osc_setup() local
174 clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup, in of_at91sam9x5_clk_slow_osc_setup()
176 if (IS_ERR(clk)) in of_at91sam9x5_clk_slow_osc_setup()
179 of_clk_add_provider(np, of_clk_src_simple_get, clk); in of_at91sam9x5_clk_slow_osc_setup()
[all …]
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| D | Makefile | 6 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
7 obj-y += clk-system.o clk-peripheral.o clk-programmable.o
9 obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
10 obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
11 obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
12 obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
|
| D | clk-usb.c | 66 struct clk *parent = NULL; in at91sam9x5_clk_usb_determine_rate()
73 for (i = 0; i < __clk_get_num_parents(hw->clk); i++) { in at91sam9x5_clk_usb_determine_rate()
76 parent = clk_get_parent_by_index(hw->clk, i); in at91sam9x5_clk_usb_determine_rate()
199 static struct clk * __init
204 struct clk *clk = NULL; in at91sam9x5_clk_register_usb() local
221 clk = clk_register(NULL, &usb->hw); in at91sam9x5_clk_register_usb()
222 if (IS_ERR(clk)) in at91sam9x5_clk_register_usb()
225 return clk; in at91sam9x5_clk_register_usb()
228 static struct clk * __init
233 struct clk *clk = NULL; in at91sam9n12_clk_register_usb() local
[all …]
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| D | clk-main.c | 141 static struct clk * __init
150 struct clk *clk = NULL; in at91_clk_register_main_osc() local
183 clk = clk_register(NULL, &osc->hw); in at91_clk_register_main_osc()
184 if (IS_ERR(clk)) { in at91_clk_register_main_osc()
189 return clk; in at91_clk_register_main_osc()
195 struct clk *clk; in of_at91rm9200_clk_main_osc_setup() local
209 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); in of_at91rm9200_clk_main_osc_setup()
210 if (IS_ERR(clk)) in of_at91rm9200_clk_main_osc_setup()
213 of_clk_add_provider(np, of_clk_src_simple_get, clk); in of_at91rm9200_clk_main_osc_setup()
294 static struct clk * __init
[all …]
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| /linux-4.1.27/arch/arm/mach-shmobile/ |
| D | clock-sh73a0.c | 63 static struct clk r_clk = {
71 struct clk sh73a0_extal1_clk = {
79 struct clk sh73a0_extal2_clk = {
88 static struct clk main_clk = {
94 static unsigned long pll_recalc(struct clk *clk) in pll_recalc() argument
98 if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) { in pll_recalc()
99 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); in pll_recalc()
101 switch (clk->enable_bit) { in pll_recalc()
104 if (__raw_readl(clk->enable_reg) & (1 << 20)) in pll_recalc()
109 return clk->parent->rate * mult; in pll_recalc()
[all …]
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| D | clock-r8a7740.c | 70 static struct clk extalr_clk = {
78 static struct clk extal1_clk = {
86 static struct clk extal2_clk = {
94 static struct clk dv_clk = {
111 static struct clk system_clk = {
118 static struct clk r_clk = {
123 static unsigned long pllc01_recalc(struct clk *clk) in pllc01_recalc() argument
128 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1; in pllc01_recalc()
130 return clk->parent->rate * mult; in pllc01_recalc()
137 static struct clk pllc0_clk = {
[all …]
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| /linux-4.1.27/drivers/clk/pistachio/ |
| D | clk.c | 26 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
63 struct clk *clk; in pistachio_clk_register_gate() local
67 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, in pistachio_clk_register_gate()
71 p->clk_data.clks[gate[i].id] = clk; in pistachio_clk_register_gate()
79 struct clk *clk; in pistachio_clk_register_mux() local
83 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, in pistachio_clk_register_mux()
89 p->clk_data.clks[mux[i].id] = clk; in pistachio_clk_register_mux()
97 struct clk *clk; in pistachio_clk_register_div() local
101 clk = clk_register_divider(NULL, div[i].name, div[i].parent, in pistachio_clk_register_div()
105 p->clk_data.clks[div[i].id] = clk; in pistachio_clk_register_div()
[all …]
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| /linux-4.1.27/drivers/base/power/ |
| D | clock_ops.c | 31 struct clk *clk; member
45 ret = clk_enable(ce->clk); in __pm_clk_enable()
50 __func__, ce->clk, ret); in __pm_clk_enable()
61 if (!ce->clk) in pm_clk_acquire()
62 ce->clk = clk_get(dev, ce->con_id); in pm_clk_acquire()
63 if (IS_ERR(ce->clk)) { in pm_clk_acquire()
66 clk_prepare(ce->clk); in pm_clk_acquire()
73 struct clk *clk) in __pm_clk_add() argument
94 if (IS_ERR(clk) || !__clk_get(clk)) { in __pm_clk_add()
98 ce->clk = clk; in __pm_clk_add()
[all …]
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| /linux-4.1.27/include/media/ |
| D | v4l2-clk.h | 25 struct clk;
33 struct clk *clk; member
39 int (*enable)(struct v4l2_clk *clk);
40 void (*disable)(struct v4l2_clk *clk);
41 unsigned long (*get_rate)(struct v4l2_clk *clk);
42 int (*set_rate)(struct v4l2_clk *clk, unsigned long);
48 void v4l2_clk_unregister(struct v4l2_clk *clk);
50 void v4l2_clk_put(struct v4l2_clk *clk);
51 int v4l2_clk_enable(struct v4l2_clk *clk);
52 void v4l2_clk_disable(struct v4l2_clk *clk);
[all …]
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| /linux-4.1.27/drivers/clk/shmobile/ |
| D | Makefile | 1 obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2 obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
3 obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
4 obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
5 obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
6 obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
7 obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
8 obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
9 obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o
10 obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
[all …]
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| D | clk-emev2.c | 74 struct clk *clk; in emev2_smu_clkdiv_init() local
80 clk = clk_register_divider(NULL, np->name, parent_name, 0, in emev2_smu_clkdiv_init()
82 of_clk_add_provider(np, of_clk_src_simple_get, clk); in emev2_smu_clkdiv_init()
83 clk_register_clkdev(clk, np->name, NULL); in emev2_smu_clkdiv_init()
84 pr_debug("## %s %s %p\n", __func__, np->name, clk); in emev2_smu_clkdiv_init()
92 struct clk *clk; in emev2_smu_gclk_init() local
98 clk = clk_register_gate(NULL, np->name, parent_name, 0, in emev2_smu_gclk_init()
100 of_clk_add_provider(np, of_clk_src_simple_get, clk); in emev2_smu_gclk_init()
101 clk_register_clkdev(clk, np->name, NULL); in emev2_smu_gclk_init()
102 pr_debug("## %s %s %p\n", __func__, np->name, clk); in emev2_smu_gclk_init()
|
| D | clk-rcar-gen2.c | 138 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) in cpg_z_clk_register()
143 struct clk *clk; in cpg_z_clk_register() local
159 clk = clk_register(NULL, &zclk->hw); in cpg_z_clk_register()
160 if (IS_ERR(clk)) in cpg_z_clk_register()
163 return clk; in cpg_z_clk_register()
166 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg, in cpg_rcan_clk_register()
172 struct clk *clk; in cpg_rcan_clk_register() local
192 clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL, in cpg_rcan_clk_register()
195 if (IS_ERR(clk)) { in cpg_rcan_clk_register()
200 return clk; in cpg_rcan_clk_register()
[all …]
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| /linux-4.1.27/drivers/usb/host/ |
| D | ohci-st.c | 34 struct clk *clks[USB_MAX_CLKS];
35 struct clk *clk48;
52 int clk, ret; in st_ohci_platform_power_on() local
70 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ohci_platform_power_on()
71 ret = clk_prepare_enable(priv->clks[clk]); in st_ohci_platform_power_on()
89 while (--clk >= 0) in st_ohci_platform_power_on()
90 clk_disable_unprepare(priv->clks[clk]); in st_ohci_platform_power_on()
104 int clk; in st_ohci_platform_power_off() local
114 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) in st_ohci_platform_power_off()
115 if (priv->clks[clk]) in st_ohci_platform_power_off()
[all …]
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| D | ehci-st.c | 35 struct clk *clks[USB_MAX_CLKS];
36 struct clk *clk48;
76 int clk, ret; in st_ehci_platform_power_on() local
94 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { in st_ehci_platform_power_on()
95 ret = clk_prepare_enable(priv->clks[clk]); in st_ehci_platform_power_on()
113 while (--clk >= 0) in st_ehci_platform_power_on()
114 clk_disable_unprepare(priv->clks[clk]); in st_ehci_platform_power_on()
127 int clk; in st_ehci_platform_power_off() local
137 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) in st_ehci_platform_power_off()
138 if (priv->clks[clk]) in st_ehci_platform_power_off()
[all …]
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| D | ohci-platform.c | 39 struct clk *clks[OHCI_MAX_CLKS];
51 int clk, ret, phy_num; in ohci_platform_power_on() local
53 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ohci_platform_power_on()
54 ret = clk_prepare_enable(priv->clks[clk]); in ohci_platform_power_on()
82 while (--clk >= 0) in ohci_platform_power_on()
83 clk_disable_unprepare(priv->clks[clk]); in ohci_platform_power_on()
92 int clk, phy_num; in ohci_platform_power_off() local
101 for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--) in ohci_platform_power_off()
102 if (priv->clks[clk]) in ohci_platform_power_off()
103 clk_disable_unprepare(priv->clks[clk]); in ohci_platform_power_off()
[all …]
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| D | ehci-platform.c | 44 struct clk *clks[EHCI_MAX_CLKS];
82 int clk, ret, phy_num; in ehci_platform_power_on() local
84 for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) { in ehci_platform_power_on()
85 ret = clk_prepare_enable(priv->clks[clk]); in ehci_platform_power_on()
113 while (--clk >= 0) in ehci_platform_power_on()
114 clk_disable_unprepare(priv->clks[clk]); in ehci_platform_power_on()
123 int clk, phy_num; in ehci_platform_power_off() local
132 for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--) in ehci_platform_power_off()
133 if (priv->clks[clk]) in ehci_platform_power_off()
134 clk_disable_unprepare(priv->clks[clk]); in ehci_platform_power_off()
[all …]
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| /linux-4.1.27/arch/blackfin/mach-common/ |
| D | clock.h | 7 unsigned long (*get_rate)(struct clk *clk);
8 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
9 int (*set_rate)(struct clk *clk, unsigned long rate);
10 int (*enable)(struct clk *clk);
11 int (*disable)(struct clk *clk);
14 struct clk { struct
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| /linux-4.1.27/drivers/clocksource/ |
| D | arm_arch_timer.c | 80 struct clock_event_device *clk) in arch_timer_reg_write() argument
83 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
93 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
109 struct clock_event_device *clk) in arch_timer_reg_read() argument
114 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
124 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
185 struct clock_event_device *clk) in timer_set_mode() argument
191 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); in timer_set_mode()
193 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); in timer_set_mode()
201 struct clock_event_device *clk) in arch_timer_set_mode_virt() argument
[all …]
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| D | metag_generic.c | 115 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); in arch_timer_setup() local
126 clk->name = name; in arch_timer_setup()
127 clk->features = CLOCK_EVT_FEAT_ONESHOT, in arch_timer_setup()
129 clk->rating = 200, in arch_timer_setup()
130 clk->shift = 12, in arch_timer_setup()
131 clk->irq = tbisig_map(TBID_SIGNUM_TRT), in arch_timer_setup()
132 clk->set_mode = metag_timer_set_mode, in arch_timer_setup()
133 clk->set_next_event = metag_timer_set_next_event, in arch_timer_setup()
135 clk->mult = div_sc(hwtimer_freq, NSEC_PER_SEC, clk->shift); in arch_timer_setup()
136 clk->max_delta_ns = clockevent_delta2ns(0x7fffffff, clk); in arch_timer_setup()
[all …]
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| D | timer-sun5i.c | 42 struct clk *clk; member
183 struct clk *clk, int irq) in sun5i_setup_clocksource() argument
193 ret = clk_prepare_enable(clk); in sun5i_setup_clocksource()
199 rate = clk_get_rate(clk); in sun5i_setup_clocksource()
202 cs->timer.clk = clk; in sun5i_setup_clocksource()
206 ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb); in sun5i_setup_clocksource()
231 clk_notifier_unregister(clk, &cs->timer.clk_rate_cb); in sun5i_setup_clocksource()
233 clk_disable_unprepare(clk); in sun5i_setup_clocksource()
255 struct clk *clk, int irq) in sun5i_setup_clockevent() argument
266 ret = clk_prepare_enable(clk); in sun5i_setup_clockevent()
[all …]
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| D | time-efm32.c | 130 struct clk *clk; in efm32_clocksource_init() local
135 clk = of_clk_get(np, 0); in efm32_clocksource_init()
136 if (IS_ERR(clk)) { in efm32_clocksource_init()
137 ret = PTR_ERR(clk); in efm32_clocksource_init()
142 ret = clk_prepare_enable(clk); in efm32_clocksource_init()
148 rate = clk_get_rate(clk); in efm32_clocksource_init()
177 clk_disable_unprepare(clk); in efm32_clocksource_init()
180 clk_put(clk); in efm32_clocksource_init()
188 struct clk *clk; in efm32_clockevent_init() local
194 clk = of_clk_get(np, 0); in efm32_clockevent_init()
[all …]
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| D | time-armada-370-xp.c | 317 struct clk *clk = of_clk_get_by_name(np, "fixed"); in armada_xp_timer_init() local
320 BUG_ON(IS_ERR(clk)); in armada_xp_timer_init()
321 clk_prepare_enable(clk); in armada_xp_timer_init()
322 timer_clk = clk_get_rate(clk); in armada_xp_timer_init()
331 struct clk *clk; in armada_375_timer_init() local
333 clk = of_clk_get_by_name(np, "fixed"); in armada_375_timer_init()
334 if (!IS_ERR(clk)) { in armada_375_timer_init()
335 clk_prepare_enable(clk); in armada_375_timer_init()
336 timer_clk = clk_get_rate(clk); in armada_375_timer_init()
343 clk = of_clk_get(np, 0); in armada_375_timer_init()
[all …]
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| /linux-4.1.27/arch/unicore32/kernel/ |
| D | clock.c | 30 struct clk { struct
36 static struct clk clk_ost_clk = { argument
41 static struct clk clk_mclk_clk = {
45 static struct clk clk_bclk32_clk = {
49 static struct clk clk_ddr_clk = {
53 static struct clk clk_vga_clk = {
60 struct clk *clk_get(struct device *dev, const char *id) in clk_get()
62 struct clk *p, *clk = ERR_PTR(-ENOENT); in clk_get() local
67 clk = p; in clk_get()
73 return clk; in clk_get()
[all …]
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| /linux-4.1.27/arch/sh/kernel/cpu/sh3/ |
| D | clock-sh7710.c | 27 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
39 return clk->parent->rate / md_table[idx]; in module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
49 return clk->parent->rate / md_table[idx]; in bus_clk_recalc()
56 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
59 return clk->parent->rate / md_table[idx]; in cpu_clk_recalc()
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| D | clock-sh7705.c | 33 static void master_clk_init(struct clk *clk) in master_clk_init() argument
35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; in master_clk_init()
42 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
45 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
52 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
55 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
65 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7706.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; in master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
54 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
61 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
66 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7709.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; in master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
55 return clk->parent->rate * stc_multipliers[idx]; in bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
67 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh3.c | 29 static void master_clk_init(struct clk *clk) in master_clk_init() argument
34 clk->rate *= pfc_divisors[idx]; in master_clk_init()
41 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
46 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
53 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
58 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
65 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
70 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| /linux-4.1.27/arch/blackfin/include/asm/ |
| D | clocks.h | 54 unsigned long (*get_rate)(struct clk *clk);
55 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
56 int (*set_rate)(struct clk *clk, unsigned long rate);
57 int (*enable)(struct clk *clk);
58 int (*disable)(struct clk *clk);
61 struct clk { struct
62 struct clk *parent; argument
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| /linux-4.1.27/arch/sh/kernel/cpu/sh5/ |
| D | clock-sh5.c | 25 static void master_clk_init(struct clk *clk) in master_clk_init() argument
28 clk->rate *= ifc_table[idx]; in master_clk_init()
35 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
38 return clk->parent->rate / ifc_table[idx]; in module_clk_recalc()
45 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
48 return clk->parent->rate / ifc_table[idx]; in bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_table[idx]; in cpu_clk_recalc()
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| /linux-4.1.27/arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7201.c | 27 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate = 10000000 * pll2_mult * in master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
40 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
47 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
50 return clk->parent->rate / pfc_divisors[idx]; in bus_clk_recalc()
57 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
60 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7206.c | 27 static void master_clk_init(struct clk *clk) in master_clk_init() argument
29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) in module_clk_recalc() argument
39 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) in bus_clk_recalc() argument
48 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) in cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| D | clock-sh7269.c | 29 static struct clk r_clk = {
37 static struct clk extal_clk = {
41 static unsigned long pll_recalc(struct clk *clk) in pll_recalc() argument
43 return clk->parent->rate * PLL_RATE; in pll_recalc()
50 static struct clk pll_clk = {
56 static unsigned long peripheral0_recalc(struct clk *clk) in peripheral0_recalc() argument
58 return clk->parent->rate / 8; in peripheral0_recalc()
65 static struct clk peripheral0_clk = {
71 static unsigned long peripheral1_recalc(struct clk *clk) in peripheral1_recalc() argument
73 return clk->parent->rate / 4; in peripheral1_recalc()
[all …]
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| /linux-4.1.27/drivers/clk/st/ |
| D | clkgen-pll.c | 294 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); in recalc_stm_pll800c65()
319 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); in recalc_stm_pll1600c65()
341 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); in recalc_stm_pll3200c32()
368 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); in recalc_stm_pll1200c32()
393 static struct clk * __init clkgen_pll_register(const char *parent_name, in clkgen_pll_register()
399 struct clk *clk; in clkgen_pll_register() local
417 clk = clk_register(NULL, &pll->hw); in clkgen_pll_register()
418 if (IS_ERR(clk)) { in clkgen_pll_register()
420 return clk; in clkgen_pll_register()
424 __clk_get_name(clk), in clkgen_pll_register()
[all …]
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| /linux-4.1.27/drivers/clk/berlin/ |
| D | bg2.c | 95 static struct clk *clks[MAX_CLKS];
506 struct clk *clk; in berlin2_clock_setup() local
515 clk = of_clk_get_by_name(np, clk_names[REFCLK]); in berlin2_clock_setup()
516 if (!IS_ERR(clk)) { in berlin2_clock_setup()
517 clk_names[REFCLK] = __clk_get_name(clk); in berlin2_clock_setup()
518 clk_put(clk); in berlin2_clock_setup()
521 clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]); in berlin2_clock_setup()
522 if (!IS_ERR(clk)) { in berlin2_clock_setup()
523 clk_names[VIDEO_EXT0] = __clk_get_name(clk); in berlin2_clock_setup()
524 clk_put(clk); in berlin2_clock_setup()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| D | ctrl.c | 39 struct nvkm_clk *clk = nvkm_clk(object); in nvkm_control_mthd_pstate_info() local
49 if (clk) { in nvkm_control_mthd_pstate_info()
50 args->v0.count = clk->state_nr; in nvkm_control_mthd_pstate_info()
51 args->v0.ustate_ac = clk->ustate_ac; in nvkm_control_mthd_pstate_info()
52 args->v0.ustate_dc = clk->ustate_dc; in nvkm_control_mthd_pstate_info()
53 args->v0.pwrsrc = clk->pwrsrc; in nvkm_control_mthd_pstate_info()
54 args->v0.pstate = clk->pstate; in nvkm_control_mthd_pstate_info()
72 struct nvkm_clk *clk = nvkm_clk(object); in nvkm_control_mthd_pstate_attr() local
85 if (!clk) in nvkm_control_mthd_pstate_attr()
89 if (args->v0.state >= clk->state_nr) in nvkm_control_mthd_pstate_attr()
[all …]
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| /linux-4.1.27/drivers/clk/sirf/ |
| D | clk-common.c | 76 struct clk_pll *clk = to_pllclk(hw); in pll_clk_recalc_rate() local
77 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - in pll_clk_recalc_rate()
85 u32 cfg0 = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
128 struct clk_pll *clk = to_pllclk(hw); in pll_clk_set_rate() local
149 clkc_writel(reg, clk->regofs); in pll_clk_set_rate()
151 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
154 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
168 struct clk *parent_clk = clk_get_parent(hw->clk); in cpu_clk_round_rate()
169 struct clk *pll_parent_clk = clk_get_parent(parent_clk); in cpu_clk_round_rate()
181 struct clk *parent_clk = clk_get_parent(hw->clk); in cpu_clk_recalc_rate()
[all …]
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| /linux-4.1.27/sound/soc/pxa/ |
| D | raumfeld.c | 44 static void set_max9485_clk(char clk) in set_max9485_clk() argument
46 i2c_master_send(max9486_client, &clk, 1); in set_max9485_clk()
91 unsigned int clk = 0; in raumfeld_cs4270_hw_params() local
97 clk = 11289600; in raumfeld_cs4270_hw_params()
101 clk = 12288000; in raumfeld_cs4270_hw_params()
105 clk = 22579200; in raumfeld_cs4270_hw_params()
109 clk = 24576000; in raumfeld_cs4270_hw_params()
115 ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, 0); in raumfeld_cs4270_hw_params()
120 ret = snd_soc_dai_set_pll(cpu_dai, 0, 0, 0, clk); in raumfeld_cs4270_hw_params()
128 ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_EXT, clk, 1); in raumfeld_cs4270_hw_params()
[all …]
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| /linux-4.1.27/arch/m68k/include/asm/ |
| D | mcfclk.h | 9 struct clk;
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
16 struct clk { struct
24 extern struct clk *mcf_clks[]; argument
33 static struct clk __clk_##clk_bank##_##clk_slot = { \
40 void __clk_init_enabled(struct clk *);
41 void __clk_init_disabled(struct clk *);
44 static struct clk clk_##clk_ref = { \
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| /linux-4.1.27/drivers/clk/mxs/ |
| D | Makefile | 5 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
7 obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
8 obj-$(CONFIG_SOC_IMX28) += clk-imx28.o
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| /linux-4.1.27/arch/sh/kernel/cpu/ |
| D | clock-cpg.c | 8 static struct clk master_clk = {
13 static struct clk peripheral_clk = {
18 static struct clk bus_clk = {
23 static struct clk cpu_clk = {
31 static struct clk *onchip_clocks[] = {
51 struct clk *clk = onchip_clocks[i]; in cpg_clk_init() local
52 arch_init_clk_ops(&clk->ops, i); in cpg_clk_init()
53 if (clk->ops) in cpg_clk_init()
54 ret |= clk_register(clk); in cpg_clk_init()
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| /linux-4.1.27/drivers/memory/ |
| D | atmel-sdramc.c | 57 struct clk *clk; in atmel_ramc_probe() local
63 clk = devm_clk_get(&pdev->dev, "ddrck"); in atmel_ramc_probe()
64 if (IS_ERR(clk)) in atmel_ramc_probe()
65 return PTR_ERR(clk); in atmel_ramc_probe()
66 clk_prepare_enable(clk); in atmel_ramc_probe()
70 clk = devm_clk_get(&pdev->dev, "mpddr"); in atmel_ramc_probe()
71 if (IS_ERR(clk)) { in atmel_ramc_probe()
73 return PTR_ERR(clk); in atmel_ramc_probe()
75 clk_prepare_enable(clk); in atmel_ramc_probe()
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| /linux-4.1.27/drivers/clk/keystone/ |
| D | pll.c | 125 static struct clk *clk_register_pll(struct device *dev, in clk_register_pll()
132 struct clk *clk; in clk_register_pll() local
147 clk = clk_register(NULL, &pll->hw); in clk_register_pll()
148 if (IS_ERR(clk)) in clk_register_pll()
151 return clk; in clk_register_pll()
167 struct clk *clk; in _of_pll_clk_init() local
216 clk = clk_register_pll(NULL, node->name, parent_name, pll_data); in _of_pll_clk_init()
217 if (clk) { in _of_pll_clk_init()
218 of_clk_add_provider(node, of_clk_src_simple_get, clk); in _of_pll_clk_init()
258 struct clk *clk; in of_pll_div_clk_init() local
[all …]
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| /linux-4.1.27/Documentation/ |
| D | clk.txt | 4 This document endeavours to explain the common clk framework details,
6 detailed explanation of the clock api in include/linux/clk.h, but
11 The common clk framework is an interface to control the clock nodes
18 clk which unifies the framework-level accounting and infrastructure that
20 is a common implementation of the clk.h api, defined in
21 drivers/clk/clk.c. Finally there is struct clk_ops, whose operations
22 are invoked by the clk api implementation.
34 is defined in struct clk_foo and pointed to within struct clk. This
40 Below is the common struct clk definition from
41 include/linux/clk-private.h, modified for brevity:
[all …]
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| /linux-4.1.27/drivers/pwm/ |
| D | pwm-fsl-ftm.c | 91 struct clk *clk[FSL_PWM_CLK_MAX]; member
103 return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_request()
110 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_free()
119 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); in fsl_pwm_calculate_default_ps()
123 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); in fsl_pwm_calculate_default_ps()
153 c = clk_get_rate(fpc->clk[fpc->cnt_select]); in fsl_pwm_calculate_cycles()
197 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); in fsl_pwm_calculate_period()
198 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); in fsl_pwm_calculate_period()
310 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); in fsl_counter_clock_enable()
314 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); in fsl_counter_clock_enable()
[all …]
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