19 static unsigned int sh_clk_read(struct clk *clk)  in sh_clk_read()  argument
21 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_read()
22 		return ioread8(clk->mapped_reg);  in sh_clk_read()
23 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_read()
24 		return ioread16(clk->mapped_reg);  in sh_clk_read()
26 	return ioread32(clk->mapped_reg);  in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk)  in sh_clk_write()  argument
31 	if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_write()
32 		iowrite8(value, clk->mapped_reg);  in sh_clk_write()
33 	else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_write()
34 		iowrite16(value, clk->mapped_reg);  in sh_clk_write()
36 		iowrite32(value, clk->mapped_reg);  in sh_clk_write()
54 static int sh_clk_mstp_enable(struct clk *clk)  in sh_clk_mstp_enable()  argument
56 	sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);  in sh_clk_mstp_enable()
57 	if (clk->status_reg) {  in sh_clk_mstp_enable()
60 		void __iomem *mapped_status = (phys_addr_t)clk->status_reg -  in sh_clk_mstp_enable()
61 			(phys_addr_t)clk->enable_reg + clk->mapped_reg;  in sh_clk_mstp_enable()
63 		if (clk->flags & CLK_ENABLE_REG_8BIT)  in sh_clk_mstp_enable()
65 		else if (clk->flags & CLK_ENABLE_REG_16BIT)  in sh_clk_mstp_enable()
71 		     (read(mapped_status) & (1 << clk->enable_bit)) && i;  in sh_clk_mstp_enable()
76 			       clk->enable_reg, clk->enable_bit);  in sh_clk_mstp_enable()
83 static void sh_clk_mstp_disable(struct clk *clk)  in sh_clk_mstp_disable()  argument
85 	sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk);  in sh_clk_mstp_disable()
94 int __init sh_clk_mstp_register(struct clk *clks, int nr)  in sh_clk_mstp_register()
96 	struct clk *clkp;  in sh_clk_mstp_register()
112 static inline struct clk_div_table *clk_to_div_table(struct clk *clk)  in clk_to_div_table()  argument
114 	return clk->priv;  in clk_to_div_table()
117 static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)  in clk_to_div_mult_table()  argument
119 	return clk_to_div_table(clk)->div_mult_table;  in clk_to_div_mult_table()
125 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)  in sh_clk_div_round_rate()  argument
127 	return clk_rate_table_round(clk, clk->freq_table, rate);  in sh_clk_div_round_rate()
130 static unsigned long sh_clk_div_recalc(struct clk *clk)  in sh_clk_div_recalc()  argument
132 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);  in sh_clk_div_recalc()
135 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div_recalc()
136 			     table, clk->arch_flags ? &clk->arch_flags : NULL);  in sh_clk_div_recalc()
138 	idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;  in sh_clk_div_recalc()
140 	return clk->freq_table[idx].frequency;  in sh_clk_div_recalc()
143 static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)  in sh_clk_div_set_rate()  argument
145 	struct clk_div_table *dt = clk_to_div_table(clk);  in sh_clk_div_set_rate()
149 	idx = clk_rate_table_find(clk, clk->freq_table, rate);  in sh_clk_div_set_rate()
153 	value = sh_clk_read(clk);  in sh_clk_div_set_rate()
154 	value &= ~(clk->div_mask << clk->enable_bit);  in sh_clk_div_set_rate()
155 	value |= (idx << clk->enable_bit);  in sh_clk_div_set_rate()
156 	sh_clk_write(value, clk);  in sh_clk_div_set_rate()
160 		dt->kick(clk);  in sh_clk_div_set_rate()
165 static int sh_clk_div_enable(struct clk *clk)  in sh_clk_div_enable()  argument
167 	if (clk->div_mask == SH_CLK_DIV6_MSK) {  in sh_clk_div_enable()
168 		int ret = sh_clk_div_set_rate(clk, clk->rate);  in sh_clk_div_enable()
173 	sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);  in sh_clk_div_enable()
177 static void sh_clk_div_disable(struct clk *clk)  in sh_clk_div_disable()  argument
181 	val = sh_clk_read(clk);  in sh_clk_div_disable()
189 	if (clk->flags & CLK_MASK_DIV_ON_DISABLE)  in sh_clk_div_disable()
190 		val |= clk->div_mask;  in sh_clk_div_disable()
192 	sh_clk_write(val, clk);  in sh_clk_div_disable()
209 static int __init sh_clk_init_parent(struct clk *clk)  in sh_clk_init_parent()  argument
213 	if (clk->parent)  in sh_clk_init_parent()
216 	if (!clk->parent_table || !clk->parent_num)  in sh_clk_init_parent()
219 	if (!clk->src_width) {  in sh_clk_init_parent()
224 	val  = (sh_clk_read(clk) >> clk->src_shift);  in sh_clk_init_parent()
225 	val &= (1 << clk->src_width) - 1;  in sh_clk_init_parent()
227 	if (val >= clk->parent_num) {  in sh_clk_init_parent()
232 	clk_reparent(clk, clk->parent_table[val]);  in sh_clk_init_parent()
233 	if (!clk->parent) {  in sh_clk_init_parent()
241 static int __init sh_clk_div_register_ops(struct clk *clks, int nr,  in sh_clk_div_register_ops()
244 	struct clk *clkp;  in sh_clk_div_register_ops()
294 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)  in sh_clk_div6_set_parent()  argument
296 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);  in sh_clk_div6_set_parent()
300 	if (!clk->parent_table || !clk->parent_num)  in sh_clk_div6_set_parent()
304 	for (i = 0; i < clk->parent_num; i++)  in sh_clk_div6_set_parent()
305 		if (clk->parent_table[i] == parent)  in sh_clk_div6_set_parent()
308 	if (i == clk->parent_num)  in sh_clk_div6_set_parent()
311 	ret = clk_reparent(clk, parent);  in sh_clk_div6_set_parent()
315 	value = sh_clk_read(clk) &  in sh_clk_div6_set_parent()
316 		~(((1 << clk->src_width) - 1) << clk->src_shift);  in sh_clk_div6_set_parent()
318 	sh_clk_write(value | (i << clk->src_shift), clk);  in sh_clk_div6_set_parent()
321 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div6_set_parent()
336 int __init sh_clk_div6_register(struct clk *clks, int nr)  in sh_clk_div6_register()
342 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)  in sh_clk_div6_reparent_register()
351 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)  in sh_clk_div4_set_parent()  argument
353 	struct clk_div_mult_table *table = clk_to_div_mult_table(clk);  in sh_clk_div4_set_parent()
363 		value = sh_clk_read(clk) & ~(1 << 7);  in sh_clk_div4_set_parent()
365 		value = sh_clk_read(clk) | (1 << 7);  in sh_clk_div4_set_parent()
367 	ret = clk_reparent(clk, parent);  in sh_clk_div4_set_parent()
371 	sh_clk_write(value, clk);  in sh_clk_div4_set_parent()
374 	clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,  in sh_clk_div4_set_parent()
375 			     table, &clk->arch_flags);  in sh_clk_div4_set_parent()
389 int __init sh_clk_div4_register(struct clk *clks, int nr,  in sh_clk_div4_register()
395 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,  in sh_clk_div4_enable_register()
402 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,  in sh_clk_div4_reparent_register()
410 static unsigned long fsidiv_recalc(struct clk *clk)  in fsidiv_recalc()  argument
414 	value = __raw_readl(clk->mapping->base);  in fsidiv_recalc()
418 		return clk->parent->rate;  in fsidiv_recalc()
420 	return clk->parent->rate / value;  in fsidiv_recalc()
423 static long fsidiv_round_rate(struct clk *clk, unsigned long rate)  in fsidiv_round_rate()  argument
425 	return clk_rate_div_range_round(clk, 1, 0xffff, rate);  in fsidiv_round_rate()
428 static void fsidiv_disable(struct clk *clk)  in fsidiv_disable()  argument
430 	__raw_writel(0, clk->mapping->base);  in fsidiv_disable()
433 static int fsidiv_enable(struct clk *clk)  in fsidiv_enable()  argument
437 	value  = __raw_readl(clk->mapping->base) >> 16;  in fsidiv_enable()
441 	__raw_writel((value << 16) | 0x3, clk->mapping->base);  in fsidiv_enable()
446 static int fsidiv_set_rate(struct clk *clk, unsigned long rate)  in fsidiv_set_rate()  argument
450 	idx = (clk->parent->rate / rate) & 0xffff;  in fsidiv_set_rate()
452 		__raw_writel(0, clk->mapping->base);  in fsidiv_set_rate()
454 		__raw_writel(idx << 16, clk->mapping->base);  in fsidiv_set_rate()
467 int __init sh_clk_fsidiv_register(struct clk *clks, int nr)  in sh_clk_fsidiv_register()