91 	struct clk *clk[FSL_PWM_CLK_MAX];  member
103 	return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_request()
110 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_free()
119 	sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_calculate_default_ps()
123 	cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]);  in fsl_pwm_calculate_default_ps()
153 	c = clk_get_rate(fpc->clk[fpc->cnt_select]);  in fsl_pwm_calculate_cycles()
197 	fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);  in fsl_pwm_calculate_period()
198 	ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);  in fsl_pwm_calculate_period()
310 	ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_enable()
314 	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_counter_clock_enable()
316 		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_enable()
352 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_counter_clock_disable()
353 	clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_counter_clock_disable()
388 	ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_init()
396 	clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_init()
447 	fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");  in fsl_pwm_probe()
448 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {  in fsl_pwm_probe()
450 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_probe()
453 	fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");  in fsl_pwm_probe()
454 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))  in fsl_pwm_probe()
455 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);  in fsl_pwm_probe()
457 	fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");  in fsl_pwm_probe()
458 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))  in fsl_pwm_probe()
459 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);  in fsl_pwm_probe()
461 	fpc->clk[FSL_PWM_CLK_CNTEN] =  in fsl_pwm_probe()
463 	if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))  in fsl_pwm_probe()
464 		return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_probe()
503 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_suspend()
504 		clk_disable_unprepare(fpc->clk[fpc->cnt_select]);  in fsl_pwm_suspend()
505 		clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_suspend()
519 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]);  in fsl_pwm_resume()
520 		clk_prepare_enable(fpc->clk[fpc->cnt_select]);  in fsl_pwm_resume()
521 		clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);  in fsl_pwm_resume()