Lines Matching refs:clk
20 clk_sysin: clk-sysin {
32 clk_s_a0_pll: clk-s-a0-pll {
38 clock-output-names = "clk-s-a0-pll0-hs",
39 "clk-s-a0-pll0-ls",
40 "clk-s-a0-pll1";
43 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
50 clock-output-names = "clk-s-a0-osc-prediv";
53 clk_s_a0_hs: clk-s-a0-hs {
62 clock-output-names = "clk-s-fdma-0",
63 "clk-s-fdma-1",
64 ""; /* clk-s-jit-sense */
68 clk_s_a0_ls: clk-s-a0-ls {
77 clock-output-names = "clk-s-icn-reg-0",
78 "clk-s-icn-if-0",
79 "clk-s-icn-reg-lp-0",
80 "clk-s-emiss",
81 "clk-s-eth1-phy",
82 "clk-s-mii-ref-out";
90 clk_s_a1_pll: clk-s-a1-pll {
96 clock-output-names = "clk-s-a1-pll0-hs",
97 "clk-s-a1-pll0-ls",
98 "clk-s-a1-pll1";
101 clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
108 clock-output-names = "clk-s-a1-osc-prediv";
111 clk_s_a1_hs: clk-s-a1-hs {
122 "clk-s-stac-phy",
123 "clk-s-vtac-tx-phy";
126 clk_s_a1_ls: clk-s-a1-ls {
135 clock-output-names = "clk-s-icn-if-2",
136 "clk-s-card-mmc",
137 "clk-s-icn-if-1",
138 "clk-s-gmac0-phy",
139 "clk-s-nand-ctrl",
141 "clk-s-mii0-ref-out",
142 ""; /* clk-s-stac-sys */
153 clk_m_a0_pll0: clk-m-a0-pll0 {
159 clock-output-names = "clk-m-a0-pll0-phi0",
160 "clk-m-a0-pll0-phi1",
161 "clk-m-a0-pll0-phi2",
162 "clk-m-a0-pll0-phi3";
165 clk_m_a0_pll1: clk-m-a0-pll1 {
171 clock-output-names = "clk-m-a0-pll1-phi0",
172 "clk-m-a0-pll1-phi1",
173 "clk-m-a0-pll1-phi2",
174 "clk-m-a0-pll1-phi3";
177 clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
184 clock-output-names = "clk-m-a0-osc-prediv";
187 clk_m_a0_div0: clk-m-a0-div0 {
196 clock-output-names = "clk-m-apb-pm", /* Unused */
200 "clk-m-pp-dmu-0",
201 "clk-m-pp-dmu-1",
202 "clk-m-icm-disp",
206 clk_m_a0_div1: clk-m-a0-div1 {
217 "clk-m-a9-ext2f",
218 "clk-m-st40rt",
219 "clk-m-st231-dmu-0",
220 "clk-m-st231-dmu-1",
221 "clk-m-st231-aud",
222 "clk-m-st231-gp-0";
225 clk_m_a0_div2: clk-m-a0-div2 {
234 clock-output-names = "clk-m-st231-gp-1",
235 "clk-m-icn-cpu",
236 "clk-m-icn-stac",
237 "clk-m-icn-dmu-0",
238 "clk-m-icn-dmu-1",
244 clk_m_a0_div3: clk-m-a0-div3 {
259 "clk-m-icn-eram",
260 "clk-m-a9-trace";
267 clk_m_a1_pll0: clk-m-a1-pll0 {
273 clock-output-names = "clk-m-a1-pll0-phi0",
274 "clk-m-a1-pll0-phi1",
275 "clk-m-a1-pll0-phi2",
276 "clk-m-a1-pll0-phi3";
279 clk_m_a1_pll1: clk-m-a1-pll1 {
285 clock-output-names = "clk-m-a1-pll1-phi0",
286 "clk-m-a1-pll1-phi1",
287 "clk-m-a1-pll1-phi2",
288 "clk-m-a1-pll1-phi3";
291 clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
298 clock-output-names = "clk-m-a1-osc-prediv";
301 clk_m_a1_div0: clk-m-a1-div0 {
310 clock-output-names = "clk-m-fdma-12",
311 "clk-m-fdma-10",
312 "clk-m-fdma-11",
313 "clk-m-hva-lmi",
314 "clk-m-proc-sc",
315 "clk-m-tp",
316 "clk-m-icn-gpu",
317 "clk-m-icn-vdp-0";
320 clk_m_a1_div1: clk-m-a1-div1 {
329 clock-output-names = "clk-m-icn-vdp-1",
330 "clk-m-icn-vdp-2",
331 "clk-m-icn-vdp-3",
332 "clk-m-prv-t1-bus",
333 "clk-m-icn-vdp-4",
334 "clk-m-icn-reg-10",
336 ""; /* clk-m-icn-st231 */
339 clk_m_a1_div2: clk-m-a1-div2 {
348 clock-output-names = "clk-m-fvdp-proc-alt",
358 clk_m_a1_div3: clk-m-a1-div3 {
378 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
389 clk_m_a2_pll0: clk-m-a2-pll0 {
395 clock-output-names = "clk-m-a2-pll0-phi0",
396 "clk-m-a2-pll0-phi1",
397 "clk-m-a2-pll0-phi2",
398 "clk-m-a2-pll0-phi3";
401 clk_m_a2_pll1: clk-m-a2-pll1 {
407 clock-output-names = "clk-m-a2-pll1-phi0",
408 "clk-m-a2-pll1-phi1",
409 "clk-m-a2-pll1-phi2",
410 "clk-m-a2-pll1-phi3";
413 clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
420 clock-output-names = "clk-m-a2-osc-prediv";
423 clk_m_a2_div0: clk-m-a2-div0 {
432 clock-output-names = "clk-m-vtac-main-phy",
433 "clk-m-vtac-aux-phy",
434 "clk-m-stac-phy",
435 "clk-m-stac-sys",
436 "", /* clk-m-mpestac-pg */
437 "", /* clk-m-mpestac-wc */
438 "", /* clk-m-mpevtacaux-pg*/
439 ""; /* clk-m-mpevtacmain-pg*/
442 clk_m_a2_div1: clk-m-a2-div1 {
451 clock-output-names = "", /* clk-m-mpevtacrx0-wc */
452 "", /* clk-m-mpevtacrx1-wc */
453 "clk-m-compo-main",
454 "clk-m-compo-aux",
455 "clk-m-bdisp-0",
456 "clk-m-bdisp-1",
457 "clk-m-icn-bdisp-0",
458 "clk-m-icn-bdisp-1";
461 clk_m_a2_div2: clk-m-a2-div2 {
470 clock-output-names = "", /* clk-m-icn-hqvdp0 */
471 "", /* clk-m-icn-hqvdp1 */
472 "clk-m-icn-compo",
473 "", /* clk-m-icn-vdpaux */
474 "clk-m-icn-ts",
475 "clk-m-icn-reg-lp-10",
476 "clk-m-dcephy-impctrl",
480 clk_m_a2_div3: clk-m-a2-div3 {
512 clk_m_a9: clk-m-a9@fdde00d8 {
525 arm_periph_clk: clk-m-a9-periphs {