43 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)  in _omap3_dpll_write_clken()  argument
48 	dd = clk->dpll_data;  in _omap3_dpll_write_clken()
50 	v = omap2_clk_readl(clk, dd->control_reg);  in _omap3_dpll_write_clken()
53 	omap2_clk_writel(v, clk, dd->control_reg);  in _omap3_dpll_write_clken()
57 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)  in _omap3_wait_dpll_status()  argument
64 	dd = clk->dpll_data;  in _omap3_wait_dpll_status()
65 	clk_name = __clk_get_name(clk->hw.clk);  in _omap3_wait_dpll_status()
69 	while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)  in _omap3_wait_dpll_status()
89 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)  in _omap3_dpll_compute_freqsel()  argument
94 	fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;  in _omap3_dpll_compute_freqsel()
134 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)  in _omap3_noncore_dpll_lock()  argument
141 	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));  in _omap3_noncore_dpll_lock()
143 	dd = clk->dpll_data;  in _omap3_noncore_dpll_lock()
147 	if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)  in _omap3_noncore_dpll_lock()
150 	ai = omap3_dpll_autoidle_read(clk);  in _omap3_noncore_dpll_lock()
153 		omap3_dpll_deny_idle(clk);  in _omap3_noncore_dpll_lock()
155 	_omap3_dpll_write_clken(clk, DPLL_LOCKED);  in _omap3_noncore_dpll_lock()
157 	r = _omap3_wait_dpll_status(clk, 1);  in _omap3_noncore_dpll_lock()
160 		omap3_dpll_allow_idle(clk);  in _omap3_noncore_dpll_lock()
179 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)  in _omap3_noncore_dpll_bypass()  argument
184 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))  in _omap3_noncore_dpll_bypass()
188 		 __clk_get_name(clk->hw.clk));  in _omap3_noncore_dpll_bypass()
190 	ai = omap3_dpll_autoidle_read(clk);  in _omap3_noncore_dpll_bypass()
192 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);  in _omap3_noncore_dpll_bypass()
194 	r = _omap3_wait_dpll_status(clk, 0);  in _omap3_noncore_dpll_bypass()
197 		omap3_dpll_allow_idle(clk);  in _omap3_noncore_dpll_bypass()
211 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)  in _omap3_noncore_dpll_stop()  argument
215 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))  in _omap3_noncore_dpll_stop()
218 	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));  in _omap3_noncore_dpll_stop()
220 	ai = omap3_dpll_autoidle_read(clk);  in _omap3_noncore_dpll_stop()
222 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);  in _omap3_noncore_dpll_stop()
225 		omap3_dpll_allow_idle(clk);  in _omap3_noncore_dpll_stop()
242 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)  in _lookup_dco()  argument
246 	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));  in _lookup_dco()
267 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)  in _lookup_sddiv()  argument
272 	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));  in _lookup_sddiv()
297 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)  in omap3_noncore_dpll_program()  argument
299 	struct dpll_data *dd = clk->dpll_data;  in omap3_noncore_dpll_program()
304 	_omap3_noncore_dpll_bypass(clk);  in omap3_noncore_dpll_program()
311 		v = omap2_clk_readl(clk, dd->control_reg);  in omap3_noncore_dpll_program()
314 		omap2_clk_writel(v, clk, dd->control_reg);  in omap3_noncore_dpll_program()
318 	v = omap2_clk_readl(clk, dd->mult_div1_reg);  in omap3_noncore_dpll_program()
334 		_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);  in omap3_noncore_dpll_program()
339 		_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,  in omap3_noncore_dpll_program()
345 	omap2_clk_writel(v, clk, dd->mult_div1_reg);  in omap3_noncore_dpll_program()
349 		v = omap2_clk_readl(clk, dd->control_reg);  in omap3_noncore_dpll_program()
365 		omap2_clk_writel(v, clk, dd->control_reg);  in omap3_noncore_dpll_program()
372 	_omap3_noncore_dpll_lock(clk);  in omap3_noncore_dpll_program()
387 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap3_dpll_recalc()  local
389 	return omap2_get_dpll_rate(clk);  in omap3_dpll_recalc()
410 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap3_noncore_dpll_enable()  local
415 	dd = clk->dpll_data;  in omap3_noncore_dpll_enable()
419 	if (clk->clkdm) {  in omap3_noncore_dpll_enable()
420 		r = clkdm_clk_enable(clk->clkdm, hw->clk);  in omap3_noncore_dpll_enable()
424 			     __func__, __clk_get_name(hw->clk),  in omap3_noncore_dpll_enable()
425 			     clk->clkdm->name, r);  in omap3_noncore_dpll_enable()
430 	parent = __clk_get_hw(__clk_get_parent(hw->clk));  in omap3_noncore_dpll_enable()
432 	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {  in omap3_noncore_dpll_enable()
434 		r = _omap3_noncore_dpll_bypass(clk);  in omap3_noncore_dpll_enable()
437 		r = _omap3_noncore_dpll_lock(clk);  in omap3_noncore_dpll_enable()
452 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap3_noncore_dpll_disable()  local
454 	_omap3_noncore_dpll_stop(clk);  in omap3_noncore_dpll_disable()
455 	if (clk->clkdm)  in omap3_noncore_dpll_disable()
456 		clkdm_clk_disable(clk->clkdm, hw->clk);  in omap3_noncore_dpll_disable()
481 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap3_noncore_dpll_determine_rate()  local
487 	dd = clk->dpll_data;  in omap3_noncore_dpll_determine_rate()
514 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap3_noncore_dpll_set_parent()  local
521 		ret = _omap3_noncore_dpll_bypass(clk);  in omap3_noncore_dpll_set_parent()
523 		ret = _omap3_noncore_dpll_lock(clk);  in omap3_noncore_dpll_set_parent()
542 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);  in omap3_noncore_dpll_set_rate()  local
550 	dd = clk->dpll_data;  in omap3_noncore_dpll_set_rate()
554 	if (__clk_get_hw(__clk_get_parent(hw->clk)) !=  in omap3_noncore_dpll_set_rate()
563 		freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);  in omap3_noncore_dpll_set_rate()
568 		 __clk_get_name(hw->clk), rate);  in omap3_noncore_dpll_set_rate()
570 	ret = omap3_noncore_dpll_program(clk, freqsel);  in omap3_noncore_dpll_set_rate()
621 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)  in omap3_dpll_autoidle_read()  argument
626 	if (!clk || !clk->dpll_data)  in omap3_dpll_autoidle_read()
629 	dd = clk->dpll_data;  in omap3_dpll_autoidle_read()
634 	v = omap2_clk_readl(clk, dd->autoidle_reg);  in omap3_dpll_autoidle_read()
650 void omap3_dpll_allow_idle(struct clk_hw_omap *clk)  in omap3_dpll_allow_idle()  argument
655 	if (!clk || !clk->dpll_data)  in omap3_dpll_allow_idle()
658 	dd = clk->dpll_data;  in omap3_dpll_allow_idle()
668 	v = omap2_clk_readl(clk, dd->autoidle_reg);  in omap3_dpll_allow_idle()
671 	omap2_clk_writel(v, clk, dd->autoidle_reg);  in omap3_dpll_allow_idle()
681 void omap3_dpll_deny_idle(struct clk_hw_omap *clk)  in omap3_dpll_deny_idle()  argument
686 	if (!clk || !clk->dpll_data)  in omap3_dpll_deny_idle()
689 	dd = clk->dpll_data;  in omap3_dpll_deny_idle()
694 	v = omap2_clk_readl(clk, dd->autoidle_reg);  in omap3_dpll_deny_idle()
697 	omap2_clk_writel(v, clk, dd->autoidle_reg);  in omap3_dpll_deny_idle()
707 	struct clk *parent;  in omap3_find_clkoutx2_dpll()
712 			parent = __clk_get_parent(hw->clk);  in omap3_find_clkoutx2_dpll()
714 		} while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));  in omap3_find_clkoutx2_dpll()
790 		*prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);  in omap3_clkoutx2_round_rate()
803 	if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {  in omap3_clkoutx2_round_rate()
807 		*prate = __clk_round_rate(__clk_get_parent(hw->clk),  in omap3_clkoutx2_round_rate()