Lines Matching refs:clk
167 static struct clk **clks;
638 struct clk *clk; in tegra20_pll_init() local
641 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
643 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
646 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", in tegra20_pll_init()
649 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", in tegra20_pll_init()
652 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
655 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
658 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
661 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", in tegra20_pll_init()
664 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", in tegra20_pll_init()
667 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; in tegra20_pll_init()
670 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
672 clks[TEGRA20_CLK_PLL_X] = clk; in tegra20_pll_init()
675 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
677 clks[TEGRA20_CLK_PLL_U] = clk; in tegra20_pll_init()
680 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
682 clks[TEGRA20_CLK_PLL_D] = clk; in tegra20_pll_init()
685 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", in tegra20_pll_init()
687 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
690 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, in tegra20_pll_init()
692 clks[TEGRA20_CLK_PLL_A] = clk; in tegra20_pll_init()
695 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", in tegra20_pll_init()
698 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", in tegra20_pll_init()
701 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
704 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
706 clks[TEGRA20_CLK_PLL_E] = clk; in tegra20_pll_init()
718 struct clk *clk; in tegra20_super_clk_init() local
721 clk = tegra_clk_register_super_mux("cclk", cclk_parents, in tegra20_super_clk_init()
724 clks[TEGRA20_CLK_CCLK] = clk; in tegra20_super_clk_init()
727 clk = tegra_clk_register_super_mux("sclk", sclk_parents, in tegra20_super_clk_init()
730 clks[TEGRA20_CLK_SCLK] = clk; in tegra20_super_clk_init()
733 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); in tegra20_super_clk_init()
734 clks[TEGRA20_CLK_TWD] = clk; in tegra20_super_clk_init()
743 struct clk *clk; in tegra20_audio_clk_init() local
746 clk = clk_register_mux(NULL, "audio_mux", audio_parents, in tegra20_audio_clk_init()
750 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, in tegra20_audio_clk_init()
753 clks[TEGRA20_CLK_AUDIO] = clk; in tegra20_audio_clk_init()
756 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", in tegra20_audio_clk_init()
758 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", in tegra20_audio_clk_init()
762 clks[TEGRA20_CLK_AUDIO_2X] = clk; in tegra20_audio_clk_init()
805 struct clk *clk; in tegra20_periph_clk_init() local
809 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", in tegra20_periph_clk_init()
812 clks[TEGRA20_CLK_AC97] = clk; in tegra20_periph_clk_init()
815 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, in tegra20_periph_clk_init()
817 clks[TEGRA20_CLK_APBDMA] = clk; in tegra20_periph_clk_init()
820 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, in tegra20_periph_clk_init()
825 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, in tegra20_periph_clk_init()
827 clks[TEGRA20_CLK_EMC] = clk; in tegra20_periph_clk_init()
829 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, in tegra20_periph_clk_init()
831 clks[TEGRA20_CLK_MC] = clk; in tegra20_periph_clk_init()
834 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
836 clk_register_clkdev(clk, NULL, "dsi"); in tegra20_periph_clk_init()
837 clks[TEGRA20_CLK_DSI] = clk; in tegra20_periph_clk_init()
840 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
842 clks[TEGRA20_CLK_PEX] = clk; in tegra20_periph_clk_init()
845 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, in tegra20_periph_clk_init()
847 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, in tegra20_periph_clk_init()
849 clks[TEGRA20_CLK_CDEV1] = clk; in tegra20_periph_clk_init()
852 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, in tegra20_periph_clk_init()
854 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, in tegra20_periph_clk_init()
856 clks[TEGRA20_CLK_CDEV2] = clk; in tegra20_periph_clk_init()
860 clk = tegra_clk_register_periph(data->name, data->p.parent_names, in tegra20_periph_clk_init()
863 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
868 clk = tegra_clk_register_periph_nodiv(data->name, in tegra20_periph_clk_init()
872 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
880 struct clk *clk; in tegra20_osc_clk_init() local
887 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | in tegra20_osc_clk_init()
889 clks[TEGRA20_CLK_CLK_M] = clk; in tegra20_osc_clk_init()
893 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", in tegra20_osc_clk_init()
895 clks[TEGRA20_CLK_PLL_REF] = clk; in tegra20_osc_clk_init()