Lines Matching refs:clk
105 struct clk clk; member
110 struct clk clk; member
116 struct clk clk; member
159 static int jz_clk_enable_gating(struct clk *clk) in jz_clk_enable_gating() argument
161 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) in jz_clk_enable_gating()
164 jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); in jz_clk_enable_gating()
168 static int jz_clk_disable_gating(struct clk *clk) in jz_clk_disable_gating() argument
170 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) in jz_clk_disable_gating()
173 jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); in jz_clk_disable_gating()
177 static int jz_clk_is_enabled_gating(struct clk *clk) in jz_clk_is_enabled_gating() argument
179 if (clk->gate_bit == JZ4740_CLK_NOT_GATED) in jz_clk_is_enabled_gating()
182 return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit); in jz_clk_is_enabled_gating()
185 static unsigned long jz_clk_static_get_rate(struct clk *clk) in jz_clk_static_get_rate() argument
187 return ((struct static_clk *)clk)->rate; in jz_clk_static_get_rate()
190 static int jz_clk_ko_enable(struct clk *clk) in jz_clk_ko_enable() argument
196 static int jz_clk_ko_disable(struct clk *clk) in jz_clk_ko_disable() argument
202 static int jz_clk_ko_is_enabled(struct clk *clk) in jz_clk_ko_is_enabled() argument
209 static unsigned long jz_clk_pll_get_rate(struct clk *clk) in jz_clk_pll_get_rate() argument
219 return clk_get_rate(clk->parent); in jz_clk_pll_get_rate()
225 return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; in jz_clk_pll_get_rate()
228 static unsigned long jz_clk_pll_half_get_rate(struct clk *clk) in jz_clk_pll_half_get_rate() argument
234 return jz_clk_pll_get_rate(clk->parent); in jz_clk_pll_half_get_rate()
235 return jz_clk_pll_get_rate(clk->parent) >> 1; in jz_clk_pll_half_get_rate()
240 static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate) in jz_clk_main_round_rate() argument
242 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); in jz_clk_main_round_rate()
256 static unsigned long jz_clk_main_get_rate(struct clk *clk) in jz_clk_main_get_rate() argument
258 struct main_clk *mclk = (struct main_clk *)clk; in jz_clk_main_get_rate()
269 return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; in jz_clk_main_get_rate()
272 static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate) in jz_clk_main_set_rate() argument
274 struct main_clk *mclk = (struct main_clk *)clk; in jz_clk_main_set_rate()
277 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); in jz_clk_main_set_rate()
279 rate = jz_clk_main_round_rate(clk, rate); in jz_clk_main_set_rate()
301 .clk = {
312 static struct clk jz_clk_pll = {
314 .parent = &jz_clk_ext.clk,
322 static struct clk jz_clk_pll_half = {
335 .clk = {
344 .clk = {
353 .clk = {
363 .clk = {
377 static struct clk jz_clk_ko = {
379 .parent = &jz_clk_memory.clk,
383 static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent) in jz_clk_spi_set_parent() argument
387 else if (parent == &jz_clk_ext.clk) in jz_clk_spi_set_parent()
392 clk->parent = parent; in jz_clk_spi_set_parent()
397 static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent) in jz_clk_i2s_set_parent() argument
401 else if (parent == &jz_clk_ext.clk) in jz_clk_i2s_set_parent()
406 clk->parent = parent; in jz_clk_i2s_set_parent()
411 static int jz_clk_udc_enable(struct clk *clk) in jz_clk_udc_enable() argument
419 static int jz_clk_udc_disable(struct clk *clk) in jz_clk_udc_disable() argument
427 static int jz_clk_udc_is_enabled(struct clk *clk) in jz_clk_udc_is_enabled() argument
433 static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent) in jz_clk_udc_set_parent() argument
437 else if (parent == &jz_clk_ext.clk) in jz_clk_udc_set_parent()
442 clk->parent = parent; in jz_clk_udc_set_parent()
447 static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate) in jz_clk_udc_set_rate() argument
451 if (clk->parent == &jz_clk_ext.clk) in jz_clk_udc_set_rate()
454 div = clk_get_rate(clk->parent) / rate - 1; in jz_clk_udc_set_rate()
466 static unsigned long jz_clk_udc_get_rate(struct clk *clk) in jz_clk_udc_get_rate() argument
470 if (clk->parent == &jz_clk_ext.clk) in jz_clk_udc_get_rate()
471 return clk_get_rate(clk->parent); in jz_clk_udc_get_rate()
477 return clk_get_rate(clk->parent) / div; in jz_clk_udc_get_rate()
480 static unsigned long jz_clk_divided_get_rate(struct clk *clk) in jz_clk_divided_get_rate() argument
482 struct divided_clk *dclk = (struct divided_clk *)clk; in jz_clk_divided_get_rate()
485 if (clk->parent == &jz_clk_ext.clk) in jz_clk_divided_get_rate()
486 return clk_get_rate(clk->parent); in jz_clk_divided_get_rate()
490 return clk_get_rate(clk->parent) / div; in jz_clk_divided_get_rate()
493 static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate) in jz_clk_divided_set_rate() argument
495 struct divided_clk *dclk = (struct divided_clk *)clk; in jz_clk_divided_set_rate()
498 if (clk->parent == &jz_clk_ext.clk) in jz_clk_divided_set_rate()
501 div = clk_get_rate(clk->parent) / rate - 1; in jz_clk_divided_set_rate()
513 static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate) in jz_clk_ldclk_round_rate() argument
516 unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent); in jz_clk_ldclk_round_rate()
530 static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate) in jz_clk_ldclk_set_rate() argument
537 div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; in jz_clk_ldclk_set_rate()
549 static unsigned long jz_clk_ldclk_get_rate(struct clk *clk) in jz_clk_ldclk_get_rate() argument
556 return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); in jz_clk_ldclk_get_rate()
568 static struct clk jz_clk_ld = {
603 .clk = {
605 .parent = &jz_clk_ext.clk,
613 .clk = {
615 .parent = &jz_clk_ext.clk,
623 .clk = {
633 .clk = {
643 .clk = {
669 static struct clk jz4740_clock_simple_clks[] = {
672 .parent = &jz_clk_ext.clk,
677 .parent = &jz_clk_ext.clk,
683 .parent = &jz_clk_ext.clk,
689 .parent = &jz_clk_high_speed_peripheral.clk,
695 .parent = &jz_clk_high_speed_peripheral.clk,
701 .parent = &jz_clk_ext.clk,
707 .parent = &jz_clk_ext.clk,
713 .parent = &jz_clk_ext.clk,
720 .clk = {
728 int clk_enable(struct clk *clk) in clk_enable() argument
730 if (!clk->ops->enable) in clk_enable()
733 return clk->ops->enable(clk); in clk_enable()
737 void clk_disable(struct clk *clk) in clk_disable() argument
739 if (clk->ops->disable) in clk_disable()
740 clk->ops->disable(clk); in clk_disable()
744 int clk_is_enabled(struct clk *clk) in clk_is_enabled() argument
746 if (clk->ops->is_enabled) in clk_is_enabled()
747 return clk->ops->is_enabled(clk); in clk_is_enabled()
752 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
754 if (clk->ops->get_rate) in clk_get_rate()
755 return clk->ops->get_rate(clk); in clk_get_rate()
756 if (clk->parent) in clk_get_rate()
757 return clk_get_rate(clk->parent); in clk_get_rate()
763 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
765 if (!clk->ops->set_rate) in clk_set_rate()
767 return clk->ops->set_rate(clk, rate); in clk_set_rate()
771 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
773 if (clk->ops->round_rate) in clk_round_rate()
774 return clk->ops->round_rate(clk, rate); in clk_round_rate()
780 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
785 if (!clk->ops->set_parent) in clk_set_parent()
788 enabled = clk_is_enabled(clk); in clk_set_parent()
790 clk_disable(clk); in clk_set_parent()
791 ret = clk->ops->set_parent(clk, parent); in clk_set_parent()
793 clk_enable(clk); in clk_set_parent()
795 jz4740_clock_debugfs_update_parent(clk); in clk_set_parent()
801 struct clk *clk_get(struct device *dev, const char *name) in clk_get()
803 struct clk *clk; in clk_get() local
805 list_for_each_entry(clk, &jz_clocks, list) { in clk_get()
806 if (strcmp(clk->name, name) == 0) in clk_get()
807 return clk; in clk_get()
813 void clk_put(struct clk *clk) in clk_put() argument
818 static inline void clk_add(struct clk *clk) in clk_add() argument
820 list_add_tail(&clk->list, &jz_clocks); in clk_add()
822 jz4740_clock_debugfs_add_clk(clk); in clk_add()
829 clk_add(&jz_clk_ext.clk); in clk_register_clks()
832 clk_add(&jz_clk_cpu.clk); in clk_register_clks()
833 clk_add(&jz_clk_high_speed_peripheral.clk); in clk_register_clks()
834 clk_add(&jz_clk_low_speed_peripheral.clk); in clk_register_clks()
837 clk_add(&jz_clk_rtc.clk); in clk_register_clks()
840 clk_add(&jz4740_clock_divided_clks[i].clk); in clk_register_clks()
908 jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; in jz4740_clock_init()
913 jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; in jz4740_clock_init()