63 static struct clk r_clk = {
71 struct clk sh73a0_extal1_clk = {
79 struct clk sh73a0_extal2_clk = {
88 static struct clk main_clk = {
94 static unsigned long pll_recalc(struct clk *clk)  in pll_recalc()  argument
98 	if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {  in pll_recalc()
99 		mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);  in pll_recalc()
101 		switch (clk->enable_bit) {  in pll_recalc()
104 			if (__raw_readl(clk->enable_reg) & (1 << 20))  in pll_recalc()
109 	return clk->parent->rate * mult;  in pll_recalc()
116 static struct clk pll0_clk = {
124 static struct clk pll1_clk = {
132 static struct clk pll2_clk = {
140 static struct clk pll3_clk = {
161 struct clk sh73a0_extcki_clk = {
164 struct clk sh73a0_extalr_clk = {
167 static struct clk *main_clks[] = {
201 static void div4_kick(struct clk *clk)  in div4_kick()  argument
225 static struct clk div4_clks[DIV4_NR] = {
242 static unsigned long twd_recalc(struct clk *clk)  in twd_recalc()  argument
244 	return clk_get_rate(clk->parent) / 4;  in twd_recalc()
251 static struct clk twd_clk = {
259 static int zclk_set_rate(struct clk *clk, unsigned long rate)  in zclk_set_rate()  argument
263 	if (!clk->parent || !__clk_get(clk->parent))  in zclk_set_rate()
269 	if (rate == clk_get_rate(clk->parent)) {  in zclk_set_rate()
273 		ret = div4_clk_ops->set_rate(clk, rate / 2);  in zclk_set_rate()
288 			ret = div4_clk_ops->set_rate(clk, rate);  in zclk_set_rate()
294 	__clk_put(clk->parent);  in zclk_set_rate()
298 static long zclk_round_rate(struct clk *clk, unsigned long rate)  in zclk_round_rate()  argument
300 	unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),  in zclk_round_rate()
301 		parent_freq = clk_get_rate(clk->parent);  in zclk_round_rate()
309 static unsigned long zclk_recalc(struct clk *clk)  in zclk_recalc()  argument
315 	unsigned long div_freq = div4_clk_ops->recalc(clk);  in zclk_recalc()
320 	return clk_get_rate(clk->parent);  in zclk_recalc()
323 static int kicker_set_rate(struct clk *clk, unsigned long rate)  in kicker_set_rate()  argument
328 	return div4_clk_ops->set_rate(clk, rate);  in kicker_set_rate()
359 static struct clk *vck_parent[8] = {
369 static struct clk *pll_parent[4] = {
375 static struct clk *hsi_parent[4] = {
381 static struct clk *pll_extal2_parent[] = {
388 static struct clk *dsi_parent[8] = {
396 static struct clk div6_clks[DIV6_NR] = {
440 static unsigned long dsiphy_recalc(struct clk *clk)  in dsiphy_recalc()  argument
444 	value = __raw_readl(clk->mapping->base);  in dsiphy_recalc()
448 		return clk->parent->rate;  in dsiphy_recalc()
459 	return clk->parent->rate / value;  in dsiphy_recalc()
462 static long dsiphy_round_rate(struct clk *clk, unsigned long rate)  in dsiphy_round_rate()  argument
464 	return clk_rate_mult_range_round(clk, 12, 33, rate);  in dsiphy_round_rate()
467 static void dsiphy_disable(struct clk *clk)  in dsiphy_disable()  argument
471 	value = __raw_readl(clk->mapping->base);  in dsiphy_disable()
474 	__raw_writel(value , clk->mapping->base);  in dsiphy_disable()
477 static int dsiphy_enable(struct clk *clk)  in dsiphy_enable()  argument
482 	value = __raw_readl(clk->mapping->base);  in dsiphy_enable()
488 	__raw_writel(value | 0x000B8000, clk->mapping->base);  in dsiphy_enable()
493 static int dsiphy_set_rate(struct clk *clk, unsigned long rate)  in dsiphy_set_rate()  argument
498 	idx = rate / clk->parent->rate;  in dsiphy_set_rate()
504 	value = __raw_readl(clk->mapping->base);  in dsiphy_set_rate()
507 	__raw_writel(value, clk->mapping->base);  in dsiphy_set_rate()
530 static struct clk dsi0phy_clk = {
536 static struct clk dsi1phy_clk = {
542 static struct clk *late_main_clks[] = {
562 static struct clk mstp_clks[MSTP_NR] = {