1/*
2 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
3 * Author: Yanhua, yanh@lemote.com
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License.  See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#include <linux/clk.h>
10#include <linux/cpufreq.h>
11#include <linux/errno.h>
12#include <linux/export.h>
13#include <linux/list.h>
14#include <linux/mutex.h>
15#include <linux/spinlock.h>
16
17#include <asm/clock.h>
18#include <asm/mach-loongson/loongson.h>
19
20static LIST_HEAD(clock_list);
21static DEFINE_SPINLOCK(clock_lock);
22static DEFINE_MUTEX(clock_list_sem);
23
24/* Minimum CLK support */
25enum {
26	DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
27	DC_87PT, DC_DISABLE, DC_RESV
28};
29
30struct cpufreq_frequency_table loongson2_clockmod_table[] = {
31	{0, DC_RESV, CPUFREQ_ENTRY_INVALID},
32	{0, DC_ZERO, CPUFREQ_ENTRY_INVALID},
33	{0, DC_25PT, 0},
34	{0, DC_37PT, 0},
35	{0, DC_50PT, 0},
36	{0, DC_62PT, 0},
37	{0, DC_75PT, 0},
38	{0, DC_87PT, 0},
39	{0, DC_DISABLE, 0},
40	{0, DC_RESV, CPUFREQ_TABLE_END},
41};
42EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
43
44static struct clk cpu_clk = {
45	.name = "cpu_clk",
46	.flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
47	.rate = 800000000,
48};
49
50struct clk *clk_get(struct device *dev, const char *id)
51{
52	return &cpu_clk;
53}
54EXPORT_SYMBOL(clk_get);
55
56static void propagate_rate(struct clk *clk)
57{
58	struct clk *clkp;
59
60	list_for_each_entry(clkp, &clock_list, node) {
61		if (likely(clkp->parent != clk))
62			continue;
63		if (likely(clkp->ops && clkp->ops->recalc))
64			clkp->ops->recalc(clkp);
65		if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
66			propagate_rate(clkp);
67	}
68}
69
70int clk_enable(struct clk *clk)
71{
72	return 0;
73}
74EXPORT_SYMBOL(clk_enable);
75
76void clk_disable(struct clk *clk)
77{
78}
79EXPORT_SYMBOL(clk_disable);
80
81unsigned long clk_get_rate(struct clk *clk)
82{
83	return (unsigned long)clk->rate;
84}
85EXPORT_SYMBOL(clk_get_rate);
86
87void clk_put(struct clk *clk)
88{
89}
90EXPORT_SYMBOL(clk_put);
91
92int clk_set_rate(struct clk *clk, unsigned long rate)
93{
94	unsigned int rate_khz = rate / 1000;
95	struct cpufreq_frequency_table *pos;
96	int ret = 0;
97	int regval;
98
99	if (likely(clk->ops && clk->ops->set_rate)) {
100		unsigned long flags;
101
102		spin_lock_irqsave(&clock_lock, flags);
103		ret = clk->ops->set_rate(clk, rate, 0);
104		spin_unlock_irqrestore(&clock_lock, flags);
105	}
106
107	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
108		propagate_rate(clk);
109
110	cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
111		if (rate_khz == pos->frequency)
112			break;
113	if (rate_khz != pos->frequency)
114		return -ENOTSUPP;
115
116	clk->rate = rate;
117
118	regval = LOONGSON_CHIPCFG(0);
119	regval = (regval & ~0x7) | (pos->driver_data - 1);
120	LOONGSON_CHIPCFG(0) = regval;
121
122	return ret;
123}
124EXPORT_SYMBOL_GPL(clk_set_rate);
125
126long clk_round_rate(struct clk *clk, unsigned long rate)
127{
128	if (likely(clk->ops && clk->ops->round_rate)) {
129		unsigned long flags, rounded;
130
131		spin_lock_irqsave(&clock_lock, flags);
132		rounded = clk->ops->round_rate(clk, rate);
133		spin_unlock_irqrestore(&clock_lock, flags);
134
135		return rounded;
136	}
137
138	return rate;
139}
140EXPORT_SYMBOL_GPL(clk_round_rate);
141