1/* 2 * Clock definitions for u8500 platform. 3 * 4 * Copyright (C) 2012 ST-Ericsson SA 5 * Author: Ulf Hansson <ulf.hansson@linaro.org> 6 * 7 * License terms: GNU General Public License (GPL) version 2 8 */ 9 10#include <linux/clk.h> 11#include <linux/clkdev.h> 12#include <linux/clk-provider.h> 13#include <linux/mfd/dbx500-prcmu.h> 14#include <linux/platform_data/clk-ux500.h> 15#include "clk.h" 16 17void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, 18 u32 clkrst5_base, u32 clkrst6_base) 19{ 20 struct prcmu_fw_version *fw_version; 21 const char *sgaclk_parent = NULL; 22 struct clk *clk; 23 24 /* Clock sources */ 25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, 26 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 27 clk_register_clkdev(clk, "soc0_pll", NULL); 28 29 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, 30 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 31 clk_register_clkdev(clk, "soc1_pll", NULL); 32 33 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, 34 CLK_IS_ROOT|CLK_IGNORE_UNUSED); 35 clk_register_clkdev(clk, "ddr_pll", NULL); 36 37 /* FIXME: Add sys, ulp and int clocks here. */ 38 39 clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL", 40 CLK_IS_ROOT|CLK_IGNORE_UNUSED, 41 32768); 42 clk_register_clkdev(clk, "clk32k", NULL); 43 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); 44 45 /* PRCMU clocks */ 46 fw_version = prcmu_get_fw_version(); 47 if (fw_version != NULL) { 48 switch (fw_version->project) { 49 case PRCMU_FW_PROJECT_U8500_C2: 50 case PRCMU_FW_PROJECT_U8520: 51 case PRCMU_FW_PROJECT_U8420: 52 sgaclk_parent = "soc0_pll"; 53 break; 54 default: 55 break; 56 } 57 } 58 59 if (sgaclk_parent) 60 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, 61 PRCMU_SGACLK, 0); 62 else 63 clk = clk_reg_prcmu_gate("sgclk", NULL, 64 PRCMU_SGACLK, CLK_IS_ROOT); 65 clk_register_clkdev(clk, NULL, "mali"); 66 67 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); 68 clk_register_clkdev(clk, NULL, "UART"); 69 70 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); 71 clk_register_clkdev(clk, NULL, "MSP02"); 72 73 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); 74 clk_register_clkdev(clk, NULL, "MSP1"); 75 76 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); 77 clk_register_clkdev(clk, NULL, "I2C"); 78 79 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); 80 clk_register_clkdev(clk, NULL, "slim"); 81 82 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); 83 clk_register_clkdev(clk, NULL, "PERIPH1"); 84 85 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); 86 clk_register_clkdev(clk, NULL, "PERIPH2"); 87 88 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); 89 clk_register_clkdev(clk, NULL, "PERIPH3"); 90 91 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); 92 clk_register_clkdev(clk, NULL, "PERIPH5"); 93 94 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); 95 clk_register_clkdev(clk, NULL, "PERIPH6"); 96 97 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); 98 clk_register_clkdev(clk, NULL, "PERIPH7"); 99 100 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, 101 CLK_IS_ROOT|CLK_SET_RATE_GATE); 102 clk_register_clkdev(clk, NULL, "lcd"); 103 clk_register_clkdev(clk, "lcd", "mcde"); 104 105 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); 106 clk_register_clkdev(clk, NULL, "bml"); 107 108 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, 109 CLK_IS_ROOT|CLK_SET_RATE_GATE); 110 111 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, 112 CLK_IS_ROOT|CLK_SET_RATE_GATE); 113 114 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, 115 CLK_IS_ROOT|CLK_SET_RATE_GATE); 116 clk_register_clkdev(clk, NULL, "hdmi"); 117 clk_register_clkdev(clk, "hdmi", "mcde"); 118 119 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); 120 clk_register_clkdev(clk, NULL, "apeat"); 121 122 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, 123 CLK_IS_ROOT); 124 clk_register_clkdev(clk, NULL, "apetrace"); 125 126 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); 127 clk_register_clkdev(clk, NULL, "mcde"); 128 clk_register_clkdev(clk, "mcde", "mcde"); 129 clk_register_clkdev(clk, "dsisys", "dsilink.0"); 130 clk_register_clkdev(clk, "dsisys", "dsilink.1"); 131 clk_register_clkdev(clk, "dsisys", "dsilink.2"); 132 133 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 134 CLK_IS_ROOT); 135 clk_register_clkdev(clk, NULL, "ipi2"); 136 137 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 138 CLK_IS_ROOT); 139 clk_register_clkdev(clk, NULL, "dsialt"); 140 141 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); 142 clk_register_clkdev(clk, NULL, "dma40.0"); 143 144 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); 145 clk_register_clkdev(clk, NULL, "b2r2"); 146 clk_register_clkdev(clk, NULL, "b2r2_core"); 147 clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); 148 149 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, 150 CLK_IS_ROOT|CLK_SET_RATE_GATE); 151 clk_register_clkdev(clk, NULL, "tv"); 152 clk_register_clkdev(clk, "tv", "mcde"); 153 154 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); 155 clk_register_clkdev(clk, NULL, "SSP"); 156 157 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); 158 clk_register_clkdev(clk, NULL, "rngclk"); 159 160 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); 161 clk_register_clkdev(clk, NULL, "uicc"); 162 163 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); 164 clk_register_clkdev(clk, NULL, "mtu0"); 165 clk_register_clkdev(clk, NULL, "mtu1"); 166 167 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, 168 100000000, 169 CLK_IS_ROOT|CLK_SET_RATE_GATE); 170 clk_register_clkdev(clk, NULL, "sdmmc"); 171 172 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", 173 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); 174 clk_register_clkdev(clk, "dsihs2", "mcde"); 175 clk_register_clkdev(clk, "dsihs2", "dsilink.2"); 176 177 178 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", 179 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); 180 clk_register_clkdev(clk, "dsihs0", "mcde"); 181 clk_register_clkdev(clk, "dsihs0", "dsilink.0"); 182 183 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", 184 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE); 185 clk_register_clkdev(clk, "dsihs1", "mcde"); 186 clk_register_clkdev(clk, "dsihs1", "dsilink.1"); 187 188 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", 189 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE); 190 clk_register_clkdev(clk, "dsilp0", "dsilink.0"); 191 clk_register_clkdev(clk, "dsilp0", "mcde"); 192 193 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", 194 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE); 195 clk_register_clkdev(clk, "dsilp1", "dsilink.1"); 196 clk_register_clkdev(clk, "dsilp1", "mcde"); 197 198 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", 199 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE); 200 clk_register_clkdev(clk, "dsilp2", "dsilink.2"); 201 clk_register_clkdev(clk, "dsilp2", "mcde"); 202 203 clk = clk_reg_prcmu_scalable_rate("armss", NULL, 204 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); 205 clk_register_clkdev(clk, "armss", NULL); 206 207 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", 208 CLK_IGNORE_UNUSED, 1, 2); 209 clk_register_clkdev(clk, NULL, "smp_twd"); 210 211 /* 212 * FIXME: Add special handled PRCMU clocks here: 213 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. 214 * 2. ab9540_clkout1yuv, see clkout0yuv 215 */ 216 217 /* PRCC P-clocks */ 218 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, 219 BIT(0), 0); 220 clk_register_clkdev(clk, "apb_pclk", "uart0"); 221 222 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, 223 BIT(1), 0); 224 clk_register_clkdev(clk, "apb_pclk", "uart1"); 225 226 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, 227 BIT(2), 0); 228 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); 229 230 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, 231 BIT(3), 0); 232 clk_register_clkdev(clk, "apb_pclk", "msp0"); 233 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0"); 234 235 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, 236 BIT(4), 0); 237 clk_register_clkdev(clk, "apb_pclk", "msp1"); 238 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1"); 239 240 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, 241 BIT(5), 0); 242 clk_register_clkdev(clk, "apb_pclk", "sdi0"); 243 244 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, 245 BIT(6), 0); 246 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); 247 248 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, 249 BIT(7), 0); 250 clk_register_clkdev(clk, NULL, "spi3"); 251 252 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, 253 BIT(8), 0); 254 clk_register_clkdev(clk, "apb_pclk", "slimbus0"); 255 256 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, 257 BIT(9), 0); 258 clk_register_clkdev(clk, NULL, "gpio.0"); 259 clk_register_clkdev(clk, NULL, "gpio.1"); 260 clk_register_clkdev(clk, NULL, "gpioblock0"); 261 262 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, 263 BIT(10), 0); 264 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); 265 266 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, 267 BIT(11), 0); 268 clk_register_clkdev(clk, "apb_pclk", "msp3"); 269 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3"); 270 271 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, 272 BIT(0), 0); 273 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); 274 275 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, 276 BIT(1), 0); 277 clk_register_clkdev(clk, NULL, "spi2"); 278 279 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, 280 BIT(2), 0); 281 clk_register_clkdev(clk, NULL, "spi1"); 282 283 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, 284 BIT(3), 0); 285 clk_register_clkdev(clk, NULL, "pwl"); 286 287 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, 288 BIT(4), 0); 289 clk_register_clkdev(clk, "apb_pclk", "sdi4"); 290 291 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, 292 BIT(5), 0); 293 clk_register_clkdev(clk, "apb_pclk", "msp2"); 294 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2"); 295 296 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, 297 BIT(6), 0); 298 clk_register_clkdev(clk, "apb_pclk", "sdi1"); 299 300 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, 301 BIT(7), 0); 302 clk_register_clkdev(clk, "apb_pclk", "sdi3"); 303 304 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, 305 BIT(8), 0); 306 clk_register_clkdev(clk, NULL, "spi0"); 307 308 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, 309 BIT(9), 0); 310 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); 311 312 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, 313 BIT(10), 0); 314 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); 315 316 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, 317 BIT(11), 0); 318 clk_register_clkdev(clk, NULL, "gpio.6"); 319 clk_register_clkdev(clk, NULL, "gpio.7"); 320 clk_register_clkdev(clk, NULL, "gpioblock1"); 321 322 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, 323 BIT(12), 0); 324 325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, 326 BIT(0), 0); 327 clk_register_clkdev(clk, "fsmc", NULL); 328 clk_register_clkdev(clk, NULL, "smsc911x.0"); 329 330 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, 331 BIT(1), 0); 332 clk_register_clkdev(clk, "apb_pclk", "ssp0"); 333 334 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, 335 BIT(2), 0); 336 clk_register_clkdev(clk, "apb_pclk", "ssp1"); 337 338 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, 339 BIT(3), 0); 340 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); 341 342 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, 343 BIT(4), 0); 344 clk_register_clkdev(clk, "apb_pclk", "sdi2"); 345 346 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, 347 BIT(5), 0); 348 clk_register_clkdev(clk, "apb_pclk", "ske"); 349 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); 350 351 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, 352 BIT(6), 0); 353 clk_register_clkdev(clk, "apb_pclk", "uart2"); 354 355 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, 356 BIT(7), 0); 357 clk_register_clkdev(clk, "apb_pclk", "sdi5"); 358 359 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, 360 BIT(8), 0); 361 clk_register_clkdev(clk, NULL, "gpio.2"); 362 clk_register_clkdev(clk, NULL, "gpio.3"); 363 clk_register_clkdev(clk, NULL, "gpio.4"); 364 clk_register_clkdev(clk, NULL, "gpio.5"); 365 clk_register_clkdev(clk, NULL, "gpioblock2"); 366 367 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, 368 BIT(0), 0); 369 clk_register_clkdev(clk, "usb", "musb-ux500.0"); 370 371 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, 372 BIT(1), 0); 373 clk_register_clkdev(clk, NULL, "gpio.8"); 374 clk_register_clkdev(clk, NULL, "gpioblock3"); 375 376 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, 377 BIT(0), 0); 378 clk_register_clkdev(clk, "apb_pclk", "rng"); 379 380 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, 381 BIT(1), 0); 382 clk_register_clkdev(clk, NULL, "cryp0"); 383 clk_register_clkdev(clk, NULL, "cryp1"); 384 385 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, 386 BIT(2), 0); 387 clk_register_clkdev(clk, NULL, "hash0"); 388 389 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, 390 BIT(3), 0); 391 clk_register_clkdev(clk, NULL, "pka"); 392 393 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, 394 BIT(4), 0); 395 clk_register_clkdev(clk, NULL, "hash1"); 396 397 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, 398 BIT(5), 0); 399 clk_register_clkdev(clk, NULL, "cfgreg"); 400 401 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, 402 BIT(6), 0); 403 clk_register_clkdev(clk, "apb_pclk", "mtu0"); 404 405 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, 406 BIT(7), 0); 407 clk_register_clkdev(clk, "apb_pclk", "mtu1"); 408 409 /* PRCC K-clocks 410 * 411 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled 412 * by enabling just the K-clock, even if it is not a valid parent to 413 * the K-clock. Until drivers get fixed we might need some kind of 414 * "parent muxed join". 415 */ 416 417 /* Periph1 */ 418 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", 419 clkrst1_base, BIT(0), CLK_SET_RATE_GATE); 420 clk_register_clkdev(clk, NULL, "uart0"); 421 422 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", 423 clkrst1_base, BIT(1), CLK_SET_RATE_GATE); 424 clk_register_clkdev(clk, NULL, "uart1"); 425 426 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", 427 clkrst1_base, BIT(2), CLK_SET_RATE_GATE); 428 clk_register_clkdev(clk, NULL, "nmk-i2c.1"); 429 430 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", 431 clkrst1_base, BIT(3), CLK_SET_RATE_GATE); 432 clk_register_clkdev(clk, NULL, "msp0"); 433 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0"); 434 435 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", 436 clkrst1_base, BIT(4), CLK_SET_RATE_GATE); 437 clk_register_clkdev(clk, NULL, "msp1"); 438 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1"); 439 440 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", 441 clkrst1_base, BIT(5), CLK_SET_RATE_GATE); 442 clk_register_clkdev(clk, NULL, "sdi0"); 443 444 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", 445 clkrst1_base, BIT(6), CLK_SET_RATE_GATE); 446 clk_register_clkdev(clk, NULL, "nmk-i2c.2"); 447 448 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", 449 clkrst1_base, BIT(8), CLK_SET_RATE_GATE); 450 clk_register_clkdev(clk, NULL, "slimbus0"); 451 452 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", 453 clkrst1_base, BIT(9), CLK_SET_RATE_GATE); 454 clk_register_clkdev(clk, NULL, "nmk-i2c.4"); 455 456 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", 457 clkrst1_base, BIT(10), CLK_SET_RATE_GATE); 458 clk_register_clkdev(clk, NULL, "msp3"); 459 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3"); 460 461 /* Periph2 */ 462 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", 463 clkrst2_base, BIT(0), CLK_SET_RATE_GATE); 464 clk_register_clkdev(clk, NULL, "nmk-i2c.3"); 465 466 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", 467 clkrst2_base, BIT(2), CLK_SET_RATE_GATE); 468 clk_register_clkdev(clk, NULL, "sdi4"); 469 470 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", 471 clkrst2_base, BIT(3), CLK_SET_RATE_GATE); 472 clk_register_clkdev(clk, NULL, "msp2"); 473 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2"); 474 475 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", 476 clkrst2_base, BIT(4), CLK_SET_RATE_GATE); 477 clk_register_clkdev(clk, NULL, "sdi1"); 478 479 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", 480 clkrst2_base, BIT(5), CLK_SET_RATE_GATE); 481 clk_register_clkdev(clk, NULL, "sdi3"); 482 483 /* Note that rate is received from parent. */ 484 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", 485 clkrst2_base, BIT(6), 486 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 487 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", 488 clkrst2_base, BIT(7), 489 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 490 491 /* Periph3 */ 492 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", 493 clkrst3_base, BIT(1), CLK_SET_RATE_GATE); 494 clk_register_clkdev(clk, NULL, "ssp0"); 495 496 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", 497 clkrst3_base, BIT(2), CLK_SET_RATE_GATE); 498 clk_register_clkdev(clk, NULL, "ssp1"); 499 500 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", 501 clkrst3_base, BIT(3), CLK_SET_RATE_GATE); 502 clk_register_clkdev(clk, NULL, "nmk-i2c.0"); 503 504 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", 505 clkrst3_base, BIT(4), CLK_SET_RATE_GATE); 506 clk_register_clkdev(clk, NULL, "sdi2"); 507 508 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 509 clkrst3_base, BIT(5), CLK_SET_RATE_GATE); 510 clk_register_clkdev(clk, NULL, "ske"); 511 clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); 512 513 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 514 clkrst3_base, BIT(6), CLK_SET_RATE_GATE); 515 clk_register_clkdev(clk, NULL, "uart2"); 516 517 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", 518 clkrst3_base, BIT(7), CLK_SET_RATE_GATE); 519 clk_register_clkdev(clk, NULL, "sdi5"); 520 521 /* Periph6 */ 522 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 523 clkrst6_base, BIT(0), CLK_SET_RATE_GATE); 524 clk_register_clkdev(clk, NULL, "rng"); 525} 526