1/*
2 * PLL clock driver for Keystone devices
3 *
4 * Copyright (C) 2013 Texas Instruments Inc.
5 *	Murali Karicheri <m-karicheri2@ti.com>
6 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/of_address.h>
19#include <linux/of.h>
20#include <linux/module.h>
21
22#define PLLM_LOW_MASK		0x3f
23#define PLLM_HIGH_MASK		0x7ffc0
24#define MAIN_PLLM_HIGH_MASK	0x7f000
25#define PLLM_HIGH_SHIFT		6
26#define PLLD_MASK		0x3f
27#define CLKOD_MASK		0x780000
28#define CLKOD_SHIFT		19
29
30/**
31 * struct clk_pll_data - pll data structure
32 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
33 *	register of pll controller, else it is in the pll_ctrl0((bit 11-6)
34 * @phy_pllm: Physical address of PLLM in pll controller. Used when
35 *	has_pllctrl is non zero.
36 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
37 *	Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
38 *	or PA PLL available on keystone2. These PLLs are controlled by
39 *	this register. Main PLL is controlled by a PLL controller.
40 * @pllm: PLL register map address for multiplier bits
41 * @pllod: PLL register map address for post divider bits
42 * @pll_ctl0: PLL controller map address
43 * @pllm_lower_mask: multiplier lower mask
44 * @pllm_upper_mask: multiplier upper mask
45 * @pllm_upper_shift: multiplier upper shift
46 * @plld_mask: divider mask
47 * @clkod_mask: output divider mask
48 * @clkod_shift: output divider shift
49 * @plld_mask: divider mask
50 * @postdiv: Fixed post divider
51 */
52struct clk_pll_data {
53	bool has_pllctrl;
54	u32 phy_pllm;
55	u32 phy_pll_ctl0;
56	void __iomem *pllm;
57	void __iomem *pllod;
58	void __iomem *pll_ctl0;
59	u32 pllm_lower_mask;
60	u32 pllm_upper_mask;
61	u32 pllm_upper_shift;
62	u32 plld_mask;
63	u32 clkod_mask;
64	u32 clkod_shift;
65	u32 postdiv;
66};
67
68/**
69 * struct clk_pll - Main pll clock
70 * @hw: clk_hw for the pll
71 * @pll_data: PLL driver specific data
72 */
73struct clk_pll {
74	struct clk_hw hw;
75	struct clk_pll_data *pll_data;
76};
77
78#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
79
80static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
81					unsigned long parent_rate)
82{
83	struct clk_pll *pll = to_clk_pll(hw);
84	struct clk_pll_data *pll_data = pll->pll_data;
85	unsigned long rate = parent_rate;
86	u32  mult = 0, prediv, postdiv, val;
87
88	/*
89	 * get bits 0-5 of multiplier from pllctrl PLLM register
90	 * if has_pllctrl is non zero
91	 */
92	if (pll_data->has_pllctrl) {
93		val = readl(pll_data->pllm);
94		mult = (val & pll_data->pllm_lower_mask);
95	}
96
97	/* bit6-12 of PLLM is in Main PLL control register */
98	val = readl(pll_data->pll_ctl0);
99	mult |= ((val & pll_data->pllm_upper_mask)
100			>> pll_data->pllm_upper_shift);
101	prediv = (val & pll_data->plld_mask);
102
103	if (!pll_data->has_pllctrl)
104		/* read post divider from od bits*/
105		postdiv = ((val & pll_data->clkod_mask) >>
106				 pll_data->clkod_shift) + 1;
107	else if (pll_data->pllod) {
108		postdiv = readl(pll_data->pllod);
109		postdiv = ((postdiv & pll_data->clkod_mask) >>
110				pll_data->clkod_shift) + 1;
111	} else
112		postdiv = pll_data->postdiv;
113
114	rate /= (prediv + 1);
115	rate = (rate * (mult + 1));
116	rate /= postdiv;
117
118	return rate;
119}
120
121static const struct clk_ops clk_pll_ops = {
122	.recalc_rate = clk_pllclk_recalc,
123};
124
125static struct clk *clk_register_pll(struct device *dev,
126			const char *name,
127			const char *parent_name,
128			struct clk_pll_data *pll_data)
129{
130	struct clk_init_data init;
131	struct clk_pll *pll;
132	struct clk *clk;
133
134	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
135	if (!pll)
136		return ERR_PTR(-ENOMEM);
137
138	init.name = name;
139	init.ops = &clk_pll_ops;
140	init.flags = 0;
141	init.parent_names = (parent_name ? &parent_name : NULL);
142	init.num_parents = (parent_name ? 1 : 0);
143
144	pll->pll_data	= pll_data;
145	pll->hw.init = &init;
146
147	clk = clk_register(NULL, &pll->hw);
148	if (IS_ERR(clk))
149		goto out;
150
151	return clk;
152out:
153	kfree(pll);
154	return NULL;
155}
156
157/**
158 * _of_clk_init - PLL initialisation via DT
159 * @node: device tree node for this clock
160 * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
161 *		pll controller, else it is in the control regsiter0(bit 11-6)
162 */
163static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
164{
165	struct clk_pll_data *pll_data;
166	const char *parent_name;
167	struct clk *clk;
168	int i;
169
170	pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL);
171	if (!pll_data) {
172		pr_err("%s: Out of memory\n", __func__);
173		return;
174	}
175
176	parent_name = of_clk_get_parent_name(node, 0);
177	if (of_property_read_u32(node, "fixed-postdiv",	&pll_data->postdiv)) {
178		/* assume the PLL has output divider register bits */
179		pll_data->clkod_mask = CLKOD_MASK;
180		pll_data->clkod_shift = CLKOD_SHIFT;
181
182		/*
183		 * Check if there is an post-divider register. If not
184		 * assume od bits are part of control register.
185		 */
186		i = of_property_match_string(node, "reg-names",
187					     "post-divider");
188		pll_data->pllod = of_iomap(node, i);
189	}
190
191	i = of_property_match_string(node, "reg-names", "control");
192	pll_data->pll_ctl0 = of_iomap(node, i);
193	if (!pll_data->pll_ctl0) {
194		pr_err("%s: ioremap failed\n", __func__);
195		iounmap(pll_data->pllod);
196		goto out;
197	}
198
199	pll_data->pllm_lower_mask = PLLM_LOW_MASK;
200	pll_data->pllm_upper_shift = PLLM_HIGH_SHIFT;
201	pll_data->plld_mask = PLLD_MASK;
202	pll_data->has_pllctrl = pllctrl;
203	if (!pll_data->has_pllctrl) {
204		pll_data->pllm_upper_mask = PLLM_HIGH_MASK;
205	} else {
206		pll_data->pllm_upper_mask = MAIN_PLLM_HIGH_MASK;
207		i = of_property_match_string(node, "reg-names", "multiplier");
208		pll_data->pllm = of_iomap(node, i);
209		if (!pll_data->pllm) {
210			iounmap(pll_data->pll_ctl0);
211			iounmap(pll_data->pllod);
212			goto out;
213		}
214	}
215
216	clk = clk_register_pll(NULL, node->name, parent_name, pll_data);
217	if (clk) {
218		of_clk_add_provider(node, of_clk_src_simple_get, clk);
219		return;
220	}
221
222out:
223	pr_err("%s: error initializing pll %s\n", __func__, node->name);
224	kfree(pll_data);
225}
226
227/**
228 * of_keystone_pll_clk_init - PLL initialisation DT wrapper
229 * @node: device tree node for this clock
230 */
231static void __init of_keystone_pll_clk_init(struct device_node *node)
232{
233	_of_pll_clk_init(node, false);
234}
235CLK_OF_DECLARE(keystone_pll_clock, "ti,keystone,pll-clock",
236					of_keystone_pll_clk_init);
237
238/**
239 * of_keystone_pll_main_clk_init - Main PLL initialisation DT wrapper
240 * @node: device tree node for this clock
241 */
242static void __init of_keystone_main_pll_clk_init(struct device_node *node)
243{
244	_of_pll_clk_init(node, true);
245}
246CLK_OF_DECLARE(keystone_main_pll_clock, "ti,keystone,main-pll-clock",
247						of_keystone_main_pll_clk_init);
248
249/**
250 * of_pll_div_clk_init - PLL divider setup function
251 * @node: device tree node for this clock
252 */
253static void __init of_pll_div_clk_init(struct device_node *node)
254{
255	const char *parent_name;
256	void __iomem *reg;
257	u32 shift, mask;
258	struct clk *clk;
259	const char *clk_name = node->name;
260
261	of_property_read_string(node, "clock-output-names", &clk_name);
262	reg = of_iomap(node, 0);
263	if (!reg) {
264		pr_err("%s: ioremap failed\n", __func__);
265		return;
266	}
267
268	parent_name = of_clk_get_parent_name(node, 0);
269	if (!parent_name) {
270		pr_err("%s: missing parent clock\n", __func__);
271		return;
272	}
273
274	if (of_property_read_u32(node, "bit-shift", &shift)) {
275		pr_err("%s: missing 'shift' property\n", __func__);
276		return;
277	}
278
279	if (of_property_read_u32(node, "bit-mask", &mask)) {
280		pr_err("%s: missing 'bit-mask' property\n", __func__);
281		return;
282	}
283
284	clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
285				 mask, 0, NULL);
286	if (clk)
287		of_clk_add_provider(node, of_clk_src_simple_get, clk);
288	else
289		pr_err("%s: error registering divider %s\n", __func__, clk_name);
290}
291CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);
292
293/**
294 * of_pll_mux_clk_init - PLL mux setup function
295 * @node: device tree node for this clock
296 */
297static void __init of_pll_mux_clk_init(struct device_node *node)
298{
299	void __iomem *reg;
300	u32 shift, mask;
301	struct clk *clk;
302	const char *parents[2];
303	const char *clk_name = node->name;
304
305	of_property_read_string(node, "clock-output-names", &clk_name);
306	reg = of_iomap(node, 0);
307	if (!reg) {
308		pr_err("%s: ioremap failed\n", __func__);
309		return;
310	}
311
312	parents[0] = of_clk_get_parent_name(node, 0);
313	parents[1] = of_clk_get_parent_name(node, 1);
314	if (!parents[0] || !parents[1]) {
315		pr_err("%s: missing parent clocks\n", __func__);
316		return;
317	}
318
319	if (of_property_read_u32(node, "bit-shift", &shift)) {
320		pr_err("%s: missing 'shift' property\n", __func__);
321		return;
322	}
323
324	if (of_property_read_u32(node, "bit-mask", &mask)) {
325		pr_err("%s: missing 'bit-mask' property\n", __func__);
326		return;
327	}
328
329	clk = clk_register_mux(NULL, clk_name, (const char **)&parents,
330				ARRAY_SIZE(parents) , 0, reg, shift, mask,
331				0, NULL);
332	if (clk)
333		of_clk_add_provider(node, of_clk_src_simple_get, clk);
334	else
335		pr_err("%s: error registering mux %s\n", __func__, clk_name);
336}
337CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);
338