Lines Matching refs:clk
13 "atmel,at91sam9x5-clk-slow-osc":
16 "atmel,at91sam9x5-clk-slow-rc-osc":
28 "atmel,at91sam9x5-clk-slow" (under sckc node)
30 "atmel,at91sam9260-clk-slow" (under pmc node):
31 at91 slow clk
33 "atmel,at91rm9200-clk-main-osc"
34 "atmel,at91sam9x5-clk-main-rc-osc"
35 at91 main clk sources
37 "atmel,at91sam9x5-clk-main"
38 "atmel,at91rm9200-clk-main":
41 "atmel,at91rm9200-clk-master" or
42 "atmel,at91sam9x5-clk-master":
45 "atmel,at91sam9x5-clk-peripheral" or
46 "atmel,at91rm9200-clk-peripheral":
49 "atmel,at91rm9200-clk-pll" or
50 "atmel,at91sam9g45-clk-pll" or
51 "atmel,at91sam9g20-clk-pllb" or
52 "atmel,sama5d3-clk-pll":
55 "atmel,at91sam9x5-clk-plldiv":
58 "atmel,at91rm9200-clk-programmable" or
59 "atmel,at91sam9g45-clk-programmable" or
60 "atmel,at91sam9x5-clk-programmable":
63 "atmel,at91sam9x5-clk-smd":
66 "atmel,at91rm9200-clk-system":
69 "atmel,at91rm9200-clk-usb" or
70 "atmel,at91sam9x5-clk-usb" or
71 "atmel,at91sam9n12-clk-usb":
74 "atmel,at91sam9x5-clk-utmi":
77 "atmel,sama5d4-clk-h32mx":
82 - #size-cells : shall be 0 (reg is used to encode clk id).
83 - #address-cells : shall be 1 (reg is used to encode clk id).
106 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
113 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
121 compatible = "atmel,at91rm9200-clk-slow-osc";
128 - clocks : shall encode the slow clk sources (see atmel datasheet).
132 compatible = "atmel,at91sam9x5-clk-slow";
139 - #size-cells : shall be 0 (reg is used to encode clk id).
140 - #address-cells : shall be 1 (reg is used to encode clk id).
178 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
189 - clocks : shall encode the main osc source clk sources (see atmel datasheet).
199 compatible = "atmel,at91rm9200-clk-main-osc";
210 - clocks : shall encode the main clk sources (see atmel datasheet).
214 compatible = "atmel,at91sam9x5-clk-main";
227 - atmel,clk-output-range : minimum and maximum clock frequency (two u32
230 - atmel,clk-divisors : master clock divisors table (four u32 fields).
233 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
238 compatible = "atmel,at91rm9200-clk-master";
242 atmel,clk-output-range = <0 133000000>;
243 atmel,clk-divisors = <1 2 4 0>;
247 - #size-cells : shall be 0 (reg is used to encode clk id).
248 - #address-cells : shall be 1 (reg is used to encode clk id).
255 * atmel,clk-output-range : minimum and maximum clock frequency
256 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
261 compatible = "atmel,at91sam9x5-clk-peripheral";
269 atmel,clk-output-range = <0 133000000>;
275 atmel,clk-output-range = <0 66000000>;
288 - atmel,clk-input-range : minimum and maximum source clock frequency (two u32
291 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
299 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
305 compatible = "atmel,at91sam9g45-clk-pll";
311 atmel,clk-input-range = <2000000 32000000>;
312 #atmel,pll-clk-output-range-cells = <4>;
313 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
331 compatible = "atmel,at91sam9x5-clk-plldiv";
338 - #size-cells : shall be 0 (reg is used to encode clk id).
339 - #address-cells : shall be 1 (reg is used to encode clk id).
350 compatible = "atmel,at91sam9g45-clk-programmable";
377 compatible = "atmel,at91sam9x5-clk-smd";
383 - #size-cells : shall be 0 (reg is used to encode clk id).
384 - #address-cells : shall be 1 (reg is used to encode clk id).
392 compatible = "atmel,at91rm9200-clk-system";
420 - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
426 compatible = "atmel,at91sam9x5-clk-usb";
432 compatible = "atmel,at91rm9200-clk-usb";
435 atmel,clk-divisors = <1 2 4 0>;
447 compatible = "atmel,at91sam9x5-clk-utmi";
461 compatible = "atmel,sama5d4-clk-h32mx";