35 static struct clk *clk[IMX1_CLK_MAX];  variable
47 	clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);  in _mx1_clocks_init()
48 	clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);  in _mx1_clocks_init()
49 	clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);  in _mx1_clocks_init()
50 	clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);  in _mx1_clocks_init()
51 	clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);  in _mx1_clocks_init()
52 …clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)…  in _mx1_clocks_init()
53 	clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);  in _mx1_clocks_init()
54 	clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);  in _mx1_clocks_init()
55 	clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);  in _mx1_clocks_init()
56 	clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);  in _mx1_clocks_init()
57 	clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);  in _mx1_clocks_init()
58 	clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);  in _mx1_clocks_init()
59 	clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);  in _mx1_clocks_init()
60 	clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);  in _mx1_clocks_init()
61 	clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);  in _mx1_clocks_init()
62 	clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);  in _mx1_clocks_init()
63 	clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);  in _mx1_clocks_init()
64 …clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)…  in _mx1_clocks_init()
65 	clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);  in _mx1_clocks_init()
66 	clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);  in _mx1_clocks_init()
67 	clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);  in _mx1_clocks_init()
68 	clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);  in _mx1_clocks_init()
69 	clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);  in _mx1_clocks_init()
70 	clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);  in _mx1_clocks_init()
71 	clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);  in _mx1_clocks_init()
73 	imx_check_clocks(clk, ARRAY_SIZE(clk));  in _mx1_clocks_init()
82 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");  in mx1_clocks_init()
83 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");  in mx1_clocks_init()
84 	clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");  in mx1_clocks_init()
85 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");  in mx1_clocks_init()
86 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");  in mx1_clocks_init()
87 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");  in mx1_clocks_init()
88 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");  in mx1_clocks_init()
89 	clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");  in mx1_clocks_init()
90 	clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");  in mx1_clocks_init()
91 	clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");  in mx1_clocks_init()
92 	clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");  in mx1_clocks_init()
93 	clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");  in mx1_clocks_init()
94 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");  in mx1_clocks_init()
95 	clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");  in mx1_clocks_init()
96 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");  in mx1_clocks_init()
97 	clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");  in mx1_clocks_init()
98 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");  in mx1_clocks_init()
99 	clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");  in mx1_clocks_init()
113 	clk_data.clks = clk;  in mx1_clocks_init_dt()
114 	clk_data.clk_num = ARRAY_SIZE(clk);  in mx1_clocks_init_dt()