Lines Matching refs:clk
21 clk_sysin: clk-sysin {
33 clk_s_a0_pll: clk-s-a0-pll {
39 clock-output-names = "clk-s-a0-pll0-hs",
40 "clk-s-a0-pll0-ls",
41 "clk-s-a0-pll1";
44 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
51 clock-output-names = "clk-s-a0-osc-prediv";
54 clk_s_a0_hs: clk-s-a0-hs {
63 clock-output-names = "clk-s-fdma-0",
64 "clk-s-fdma-1",
65 ""; /* clk-s-jit-sense */
69 clk_s_a0_ls: clk-s-a0-ls {
78 clock-output-names = "clk-s-icn-reg-0",
79 "clk-s-icn-if-0",
80 "clk-s-icn-reg-lp-0",
81 "clk-s-emiss",
82 "clk-s-eth1-phy",
83 "clk-s-mii-ref-out";
91 clk_s_a1_pll: clk-s-a1-pll {
97 clock-output-names = "clk-s-a1-pll0-hs",
98 "clk-s-a1-pll0-ls",
99 "clk-s-a1-pll1";
102 clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
109 clock-output-names = "clk-s-a1-osc-prediv";
112 clk_s_a1_hs: clk-s-a1-hs {
123 "clk-s-stac-phy",
124 "clk-s-vtac-tx-phy";
127 clk_s_a1_ls: clk-s-a1-ls {
136 clock-output-names = "clk-s-icn-if-2",
137 "clk-s-card-mmc-0",
138 "clk-s-icn-if-1",
139 "clk-s-gmac0-phy",
140 "clk-s-nand-ctrl",
142 "clk-s-mii0-ref-out",
143 "clk-s-stac-sys",
144 "clk-s-card-mmc-1";
155 clk_m_a0_pll0: clk-m-a0-pll0 {
161 clock-output-names = "clk-m-a0-pll0-phi0",
162 "clk-m-a0-pll0-phi1",
163 "clk-m-a0-pll0-phi2",
164 "clk-m-a0-pll0-phi3";
167 clk_m_a0_pll1: clk-m-a0-pll1 {
173 clock-output-names = "clk-m-a0-pll1-phi0",
174 "clk-m-a0-pll1-phi1",
175 "clk-m-a0-pll1-phi2",
176 "clk-m-a0-pll1-phi3";
179 clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
186 clock-output-names = "clk-m-a0-osc-prediv";
189 clk_m_a0_div0: clk-m-a0-div0 {
200 "clk-m-fdma-12",
202 "clk-m-pp-dmu-0",
203 "clk-m-pp-dmu-1",
204 "clk-m-icm-lmi",
205 "clk-m-vid-dmu-0";
208 clk_m_a0_div1: clk-m-a0-div1 {
217 clock-output-names = "clk-m-vid-dmu-1",
219 "clk-m-a9-ext2f",
220 "clk-m-st40rt",
221 "clk-m-st231-dmu-0",
222 "clk-m-st231-dmu-1",
223 "clk-m-st231-aud",
224 "clk-m-st231-gp-0";
227 clk_m_a0_div2: clk-m-a0-div2 {
236 clock-output-names = "clk-m-st231-gp-1",
237 "clk-m-icn-cpu",
238 "clk-m-icn-stac",
239 "clk-m-tx-icn-dmu-0",
240 "clk-m-tx-icn-dmu-1",
241 "clk-m-tx-icn-ts",
242 "clk-m-icn-vdp-0",
243 "clk-m-icn-vdp-1";
246 clk_m_a0_div3: clk-m-a0-div3 {
259 "clk-m-icn-vp8",
261 "clk-m-icn-reg-11",
262 "clk-m-a9-trace";
269 clk_m_a1_pll0: clk-m-a1-pll0 {
275 clock-output-names = "clk-m-a1-pll0-phi0",
276 "clk-m-a1-pll0-phi1",
277 "clk-m-a1-pll0-phi2",
278 "clk-m-a1-pll0-phi3";
281 clk_m_a1_pll1: clk-m-a1-pll1 {
287 clock-output-names = "clk-m-a1-pll1-phi0",
288 "clk-m-a1-pll1-phi1",
289 "clk-m-a1-pll1-phi2",
290 "clk-m-a1-pll1-phi3";
293 clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
300 clock-output-names = "clk-m-a1-osc-prediv";
303 clk_m_a1_div0: clk-m-a1-div0 {
313 "clk-m-fdma-10",
314 "clk-m-fdma-11",
315 "clk-m-hva-alt",
316 "clk-m-proc-sc",
317 "clk-m-tp",
318 "clk-m-rx-icn-dmu-0",
319 "clk-m-rx-icn-dmu-1";
322 clk_m_a1_div1: clk-m-a1-div1 {
331 clock-output-names = "clk-m-rx-icn-ts",
332 "clk-m-rx-icn-vdp-0",
334 "clk-m-prv-t1-bus",
335 "clk-m-icn-reg-12",
336 "clk-m-icn-reg-10",
338 "clk-m-icn-st231";
341 clk_m_a1_div2: clk-m-a1-div2 {
350 clock-output-names = "clk-m-fvdp-proc-alt",
351 "clk-m-icn-reg-13",
352 "clk-m-tx-icn-gpu",
353 "clk-m-rx-icn-gpu",
356 "", /* clk-m-apb-pm-12 */
360 clk_m_a1_div3: clk-m-a1-div3 {
376 ""; /* clk-m-gpu-alt */
380 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
391 clk_m_a2_pll0: clk-m-a2-pll0 {
397 clock-output-names = "clk-m-a2-pll0-phi0",
398 "clk-m-a2-pll0-phi1",
399 "clk-m-a2-pll0-phi2",
400 "clk-m-a2-pll0-phi3";
403 clk_m_a2_pll1: clk-m-a2-pll1 {
409 clock-output-names = "clk-m-a2-pll1-phi0",
410 "clk-m-a2-pll1-phi1",
411 "clk-m-a2-pll1-phi2",
412 "clk-m-a2-pll1-phi3";
415 clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
422 clock-output-names = "clk-m-a2-osc-prediv";
425 clk_m_a2_div0: clk-m-a2-div0 {
434 clock-output-names = "clk-m-vtac-main-phy",
435 "clk-m-vtac-aux-phy",
436 "clk-m-stac-phy",
437 "clk-m-stac-sys",
438 "", /* clk-m-mpestac-pg */
439 "", /* clk-m-mpestac-wc */
440 "", /* clk-m-mpevtacaux-pg*/
441 ""; /* clk-m-mpevtacmain-pg*/
444 clk_m_a2_div1: clk-m-a2-div1 {
453 clock-output-names = "", /* clk-m-mpevtacrx0-wc */
454 "", /* clk-m-mpevtacrx1-wc */
455 "clk-m-compo-main",
456 "clk-m-compo-aux",
457 "clk-m-bdisp-0",
458 "clk-m-bdisp-1",
459 "clk-m-icn-bdisp",
460 "clk-m-icn-compo";
463 clk_m_a2_div2: clk-m-a2-div2 {
472 clock-output-names = "clk-m-icn-vdp-2",
474 "clk-m-icn-reg-14",
475 "clk-m-mdtp",
476 "clk-m-jpegdec",
478 "clk-m-dcephy-impctrl",
482 clk_m_a2_div3: clk-m-a2-div3 {
492 ""; /* clk-m-apb-pm-11 */
515 clk_m_a9: clk-m-a9@fdde08ac {
528 arm_periph_clk: clk-m-a9-periphs {
545 clock-output-names = "clk-s-usb48",
546 "clk-s-dss",
547 "clk-s-stfe-frc-2",
548 "clk-s-thsens-scard";
557 clock-output-names = "clk-s-pcm-0",
558 "clk-s-pcm-1",
559 "clk-s-pcm-2",
560 "clk-s-pcm-3";
569 clock-output-names = "clk-s-c-fs0-ch0",
570 "clk-s-c-vcc-sd",
571 "clk-s-c-fs0-ch2";
574 clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 {
586 clk_s_tmds_fromphy: clk-s-tmds-fromphy {
602 clock-output-names = "clk-s-pix-hdmi",
603 "clk-s-pix-dvo",
604 "clk-s-out-dvo",
605 "clk-s-pix-hd",
606 "clk-s-hddac",
607 "clk-s-denc",
608 "clk-s-sddac",
609 "clk-s-pix-main",
610 "clk-s-pix-aux",
611 "clk-s-stfe-frc-0",
612 "clk-s-ref-mcru",
613 "clk-s-slave-mcru",
614 "clk-s-tmds-hdmi",
615 "clk-s-hdmi-reject-pll",
616 "clk-s-thsens";
625 clock-output-names = "clk-s-ccsc",
626 "clk-s-stfe-frc-1",
627 "clk-s-tsout-1",
628 "clk-s-mchi";
640 clock-output-names = "clk-m-pix-mdtp-0",
641 "clk-m-pix-mdtp-1",
642 "clk-m-pix-mdtp-2",
643 "clk-m-mpelpc";
652 clock-output-names = "clk-m-main-vidfs",
653 "clk-m-hva-fs",
654 "clk-m-fvdp-vcpu",
655 "clk-m-fvdp-proc-fs";
658 clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 {
667 clk_m_hva: clk-m-hva@fd690868 {
676 clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c {
685 clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c {
697 clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas {
713 clock-output-names = "clk-m-pix-main-pipe",
714 "clk-m-pix-aux-pipe",
715 "clk-m-pix-main-cru",
716 "clk-m-pix-aux-cru",
717 "clk-m-xfer-be-compo",
718 "clk-m-xfer-pip-compo",
719 "clk-m-xfer-aux-compo",
720 "clk-m-vsens",
721 "clk-m-pix-hdmirx-0",
722 "clk-m-pix-hdmirx-1";