1022 static struct clk **clks;
1109 	struct clk *clk;  in tegra124_periph_clk_init()  local
1112 	clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,  in tegra124_periph_clk_init()
1114 	clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;  in tegra124_periph_clk_init()
1116 	clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,  in tegra124_periph_clk_init()
1118 	clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;  in tegra124_periph_clk_init()
1120 	clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,  in tegra124_periph_clk_init()
1123 	clks[TEGRA124_CLK_DSIA] = clk;  in tegra124_periph_clk_init()
1125 	clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,  in tegra124_periph_clk_init()
1128 	clks[TEGRA124_CLK_DSIB] = clk;  in tegra124_periph_clk_init()
1131 	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,  in tegra124_periph_clk_init()
1136 	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1138 	clks[TEGRA124_CLK_MC] = clk;  in tegra124_periph_clk_init()
1141 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1143 	clk_register_clkdev(clk, "cml0", NULL);  in tegra124_periph_clk_init()
1144 	clks[TEGRA124_CLK_CML0] = clk;  in tegra124_periph_clk_init()
1147 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1149 	clk_register_clkdev(clk, "cml1", NULL);  in tegra124_periph_clk_init()
1150 	clks[TEGRA124_CLK_CML1] = clk;  in tegra124_periph_clk_init()
1159 	struct clk *clk;  in tegra124_pll_init()  local
1162 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra124_pll_init()
1164 	clk_register_clkdev(clk, "pll_c", NULL);  in tegra124_pll_init()
1165 	clks[TEGRA124_CLK_PLL_C] = clk;  in tegra124_pll_init()
1168 	clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",  in tegra124_pll_init()
1171 	clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",  in tegra124_pll_init()
1174 	clk_register_clkdev(clk, "pll_c_out1", NULL);  in tegra124_pll_init()
1175 	clks[TEGRA124_CLK_PLL_C_OUT1] = clk;  in tegra124_pll_init()
1178 	clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",  in tegra124_pll_init()
1180 	clk_register_clkdev(clk, "pll_c_ud", NULL);  in tegra124_pll_init()
1181 	clks[TEGRA124_CLK_PLL_C_UD] = clk;  in tegra124_pll_init()
1184 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1186 	clk_register_clkdev(clk, "pll_c2", NULL);  in tegra124_pll_init()
1187 	clks[TEGRA124_CLK_PLL_C2] = clk;  in tegra124_pll_init()
1190 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1192 	clk_register_clkdev(clk, "pll_c3", NULL);  in tegra124_pll_init()
1193 	clks[TEGRA124_CLK_PLL_C3] = clk;  in tegra124_pll_init()
1196 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1199 	clk_register_clkdev(clk, "pll_m", NULL);  in tegra124_pll_init()
1200 	clks[TEGRA124_CLK_PLL_M] = clk;  in tegra124_pll_init()
1203 	clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",  in tegra124_pll_init()
1206 	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",  in tegra124_pll_init()
1209 	clk_register_clkdev(clk, "pll_m_out1", NULL);  in tegra124_pll_init()
1210 	clks[TEGRA124_CLK_PLL_M_OUT1] = clk;  in tegra124_pll_init()
1213 	clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",  in tegra124_pll_init()
1215 	clk_register_clkdev(clk, "pll_m_ud", NULL);  in tegra124_pll_init()
1216 	clks[TEGRA124_CLK_PLL_M_UD] = clk;  in tegra124_pll_init()
1223 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1225 	clk_register_clkdev(clk, "pll_u", NULL);  in tegra124_pll_init()
1226 	clks[TEGRA124_CLK_PLL_U] = clk;  in tegra124_pll_init()
1231 	clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",  in tegra124_pll_init()
1234 	clk_register_clkdev(clk, "pll_u_480M", NULL);  in tegra124_pll_init()
1235 	clks[TEGRA124_CLK_PLL_U_480M] = clk;  in tegra124_pll_init()
1238 	clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",  in tegra124_pll_init()
1240 	clk_register_clkdev(clk, "pll_u_60M", NULL);  in tegra124_pll_init()
1241 	clks[TEGRA124_CLK_PLL_U_60M] = clk;  in tegra124_pll_init()
1244 	clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",  in tegra124_pll_init()
1246 	clk_register_clkdev(clk, "pll_u_48M", NULL);  in tegra124_pll_init()
1247 	clks[TEGRA124_CLK_PLL_U_48M] = clk;  in tegra124_pll_init()
1250 	clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",  in tegra124_pll_init()
1252 	clk_register_clkdev(clk, "pll_u_12M", NULL);  in tegra124_pll_init()
1253 	clks[TEGRA124_CLK_PLL_U_12M] = clk;  in tegra124_pll_init()
1256 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1258 	clk_register_clkdev(clk, "pll_d", NULL);  in tegra124_pll_init()
1259 	clks[TEGRA124_CLK_PLL_D] = clk;  in tegra124_pll_init()
1262 	clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",  in tegra124_pll_init()
1264 	clk_register_clkdev(clk, "pll_d_out0", NULL);  in tegra124_pll_init()
1265 	clks[TEGRA124_CLK_PLL_D_OUT0] = clk;  in tegra124_pll_init()
1268 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1270 	clk_register_clkdev(clk, "pll_re_vco", NULL);  in tegra124_pll_init()
1271 	clks[TEGRA124_CLK_PLL_RE_VCO] = clk;  in tegra124_pll_init()
1273 	clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,  in tegra124_pll_init()
1276 	clk_register_clkdev(clk, "pll_re_out", NULL);  in tegra124_pll_init()
1277 	clks[TEGRA124_CLK_PLL_RE_OUT] = clk;  in tegra124_pll_init()
1280 	clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",  in tegra124_pll_init()
1282 	clk_register_clkdev(clk, "pll_e", NULL);  in tegra124_pll_init()
1283 	clks[TEGRA124_CLK_PLL_E] = clk;  in tegra124_pll_init()
1286 	clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1288 	clk_register_clkdev(clk, "pll_c4", NULL);  in tegra124_pll_init()
1289 	clks[TEGRA124_CLK_PLL_C4] = clk;  in tegra124_pll_init()
1292 	clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1294 	clk_register_clkdev(clk, "pll_dp", NULL);  in tegra124_pll_init()
1295 	clks[TEGRA124_CLK_PLL_DP] = clk;  in tegra124_pll_init()
1298 	clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1300 	clk_register_clkdev(clk, "pll_d2", NULL);  in tegra124_pll_init()
1301 	clks[TEGRA124_CLK_PLL_D2] = clk;  in tegra124_pll_init()
1304 	clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",  in tegra124_pll_init()
1306 	clk_register_clkdev(clk, "pll_d2_out0", NULL);  in tegra124_pll_init()
1307 	clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;  in tegra124_pll_init()