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Searched refs:writel (Results 1 – 200 of 1395) sorted by relevance

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/linux-4.1.27/drivers/video/fbdev/via/
Daccel.c48 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
105 writel(tmp, engine + 0x08); in hw_bitblt_1()
114 writel(tmp, engine + 0x0C); in hw_bitblt_1()
122 writel(tmp, engine + 0x10); in hw_bitblt_1()
125 writel(fg_color, engine + 0x18); in hw_bitblt_1()
128 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
138 writel(tmp, engine + 0x30); in hw_bitblt_1()
147 writel(tmp, engine + 0x34); in hw_bitblt_1()
159 writel(tmp, engine + 0x38); in hw_bitblt_1()
172 writel(ge_cmd, engine); in hw_bitblt_1()
[all …]
/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_dp_reg.c34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap()
70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param()
73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param()
76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param()
80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); in exynos_dp_init_analog_param()
84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); in exynos_dp_init_analog_param()
90 writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); in exynos_dp_init_interrupt()
[all …]
Dexynos7_drm_decon.c104 writel(val, ctx->regs + WINCON(win)); in decon_clear_channel()
196 writel(val, ctx->regs + VIDTCON0); in decon_commit()
199 writel(val, ctx->regs + VIDTCON1); in decon_commit()
208 writel(val, ctx->regs + VIDTCON2); in decon_commit()
211 writel(val, ctx->regs + VIDTCON3); in decon_commit()
217 writel(val, ctx->regs + VIDTCON4); in decon_commit()
219 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); in decon_commit()
226 writel(val, ctx->regs + VIDCON0); in decon_commit()
231 writel(val, ctx->regs + VCLKCON1); in decon_commit()
232 writel(val, ctx->regs + VCLKCON2); in decon_commit()
[all …]
Dexynos_drm_fimd.c228 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output()
242 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
354 writel(val, timing_base + I80IFCONFAx(0)); in fimd_commit()
357 writel(0, timing_base + I80IFCONFBx(0)); in fimd_commit()
378 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit()
388 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
398 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
402 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit()
418 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
434 writel(val, ctx->regs + VIDCON0); in fimd_commit()
[all …]
/linux-4.1.27/drivers/video/fbdev/
Dwmt_ge_rops.c67 writel(p->var.bits_per_pixel == 32 ? 3 : in wmt_ge_fillrect()
69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); in wmt_ge_fillrect()
70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); in wmt_ge_fillrect()
71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); in wmt_ge_fillrect()
72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); in wmt_ge_fillrect()
73 writel(rect->dx, regbase + GE_DESTAREAX_OFF); in wmt_ge_fillrect()
74 writel(rect->dy, regbase + GE_DESTAREAY_OFF); in wmt_ge_fillrect()
75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); in wmt_ge_fillrect()
76 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); in wmt_ge_fillrect()
78 writel(pat, regbase + GE_PAT0C_OFF); in wmt_ge_fillrect()
[all …]
Dw100fb.c133 writel(param, remapped_regs + regs); in w100fb_reg_write()
297 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET); in w100_init_graphic_engine()
298 writel(par->xres, remapped_regs + mmDST_PITCH); in w100_init_graphic_engine()
299 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET); in w100_init_graphic_engine()
300 writel(par->xres, remapped_regs + mmSRC_PITCH); in w100_init_graphic_engine()
303 writel(0, remapped_regs + mmSC_TOP_LEFT); in w100_init_graphic_engine()
304 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT); in w100_init_graphic_engine()
305 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT); in w100_init_graphic_engine()
315 writel(dp_cntl.val, remapped_regs + mmDP_CNTL); in w100_init_graphic_engine()
332 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); in w100_init_graphic_engine()
[all …]
Dfb-puv3.c164 writel(((u32 *)(info->pseudo_palette))[fg_color], UGE_FCOLOR); in unifb_prim_fillrect()
165 writel(0, UGE_BCOLOR); in unifb_prim_fillrect()
166 writel(src_pitch, UGE_PITCH); in unifb_prim_fillrect()
167 writel(src_offset, UGE_SRCSTART); in unifb_prim_fillrect()
168 writel(dst_offset, UGE_DSTSTART); in unifb_prim_fillrect()
169 writel(awidth, UGE_WIDHEIGHT); in unifb_prim_fillrect()
170 writel(top, UGE_CLIP0); in unifb_prim_fillrect()
171 writel(bottom, UGE_CLIP1); in unifb_prim_fillrect()
172 writel(alpha_r, UGE_ROPALPHA); in unifb_prim_fillrect()
173 writel(src_x0, UGE_SRCXY); in unifb_prim_fillrect()
[all …]
Dwm8505fb.c59 writel(0, fbi->regbase + i); in wm8505fb_init_hw()
62 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); in wm8505fb_init_hw()
63 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); in wm8505fb_init_hw()
70 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); in wm8505fb_init_hw()
71 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); in wm8505fb_init_hw()
74 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); in wm8505fb_init_hw()
75 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); in wm8505fb_init_hw()
78 writel(0xf, fbi->regbase + WMT_GOVR_FHI); in wm8505fb_init_hw()
79 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); in wm8505fb_init_hw()
80 writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE); in wm8505fb_init_hw()
[all …]
Doffb.c173 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_setcolreg()
175 writel(((red) << 22) | ((green) << 12) | ((blue) << 2), in offb_setcolreg()
177 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_setcolreg()
179 writel(((red) << 22) | ((green) << 12) | ((blue) << 2), in offb_setcolreg()
239 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_blank()
241 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); in offb_blank()
242 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_blank()
244 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); in offb_blank()
258 writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL); in offb_set_par()
259 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE); in offb_set_par()
[all …]
Ds3c-fb.c47 #undef writel
48 #define writel(v, r) do { \ macro
401 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant) in vidosd_set_size()
416 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant)); in vidosd_set_alpha()
432 writel(PRTCON_PROTECT, sfb->regs + PRTCON); in shadow_protect_win()
435 writel(reg | SHADOWCON_WINx_PROTECT(win->index), in shadow_protect_win()
440 writel(0, sfb->regs + PRTCON); in shadow_protect_win()
443 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index), in shadow_protect_win()
474 writel(vidcon0, sfb->regs + VIDCON0); in s3c_fb_enable()
533 writel(0, regs + WINCON(win_no)); in s3c_fb_set_par()
[all …]
Dnuc900fb.c60 writel(vbaddr1, regs + REG_LCM_VA_BADDR0); in nuc900fb_set_lcdaddr()
61 writel(vbaddr2, regs + REG_LCM_VA_BADDR1); in nuc900fb_set_lcdaddr()
63 writel(fbi->regs.lcd_va_fbctrl, regs + REG_LCM_VA_FBCTRL); in nuc900fb_set_lcdaddr()
64 writel(fbi->regs.lcd_va_scale, regs + REG_LCM_VA_SCALE); in nuc900fb_set_lcdaddr()
248 writel(fbi->regs.lcd_device_ctrl, regs + REG_LCM_DEV_CTRL); in nuc900fb_activate_var()
249 writel(fbi->regs.lcd_crtc_size, regs + REG_LCM_CRTC_SIZE); in nuc900fb_activate_var()
250 writel(fbi->regs.lcd_crtc_dend, regs + REG_LCM_CRTC_DEND); in nuc900fb_activate_var()
251 writel(fbi->regs.lcd_crtc_hr, regs + REG_LCM_CRTC_HR); in nuc900fb_activate_var()
252 writel(fbi->regs.lcd_crtc_hsync, regs + REG_LCM_CRTC_HSYNC); in nuc900fb_activate_var()
253 writel(fbi->regs.lcd_crtc_vr, regs + REG_LCM_CRTC_VR); in nuc900fb_activate_var()
[all …]
Dpxa168fb.c291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider()
326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start()
386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control()
399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions()
426 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
431 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
451 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); in pxa168fb_set_par()
452 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
[all …]
/linux-4.1.27/drivers/clocksource/
Dtimer-u300.c204 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_set_mode()
207 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_set_mode()
213 writel(cevdata->ticks_per_jiffy, in u300_set_mode()
219 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, in u300_set_mode()
222 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, in u300_set_mode()
225 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, in u300_set_mode()
236 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_set_mode()
239 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_set_mode()
245 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); in u300_set_mode()
247 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, in u300_set_mode()
[all …]
Dzevio-timer.c72 writel(delta, timer->timer1 + IO_CURRENT_VAL); in zevio_timer_set_event()
73 writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH), in zevio_timer_set_event()
89 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK); in zevio_timer_set_mode()
90 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_set_mode()
95 writel(0, timer->interrupt_regs + IO_INTR_MSK); in zevio_timer_set_mode()
96 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_set_mode()
98 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_set_mode()
116 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_interrupt()
117 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_interrupt()
171 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_add()
[all …]
Dnomadik-mtu.c95 writel(1 << 1, mtu_base + MTU_IMSC); in nmdk_clkevt_next()
96 writel(evt, mtu_base + MTU_LR(1)); in nmdk_clkevt_next()
98 writel(MTU_CRn_ONESHOT | clk_prescale | in nmdk_clkevt_next()
109 writel(nmdk_cycle, mtu_base + MTU_LR(1)); in nmdk_clkevt_reset()
110 writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); in nmdk_clkevt_reset()
112 writel(MTU_CRn_PERIODIC | clk_prescale | in nmdk_clkevt_reset()
115 writel(1 << 1, mtu_base + MTU_IMSC); in nmdk_clkevt_reset()
135 writel(0, mtu_base + MTU_IMSC); in nmdk_clkevt_mode()
137 writel(0, mtu_base + MTU_CR(1)); in nmdk_clkevt_mode()
139 writel(0xffffffff, mtu_base + MTU_LR(1)); in nmdk_clkevt_mode()
[all …]
Dtimer-integrator-ap.c49 writel(0xffff, base + TIMER_LOAD); in integrator_clocksource_init()
50 writel(ctrl, base + TIMER_CTRL); in integrator_clocksource_init()
70 writel(1, clkevt_base + TIMER_INTCLR); in integrator_timer_interrupt()
82 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_set_mode()
87 writel(timer_reload, clkevt_base + TIMER_LOAD); in clkevt_set_mode()
89 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_set_mode()
94 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_set_mode()
110 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); in clkevt_set_next_event()
111 writel(next, clkevt_base + TIMER_LOAD); in clkevt_set_next_event()
112 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); in clkevt_set_next_event()
[all …]
Dmoxart_timer.c67 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_mode()
68 writel(~0, base + TIMER1_BASE + REG_LOAD); in moxart_clkevt_mode()
71 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); in moxart_clkevt_mode()
72 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_mode()
77 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_mode()
87 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_next_event()
90 writel(u, base + TIMER1_BASE + REG_MATCH1); in moxart_clkevt_next_event()
92 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_next_event()
150 writel(~0, base + TIMER2_BASE + REG_LOAD); in moxart_timer_init()
151 writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); in moxart_timer_init()
Dvt8500_timer.c60 writel(3, regbase + TIMER_CTRL_VAL); in vt8500_timer_read()
83 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); in vt8500_timer_set_next_event()
88 writel(1, regbase + TIMER_IER_VAL); in vt8500_timer_set_next_event()
103 writel(readl(regbase + TIMER_CTRL_VAL) | 1, in vt8500_timer_set_mode()
105 writel(0, regbase + TIMER_IER_VAL); in vt8500_timer_set_mode()
121 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_interrupt()
151 writel(1, regbase + TIMER_CTRL_VAL); in vt8500_timer_init()
152 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_init()
153 writel(~0, regbase + TIMER_MATCH_VAL); in vt8500_timer_init()
Dtime-armada-370-xp.c91 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
110 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); in armada_370_xp_clkevt_next_event()
115 writel(delta, local_base + TIMER0_VAL_OFF); in armada_370_xp_clkevt_next_event()
133 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF); in armada_370_xp_clkevt_mode()
134 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF); in armada_370_xp_clkevt_mode()
149 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); in armada_370_xp_clkevt_mode()
162 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); in armada_370_xp_timer_interrupt()
238 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); in armada_370_xp_timer_resume()
239 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); in armada_370_xp_timer_resume()
240 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF); in armada_370_xp_timer_resume()
[all …]
Dmtk_timer.c73 writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + in mtk_clkevt_time_stop()
80 writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); in mtk_clkevt_time_setup()
89 writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); in mtk_clkevt_time_start()
101 writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, in mtk_clkevt_time_start()
145 writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); in mtk_timer_interrupt()
154 writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); in mtk_timer_global_reset()
156 writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); in mtk_timer_global_reset()
162 writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, in mtk_timer_setup()
165 writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, in mtk_timer_setup()
168 writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); in mtk_timer_setup()
[all …]
Darm_global_timer.c97 writel(ctrl, gt_base + GT_CONTROL); in gt_compare_set()
98 writel(lower_32_bits(counter), gt_base + GT_COMP0); in gt_compare_set()
99 writel(upper_32_bits(counter), gt_base + GT_COMP1); in gt_compare_set()
102 writel(delta, gt_base + GT_AUTO_INC); in gt_compare_set()
107 writel(ctrl, gt_base + GT_CONTROL); in gt_compare_set()
125 writel(ctrl, gt_base + GT_CONTROL); in gt_clockevent_set_mode()
213 writel(0, gt_base + GT_CONTROL); in gt_clocksource_init()
214 writel(0, gt_base + GT_COUNTER0); in gt_clocksource_init()
215 writel(0, gt_base + GT_COUNTER1); in gt_clocksource_init()
217 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); in gt_clocksource_init()
Dsun4i_timer.c62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_stop()
68 writel(delay, timer_base + TIMER_INTVAL_REG(timer)); in sun4i_clkevt_time_setup()
80 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, in sun4i_clkevt_time_start()
128 writel(0x1, timer_base + TIMER_IRQ_ST_REG); in sun4i_timer_interrupt()
168 writel(~0, timer_base + TIMER_INTVAL_REG(1)); in sun4i_timer_init()
169 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | in sun4i_timer_init()
187 writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), in sun4i_timer_init()
205 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); in sun4i_timer_init()
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
Despi.c65 writel(V_WRITE_DATA(wr_data) | in tricn_write()
71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
111 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, in tricn_init()
129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
[all …]
Dtp.c31 writel(val, ap->regs + A_TP_IN_CONFIG); in tp_init()
32 writel(F_TP_OUT_CSPI_CPL | in tp_init()
36 writel(V_IP_TTL(64) | in tp_init()
46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | in tp_init()
77 writel(0xffffffff, in t1_tp_intr_enable()
79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_enable()
85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable()
86 writel(tp_intr | F_PL_INTR_TP, in t1_tp_intr_enable()
98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_disable()
99 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_disable()
[all …]
/linux-4.1.27/arch/arm/mach-pxa/
Dcm-x2xx-pci.c136 writel(0x848, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
137 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
140 writel(0x840, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
141 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
143 writel(0x20, IT8152_GPIO_GPDR); in cmx2xx_pci_preinit()
146 writel(0x4000, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
151 writel(0x408C, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
152 writel(0x1022, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
154 writel(0x4080, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
155 writel(0x3844d060, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit()
[all …]
/linux-4.1.27/arch/unicore32/kernel/
Dirq.c68 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); in puv3_gpio_type()
69 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); in puv3_gpio_type()
79 writel((1 << d->irq), GPIO_GEDR); in puv3_low_gpio_ack()
84 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); in puv3_low_gpio_mask()
89 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); in puv3_low_gpio_unmask()
95 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
97 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); in puv3_low_gpio_wake()
126 writel(mask, GPIO_GEDR); in puv3_gpio_handler()
148 writel(mask, GPIO_GEDR); in puv3_high_gpio_ack()
157 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); in puv3_high_gpio_mask()
[all …]
Dtime.c29 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_ost0_interrupt()
30 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_ost0_interrupt()
41 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); in puv3_osmr0_set_next_event()
43 writel(next, OST_OSMR0); in puv3_osmr0_set_next_event()
56 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_osmr0_set_mode()
57 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_osmr0_set_mode()
96 writel(0, OST_OIER); /* disable any timer interrupts */ in time_init()
97 writel(0, OST_OSSR); /* clear status on all timers */ in time_init()
127 writel(0, OST_OSSR); in puv3_timer_resume()
128 writel(osmr[0], OST_OSMR0); in puv3_timer_resume()
[all …]
Dpci.c32 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_read_config()
51 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_write_config()
54 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) in puv3_write_config()
58 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) in puv3_write_config()
62 writel(value, PCICFG_DATA); in puv3_write_config()
77 writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); in pci_puv3_preinit()
79 writel(0, PCIBRI_AHBCTL0); in pci_puv3_preinit()
80 writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); in pci_puv3_preinit()
81 writel(0xFFFF0000, PCIBRI_AHBAMR0); in pci_puv3_preinit()
82 writel(0, PCIBRI_AHBTAR0); in pci_puv3_preinit()
[all …]
Dgpio.c61 writel(GPIO_GPIO(offset), GPIO_GPSR); in puv3_gpio_set()
63 writel(GPIO_GPIO(offset), GPIO_GPCR); in puv3_gpio_set()
71 writel(readl(GPIO_GPDR) & ~GPIO_GPIO(offset), GPIO_GPDR); in puv3_direction_input()
83 writel(readl(GPIO_GPDR) | GPIO_GPIO(offset), GPIO_GPDR); in puv3_direction_output()
100 writel(GPIO_DIR, GPIO_GPDR); in puv3_init_gpio()
/linux-4.1.27/drivers/media/platform/s5p-jpeg/
Djpeg-hw-exynos3250.c26 writel(1, regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
38 writel(1, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
44 writel(0, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
49 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON); in exynos3250_jpeg_poweron()
54 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) & in exynos3250_jpeg_set_dma_num()
69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
120 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_input_raw_fmt()
132 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_set_y16()
146 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_proc_mode()
168 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_subsampling_mode()
[all …]
Djpeg-hw-exynos4.c24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
118 writel(reg, base + EXYNOS4_IMG_FMT_REG); in exynos4_jpeg_set_img_fmt()
149 writel(reg, base + EXYNOS4_IMG_FMT_REG); in exynos4_jpeg_set_enc_out_fmt()
154 writel(EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt()
182 writel(reg | EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable()
185 writel(reg & ~EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable()
196 writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_sys_int_enable()
[all …]
Djpeg-hw-s5p.c24 writel(1, regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
35 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); in s5p_jpeg_poweron()
51 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
66 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
81 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
96 writel(reg, regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
101 writel(reg, regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
111 writel(reg, regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
122 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
133 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_dc()
[all …]
/linux-4.1.27/arch/arm/mach-netx/
Dtime.c43 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in netx_set_mode()
47 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); in netx_set_mode()
54 writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); in netx_set_mode()
70 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in netx_set_mode()
76 writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); in netx_set_next_event()
96 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); in netx_timer_interrupt()
115 writel(0, NETX_GPIO_COUNTER_CTRL(0)); in netx_timer_init()
118 writel(0, NETX_GPIO_COUNTER_CURRENT(0)); in netx_timer_init()
120 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0)); in netx_timer_init()
123 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); in netx_timer_init()
[all …]
Dgeneric.c117 writel(val, NETX_DPMAS_IF_CONF1); in netx_hif_irq_type()
128 writel((1 << 24) << irq, NETX_DPMAS_INT_STAT); in netx_hif_ack_irq()
132 writel(val, NETX_DPMAS_INT_EN); in netx_hif_ack_irq()
145 writel(val, NETX_DPMAS_INT_EN); in netx_hif_mask_irq()
157 writel(val, NETX_DPMAS_INT_EN); in netx_hif_unmask_irq()
180 writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); in netx_init_irq()
193 writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, in netx_restart()
/linux-4.1.27/drivers/scsi/bfa/
Dbfa_ioc_ct.c73 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
75 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
76 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
95 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
104 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
106 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
124 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
128 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
138 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
139 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
[all …]
Dbfa_ioc_cb.c121 writel(~0U, ioc->ioc_regs.err_set); in bfa_ioc_cb_notify_fail()
234 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_start()
235 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); in bfa_ioc_cb_sync_start()
255 writel(1, ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_cb_ownership_reset()
267 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_join()
276 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_leave()
285 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_cur_ioc_fwstate()
302 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_alt_ioc_fwstate()
378 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_cb_pll_init()
381 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_cb_pll_init()
[all …]
/linux-4.1.27/drivers/net/ethernet/brocade/bna/
Dbfa_ioc_ct.c140 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
142 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
166 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
191 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
200 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
201 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
428 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
438 writel(1, ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
461 writel(r32 & __MSIX_VT_OFST_, in bfa_nw_ioc_ct2_poweron()
466 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | in bfa_nw_ioc_ct2_poweron()
[all …]
Dbna_hw_defs.h167 writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
174 writel(0xffffffff, (_bna)->regs.fn_int_mask); \
178 writel((new_mask), (bna)->regs.fn_int_mask)
183 writel((mask | (bna)->bits.mbox_mask_bits | \
192 writel((mask & ~((bna)->bits.mbox_mask_bits | \
201 writel(((_status) & ~(_bna)->bits.mbox_status_bits), \
233 (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
238 (writel(((_i_dbell)->doorbell_ack | (_events)), \
260 writel(BNA_DOORBELL_IB_INT_DISABLE, \
270 (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
[all …]
/linux-4.1.27/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_lowlevel.c40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_set_interrupt_mask()
100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); in exynos_mipi_dsi_set_phy_tunning()
128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_stand_by()
139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_disp_resol()
145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_disp_resol()
[all …]
/linux-4.1.27/arch/m68k/coldfire/
Dm53xx.c311 writel(0x77777777, MCF_SCM_MPR); in scm_init()
315 writel(0, MCF_SCM_PACRA); in scm_init()
316 writel(0, MCF_SCM_PACRB); in scm_init()
317 writel(0, MCF_SCM_PACRC); in scm_init()
318 writel(0, MCF_SCM_PACRD); in scm_init()
319 writel(0, MCF_SCM_PACRE); in scm_init()
320 writel(0, MCF_SCM_PACRF); in scm_init()
323 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); in scm_init()
332 writel(0x10080000, MCF_FBCS1_CSAR); in fbcs_init()
334 writel(0x002A3780, MCF_FBCS1_CSCR); in fbcs_init()
[all …]
Dintc-5272.c89 writel(v, intc_irqmap[irq].icr); in intc_irq_mask()
101 writel(v, intc_irqmap[irq].icr); in intc_irq_unmask()
117 writel(v, intc_irqmap[irq].icr); in intc_irq_ack()
135 writel(v, MCFSIM_PITR); in intc_irq_set_type()
166 writel(0x88888888, MCFSIM_ICR1); in init_IRQ()
167 writel(0x88888888, MCFSIM_ICR2); in init_IRQ()
168 writel(0x88888888, MCFSIM_ICR3); in init_IRQ()
169 writel(0x88888888, MCFSIM_ICR4); in init_IRQ()
/linux-4.1.27/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr_v6.c38 #undef writel
39 #define writel(v, r) \ macro
414 writel(strm_size, mfc_regs->d_stream_data_size); in s5p_mfc_set_dec_stream_buffer_v6()
415 writel(buf_addr, mfc_regs->d_cpb_buffer_addr); in s5p_mfc_set_dec_stream_buffer_v6()
416 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); in s5p_mfc_set_dec_stream_buffer_v6()
417 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); in s5p_mfc_set_dec_stream_buffer_v6()
441 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); in s5p_mfc_set_dec_frame_buffer_v6()
442 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
443 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
445 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); in s5p_mfc_set_dec_frame_buffer_v6()
[all …]
/linux-4.1.27/drivers/video/fbdev/geode/
Ddisplay_gx1.c90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
97 writel(tcfg, par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
135 writel(0, par->dc_regs + DC_FB_ST_OFFSET); in gx1_set_mode()
138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); in gx1_set_mode()
139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, in gx1_set_mode()
166 writel(val, par->dc_regs + DC_H_TIMING_1); in gx1_set_mode()
168 writel(val, par->dc_regs + DC_H_TIMING_2); in gx1_set_mode()
[all …]
Dvideo_cs5530.c92 writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG); in cs5530_set_dclk_frequency()
93 writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */ in cs5530_set_dclk_frequency()
95 writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */ in cs5530_set_dclk_frequency()
96 writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */ in cs5530_set_dclk_frequency()
134 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_configure_display()
184 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_blank_display()
/linux-4.1.27/drivers/gpu/drm/sti/
Dsti_vtg.c121 writel(1, vtg->regs + VTG_DRST_AUTOC); in vtg_reset()
132 writel(mode->htotal, vtg->regs + VTG_CLKLN); in vtg_set_mode()
133 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); in vtg_set_mode()
137 writel(tmp, vtg->regs + VTG_VID_TFO); in vtg_set_mode()
138 writel(tmp, vtg->regs + VTG_VID_BFO); in vtg_set_mode()
142 writel(tmp, vtg->regs + VTG_VID_TFS); in vtg_set_mode()
143 writel(tmp, vtg->regs + VTG_VID_BFS); in vtg_set_mode()
148 writel(tmp, vtg->regs + VTG_H_HD_1); in vtg_set_mode()
152 writel(tmp, vtg->regs + VTG_TOP_V_VD_1); in vtg_set_mode()
153 writel(tmp, vtg->regs + VTG_BOT_V_VD_1); in vtg_set_mode()
[all …]
Dsti_vid.c53 writel(val, vid->regs + VID_CTL); in sti_vid_prepare_layer()
68 writel((ydo << 16) | xdo, vid->regs + VID_VPO); in sti_vid_commit_layer()
69 writel((yds << 16) | xds, vid->regs + VID_VPS); in sti_vid_commit_layer()
81 writel(val, vid->regs + VID_CTL); in sti_vid_disable_layer()
99 writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL); in sti_vid_init()
102 writel(VID_ALP_OPAQUE, vid->regs + VID_ALP); in sti_vid_init()
105 writel(VID_MPR0_BT709, vid->regs + VID_MPR0); in sti_vid_init()
106 writel(VID_MPR1_BT709, vid->regs + VID_MPR1); in sti_vid_init()
107 writel(VID_MPR2_BT709, vid->regs + VID_MPR2); in sti_vid_init()
108 writel(VID_MPR3_BT709, vid->regs + VID_MPR3); in sti_vid_init()
[all …]
Dsti_vtac.c95 writel(VTAC_FIFO_CONFIG_VAL, vtac->regs + VTAC_RX_FIFO_CONFIG); in sti_vtac_rx_set_config()
101 writel(config, vtac->regs + VTAC_CONFIG); in sti_vtac_rx_set_config()
115 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8522); in sti_vtac_tx_set_config()
117 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config()
120 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config()
123 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config()
126 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config()
129 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config()
136 writel(config, vtac->regs + VTAC_CONFIG); in sti_vtac_tx_set_config()
Dsti_hqvdp.c654 writel(hqvdp->hqvdp_cmd_paddr + cmd_offset, in sti_hqvdp_commit_layer()
682 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); in sti_hqvdp_disable_layer()
748 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset, in sti_hqvdp_vtg_cb()
824 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE); in sti_hqvdp_init_plugs()
825 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC); in sti_hqvdp_init_plugs()
826 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC); in sti_hqvdp_init_plugs()
827 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK); in sti_hqvdp_init_plugs()
828 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG); in sti_hqvdp_init_plugs()
829 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE); in sti_hqvdp_init_plugs()
830 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL); in sti_hqvdp_init_plugs()
[all …]
/linux-4.1.27/drivers/net/hippi/
Drrunner.c189 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, in rr_init_one()
231 writel(HALT_NIC, &rr->regs->HostCtrl); in rr_remove_one()
272 writel(*(u32*)(cmd), &regs->CmdRing[idx]); in rr_issue_cmd()
300 writel(0x01000000, &regs->TX_state); in rr_reset()
301 writel(0xff800000, &regs->RX_state); in rr_reset()
302 writel(0, &regs->AssistState); in rr_reset()
303 writel(CLEAR_INTA, &regs->LocalCtrl); in rr_reset()
304 writel(0x01, &regs->BrkPt); in rr_reset()
305 writel(0, &regs->Timer); in rr_reset()
306 writel(0, &regs->TimerRef); in rr_reset()
[all …]
/linux-4.1.27/arch/arm/plat-orion/
Dtime.c86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_next_event()
90 writel(u, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event()
95 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event()
102 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event()
120 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_mode()
121 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_mode()
127 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
133 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, in orion_clkevt_mode()
140 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); in orion_clkevt_mode()
146 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_mode()
[all …]
Dpcie.c89 writel(stat, base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
105 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
115 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset()
135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); in orion_pcie_setup_wins()
136 writel(0, base + PCIE_BAR_LO_OFF(i)); in orion_pcie_setup_wins()
137 writel(0, base + PCIE_BAR_HI_OFF(i)); in orion_pcie_setup_wins()
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); in orion_pcie_setup_wins()
142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); in orion_pcie_setup_wins()
146 writel(0, base + PCIE_WIN5_CTRL_OFF); in orion_pcie_setup_wins()
[all …]
/linux-4.1.27/drivers/spi/
Dspi-sirf.c203 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); in spi_sirfsoc_tx_word_u8()
232 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); in spi_sirfsoc_tx_word_u16()
262 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); in spi_sirfsoc_tx_word_u32()
272 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); in spi_sirfsoc_irq()
273 writel(SIRFSOC_SPI_INT_MASK_ALL, in spi_sirfsoc_irq()
283 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); in spi_sirfsoc_irq()
284 writel(SIRFSOC_SPI_INT_MASK_ALL, in spi_sirfsoc_irq()
294 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); in spi_sirfsoc_irq()
295 writel(SIRFSOC_SPI_INT_MASK_ALL, in spi_sirfsoc_irq()
316 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); in spi_sirfsoc_cmd_transfer()
[all …]
Dspi-altera.c76 writel(1 << spi->chip_select, in altera_spi_chipsel()
79 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel()
84 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel()
85 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL); in altera_spi_chipsel()
92 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel()
96 writel(1 << spi->chip_select, in altera_spi_chipsel()
99 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel()
132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_txrx()
135 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA); in altera_spi_txrx()
140 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_txrx()
[all …]
Dspi-mxs.c98 writel(BM_SSP_CTRL0_LOCK_CS, in mxs_spi_setup_transfer()
101 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | in mxs_spi_setup_transfer()
107 writel(0x0, ssp->base + HW_SSP_CMD0); in mxs_spi_setup_transfer()
108 writel(0x0, ssp->base + HW_SSP_CMD1); in mxs_spi_setup_transfer()
313 writel(BM_SSP_CTRL0_IGNORE_CRC, in mxs_spi_txrx_pio()
318 writel(BM_SSP_CTRL0_IGNORE_CRC, in mxs_spi_txrx_pio()
322 writel(BM_SSP_CTRL0_XFER_COUNT, in mxs_spi_txrx_pio()
324 writel(1, in mxs_spi_txrx_pio()
327 writel(1, ssp->base + HW_SSP_XFER_SIZE); in mxs_spi_txrx_pio()
331 writel(BM_SSP_CTRL0_READ, in mxs_spi_txrx_pio()
[all …]
Dspi-s3c64xx.c206 writel(0, regs + S3C64XX_SPI_PACKET_CNT); in flush_fifo()
210 writel(val, regs + S3C64XX_SPI_CH_CFG); in flush_fifo()
215 writel(val, regs + S3C64XX_SPI_CH_CFG); in flush_fifo()
241 writel(val, regs + S3C64XX_SPI_CH_CFG); in flush_fifo()
245 writel(val, regs + S3C64XX_SPI_MODE_CFG); in flush_fifo()
396 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in enable_datapath()
435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in enable_datapath()
442 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); in enable_datapath()
443 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); in enable_datapath()
585 writel(val, regs + S3C64XX_SPI_CLK_CFG); in s3c64xx_spi_config()
[all …]
/linux-4.1.27/sound/soc/ux500/
Dux500_msp_i2s.c144 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
172 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
214 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
261 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
298 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel()
301 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
303 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
[all …]
/linux-4.1.27/drivers/irqchip/
Dirq-sun4i.c48 writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_irq_ack()
59 writel(val & ~(1 << irq_off), in sun4i_irq_mask()
71 writel(val | (1 << irq_off), in sun4i_irq_unmask()
106 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); in sun4i_of_init()
107 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); in sun4i_of_init()
108 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); in sun4i_of_init()
111 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); in sun4i_of_init()
112 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); in sun4i_of_init()
113 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); in sun4i_of_init()
116 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_of_init()
[all …]
Dirq-vic.c106 writel(VIC_VECT_CNTL_ENABLE | i, reg); in vic_init2()
109 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
122 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
123 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
126 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
127 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); in resume_one_vic()
131 writel(vic->soft_int, base + VIC_INT_SOFT); in resume_one_vic()
132 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); in resume_one_vic()
157 writel(vic->resume_irqs, base + VIC_INT_ENABLE); in suspend_one_vic()
158 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); in suspend_one_vic()
[all …]
Dirq-armada-370-xp.c104 writel(hwirq, main_int_base + in armada_370_xp_irq_mask()
107 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_mask()
116 writel(hwirq, main_int_base + in armada_370_xp_irq_unmask()
119 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_unmask()
250 writel(reg, per_cpu_int_base + in armada_370_xp_msi_init()
254 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); in armada_370_xp_msi_init()
283 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); in armada_xp_set_affinity()
306 writel(hw, per_cpu_int_base + in armada_370_xp_mpic_irq_map()
309 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); in armada_370_xp_mpic_irq_map()
335 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); in armada_xp_mpic_smp_cpu_init()
[all …]
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_dma.c41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
69 writel(upper_32_bits(dma_tx), in sxgbe_dma_channel_init()
71 writel(lower_32_bits(dma_tx), in sxgbe_dma_channel_init()
74 writel(upper_32_bits(dma_rx), in sxgbe_dma_channel_init()
76 writel(lower_32_bits(dma_rx), in sxgbe_dma_channel_init()
84 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
88 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init()
[all …]
Dsxgbe_mtl.c43 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
53 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
59 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); in sxgbe_mtl_dma_dm_rxqueue()
60 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); in sxgbe_mtl_dma_dm_rxqueue()
61 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); in sxgbe_mtl_dma_dm_rxqueue()
73 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
85 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_rxfifosize()
94 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_enable_txqueue()
103 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_disable_txqueue()
115 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_active()
[all …]
Dsxgbe_core.c34 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
43 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
99 writel(high_word, ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); in sxgbe_core_set_umac_addr()
100 writel(low_word, ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); in sxgbe_core_set_umac_addr()
129 writel(tx_config, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx()
141 writel(rx_config, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx()
165 writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_set_speed()
175 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_enable_rxqueue()
185 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_disable_rxqueue()
199 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode()
[all …]
/linux-4.1.27/drivers/media/platform/exynos-gsc/
Dgsc-regs.c20 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset()
47 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
59 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
71 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK); in gsc_hw_set_input_buf_masking()
72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK); in gsc_hw_set_input_buf_masking()
73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK); in gsc_hw_set_input_buf_masking()
85 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); in gsc_hw_set_output_buf_masking()
86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK); in gsc_hw_set_output_buf_masking()
87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK); in gsc_hw_set_output_buf_masking()
95 writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index)); in gsc_hw_set_input_addr()
[all …]
/linux-4.1.27/arch/mips/ar7/
Dirq.c54 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_unmask_irq()
60 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_mask_irq()
66 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_ack_irq()
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
111 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
112 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
114 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init()
[all …]
Dgpio.c61 writel(tmp, gpio_out); in ar7_gpio_set_value()
76 writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); in titan_gpio_set_value()
85 writel(readl(gpio_dir) | (1 << gpio), gpio_dir); in ar7_gpio_direction_input()
100 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), in titan_gpio_direction_input()
113 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); in ar7_gpio_direction_output()
130 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << in titan_gpio_direction_output()
164 writel(readl(gpio_en) | (1 << gpio), gpio_en); in ar7_gpio_enable_ar7()
174 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), in ar7_gpio_enable_titan()
191 writel(readl(gpio_en) & ~(1 << gpio), gpio_en); in ar7_gpio_disable_ar7()
201 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), in ar7_gpio_disable_titan()
[all …]
Dclock.c241 writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); in tnetd7300_set_clock()
243 writel(4, &clock->pll); in tnetd7300_set_clock()
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); in tnetd7300_set_clock()
282 writel(0, &clock->ctrl); in tnetd7200_set_clock()
283 writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv); in tnetd7200_set_clock()
284 writel((mul - 1) & 0xF, &clock->mul); in tnetd7200_set_clock()
289 writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv); in tnetd7200_set_clock()
291 writel(readl(&clock->cmden) | 1, &clock->cmden); in tnetd7200_set_clock()
292 writel(readl(&clock->cmd) | 1, &clock->cmd); in tnetd7200_set_clock()
297 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); in tnetd7200_set_clock()
[all …]
/linux-4.1.27/arch/arm/mach-cns3xxx/
Dcore.c107 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
126 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_timer_set_mode()
139 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_mode()
147 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_timer_set_next_event()
148 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
181 writel(val & ~(1 << 2), stat); in cns3xxx_timer_interrupt()
207 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
209 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); in __cns3xxx_timer_init()
212 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); in __cns3xxx_timer_init()
213 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in __cns3xxx_timer_init()
[all …]
/linux-4.1.27/drivers/media/platform/exynos4-is/
Dfimc-reg.c28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
97 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation()
103 writel(flip, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_rotation()
142 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format()
147 writel(cfg, dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format()
157 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); in fimc_hw_set_out_dma_size()
165 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size()
179 writel(cfg, dev->regs + FIMC_REG_CIOYOFF); in fimc_hw_set_out_dma()
[all …]
Dfimc-lite-reg.c30 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
40 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
47 writel(cfg, dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq()
61 writel(cfg, dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end()
83 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask()
90 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_start()
97 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_stop()
111 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern()
150 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format()
157 writel(cfg, dev->regs + FLITE_REG_CISRCSIZE); in flite_hw_set_source_format()
[all …]
/linux-4.1.27/sound/soc/samsung/
Ds3c24xx-i2s.c76 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_txctrl()
77 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_txctrl()
78 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_txctrl()
93 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_txctrl()
94 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_txctrl()
95 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_txctrl()
121 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_rxctrl()
122 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_rxctrl()
123 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_rxctrl()
138 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_rxctrl()
[all …]
Ds3c-i2s-v2.c113 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_txctrl()
114 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_txctrl()
142 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_txctrl()
143 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_txctrl()
185 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_rxctrl()
186 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_rxctrl()
210 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_rxctrl()
211 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_rxctrl()
295 writel(iismod, i2s->regs + S3C2412_IISMOD); in s3c2412_i2s_set_fmt()
334 writel(iismod, i2s->regs + S3C2412_IISMOD); in s3c_i2sv2_hw_params()
[all …]
Dac97.c65 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate()
69 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate()
74 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate()
94 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_read()
100 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_read()
131 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_write()
137 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_write()
144 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_write()
152 writel(S3C_AC97_GLBCTRL_COLDRESET, in s3c_ac97_cold_reset()
156 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_cold_reset()
[all …]
/linux-4.1.27/drivers/gpu/ipu-v3/
Dipu-dp.c101 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha()
105 writel(reg | ((u32) alpha << 24), in ipu_dp_set_global_alpha()
109 writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha()
112 writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha()
128 writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS); in ipu_dp_set_window_pos()
147 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_csc_init()
152 writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0); in ipu_dp_csc_init()
153 writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1); in ipu_dp_csc_init()
154 writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2); in ipu_dp_csc_init()
155 writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3); in ipu_dp_csc_init()
[all …]
Dipu-dc.c127 writel(reg, dc->base + DC_RL_CH(event)); in dc_link_event()
146 writel(reg1, priv->dc_tmpl_reg + word * 8); in dc_write_tmpl()
147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); in dc_write_tmpl()
225 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync()
227 writel(0x0, dc->base + DC_WR_CH_ADDR); in ipu_dc_init_sync()
228 writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di)); in ipu_dc_init_sync()
258 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel()
269 writel(reg, dc->base + DC_WR_CH_CONF); in dc_irq_handler()
301 writel(val, dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel()
332 writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
[all …]
/linux-4.1.27/sound/soc/fsl/
Dimx-ssi.c70 writel(sccr, ssi->base + SSI_STCCR); in imx_ssi_set_dai_tdm_slot()
75 writel(sccr, ssi->base + SSI_SRCCR); in imx_ssi_set_dai_tdm_slot()
77 writel(~tx_mask, ssi->base + SSI_STMSK); in imx_ssi_set_dai_tdm_slot()
78 writel(~rx_mask, ssi->base + SSI_SRMSK); in imx_ssi_set_dai_tdm_slot()
153 writel(strcr, ssi->base + SSI_STCR); in imx_ssi_set_dai_fmt()
154 writel(strcr, ssi->base + SSI_SRCR); in imx_ssi_set_dai_fmt()
155 writel(scr, ssi->base + SSI_SCR); in imx_ssi_set_dai_fmt()
183 writel(scr, ssi->base + SSI_SCR); in imx_ssi_set_dai_sysclk()
230 writel(stccr, ssi->base + SSI_STCCR); in imx_ssi_set_dai_clkdiv()
231 writel(srccr, ssi->base + SSI_SRCCR); in imx_ssi_set_dai_clkdiv()
[all …]
/linux-4.1.27/drivers/net/ethernet/sun/
Dsungem.c128 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_read()
166 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_write()
191 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_enable_ints()
197 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_disable_ints()
368 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_rxmac_reset()
379 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, in gem_rxmac_reset()
392 writel(0, gp->regs + RXDMA_CFG); in gem_rxmac_reset()
406 writel(gp->swrst_base | GREG_SWRST_RXRST, in gem_rxmac_reset()
434 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_rxmac_reset()
435 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_rxmac_reset()
[all …]
Dcassini.c298 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); in cas_disable_irq()
315 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, in cas_disable_irq()
320 writel(INTRN_MASK_CLEAR_ALL, cp->regs + in cas_disable_irq()
338 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); in cas_enable_irq()
354 writel(INTRN_MASK_RX_EN, cp->regs + in cas_enable_irq()
390 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, in cas_entropy_reset()
413 writel(cmd, cp->regs + REG_MIF_FRAME); in cas_phy_read()
435 writel(cmd, cp->regs + REG_MIF_FRAME); in cas_phy_write()
688 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, in cas_mif_poll()
690 writel(cfg, cp->regs + REG_MIF_CFG); in cas_mif_poll()
[all …]
/linux-4.1.27/drivers/gpio/
Dgpio-sta2x11.c82 writel(bit, &regs->dats); in gsta_gpio_set()
84 writel(bit, &regs->datc); in gsta_gpio_set()
103 writel(bit, &regs->dirs); in gsta_gpio_direction_output()
106 writel(bit, &regs->dats); in gsta_gpio_direction_output()
108 writel(bit, &regs->datc); in gsta_gpio_direction_output()
118 writel(bit, &regs->dirc); in gsta_gpio_direction_input()
186 writel(val | bit, &regs->afsela); in gsta_set_config()
195 writel(bit, &regs->dirs); in gsta_set_config()
196 writel(bit, &regs->datc); in gsta_set_config()
199 writel(bit, &regs->dirs); in gsta_set_config()
[all …]
/linux-4.1.27/drivers/mtd/spi-nor/
Dfsl-quadspi.c259 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_unlock_lut()
260 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_unlock_lut()
265 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_lock_lut()
266 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_lock_lut()
276 writel(reg, q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler()
297 writel(0, base + QUADSPI_LUT_BASE + i * 4); in fsl_qspi_init_lut()
313 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
315 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo), in fsl_qspi_init_lut()
320 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
334 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
[all …]
/linux-4.1.27/drivers/isdn/hisax/
Dtelespci.c51 writel(WRITE_ADDR_ISAC | off, adr + 0x200); in readisac()
55 writel(READ_DATA_ISAC, adr + 0x200); in readisac()
68 writel(WRITE_ADDR_ISAC | off, adr + 0x200); in writeisac()
72 writel(WRITE_DATA_ISAC | data, adr + 0x200); in writeisac()
83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in readhscx()
87 writel(READ_DATA_HSCX, adr + 0x200); in readhscx()
99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in writehscx()
103 writel(WRITE_DATA_HSCX | data, adr + 0x200); in writehscx()
117 writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200); in read_fifo_isac()
119 writel(READ_DATA_ISAC, adr + 0x200); in read_fifo_isac()
[all …]
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
Dstmmac_hwtstamp.c33 writel(data, ioaddr + PTP_TCR); in stmmac_config_hw_tstamping()
51 writel(data, ioaddr + PTP_SSIR); in stmmac_config_sub_second_increment()
59 writel(sec, ioaddr + PTP_STSUR); in stmmac_init_systime()
60 writel(nsec, ioaddr + PTP_STNSUR); in stmmac_init_systime()
64 writel(value, ioaddr + PTP_TCR); in stmmac_init_systime()
84 writel(addend, ioaddr + PTP_TAR); in stmmac_config_addend()
88 writel(value, ioaddr + PTP_TCR); in stmmac_config_addend()
109 writel(sec, ioaddr + PTP_STSUR); in stmmac_adjust_systime()
110 writel(((add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec), in stmmac_adjust_systime()
115 writel(value, ioaddr + PTP_TCR); in stmmac_adjust_systime()
Ddwmac_lib.c32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); in dwmac_enable_dma_transmission()
37 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
42 writel(0, ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq()
49 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
56 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
63 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
70 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
209 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); in dwmac_dma_interrupt()
217 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
232 writel(data | GMAC_HI_REG_AE, ioaddr + high); in stmmac_set_mac_addr()
[all …]
Ddwmac1000_dma.c41 writel(value, ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init()
76 writel(value, ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init()
95 writel(burst_len, ioaddr + DMA_AXI_BUS_MODE); in dwmac1000_dma_init()
98 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac1000_dma_init()
103 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); in dwmac1000_dma_init()
104 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); in dwmac1000_dma_init()
180 writel(csr6, ioaddr + DMA_CONTROL); in dwmac1000_dma_operation_mode()
204 writel(riwt, ioaddr + DMA_RX_WATCHDOG); in dwmac1000_rx_watchdog()
Ddwmac1000_core.c45 writel(value, ioaddr + GMAC_CONTROL); in dwmac1000_core_init()
48 writel(0x207, ioaddr + GMAC_INT_MASK); in dwmac1000_core_init()
52 writel(0x0, ioaddr + GMAC_VLAN_TAG); in dwmac1000_core_init()
66 writel(value, ioaddr + GMAC_CONTROL); in dwmac1000_rx_ipc_enable()
111 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW); in dwmac1000_set_mchash()
112 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH); in dwmac1000_set_mchash()
127 writel(mcfilterbits[regs], in dwmac1000_set_mchash()
196 writel(value, ioaddr + GMAC_FRAME_FILTER); in dwmac1000_set_filter()
224 writel(flow, ioaddr + GMAC_FLOW_CTRL); in dwmac1000_flow_ctrl()
241 writel(pmt, ioaddr + GMAC_PMT); in dwmac1000_pmt()
[all …]
Ddwmac100_core.c40 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL); in dwmac100_core_init()
43 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1); in dwmac100_core_init()
112 writel(0xffffffff, ioaddr + MAC_HASH_HIGH); in dwmac100_set_filter()
113 writel(0xffffffff, ioaddr + MAC_HASH_LOW); in dwmac100_set_filter()
140 writel(mc_filter[0], ioaddr + MAC_HASH_LOW); in dwmac100_set_filter()
141 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH); in dwmac100_set_filter()
144 writel(value, ioaddr + MAC_CONTROL); in dwmac100_set_filter()
155 writel(flow, ioaddr + MAC_FLOW_CTRL); in dwmac100_flow_ctrl()
Ddwmac100_dma.c43 writel(value, ioaddr + DMA_BUS_MODE); in dwmac100_dma_init()
54 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), in dwmac100_dma_init()
58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac100_dma_init()
63 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); in dwmac100_dma_init()
64 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); in dwmac100_dma_init()
86 writel(csr6, ioaddr + DMA_CONTROL); in dwmac100_dma_operation_mode()
/linux-4.1.27/arch/arm/mach-integrator/
Dintegrator_ap.c126 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); in irq_resume()
127 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); in irq_resume()
129 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); in irq_resume()
157 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, in ap_flash_init()
162 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_init()
166 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); in ap_flash_init()
167 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_init()
168 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); in ap_flash_init()
177 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, in ap_flash_exit()
182 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_exit()
[all …]
/linux-4.1.27/arch/arm/mach-gemini/
Dtime.c50 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
53 writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); in gemini_timer_set_next_event()
54 writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); in gemini_timer_set_next_event()
57 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_next_event()
71 writel(period, in gemini_timer_set_mode()
73 writel(period, in gemini_timer_set_mode()
78 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
91 writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); in gemini_timer_set_mode()
159 writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); in gemini_timer_init()
160 writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); in gemini_timer_init()
[all …]
/linux-4.1.27/drivers/usb/host/
Dxhci-rcar.c67 writel(temp, hcd->regs + RCAR_USB3_INT_ENA); in xhci_rcar_start()
69 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK); in xhci_rcar_start()
71 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1); in xhci_rcar_start()
72 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2); in xhci_rcar_start()
73 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3); in xhci_rcar_start()
75 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL); in xhci_rcar_start()
76 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL); in xhci_rcar_start()
95 writel(temp, regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
103 writel(data, regs + RCAR_USB3_FW_DATA0); in xhci_rcar_download_firmware()
106 writel(temp, regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware()
[all …]
Dxhci-mvebu.c28 writel(0, base + USB3_WIN_CTRL(win)); in xhci_mvebu_mbus_config()
29 writel(0, base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config()
36 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in xhci_mvebu_mbus_config()
40 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config()
/linux-4.1.27/drivers/i2c/busses/
Di2c-bcm-kona.c176 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
182 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
189 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
196 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl()
208 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, in bcm_kona_i2c_enable_clock()
214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, in bcm_kona_i2c_disable_clock()
228 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, in bcm_kona_i2c_isr()
231 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); in bcm_kona_i2c_isr()
264 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); in bcm_kona_send_i2c_cmd()
276 writel(0, dev->base + IER_OFFSET); in bcm_kona_send_i2c_cmd()
[all …]
Di2c-sirf.c115 writel(regval, in i2c_sirfsoc_queue_cmd()
128 writel(regval, in i2c_sirfsoc_queue_cmd()
130 writel(siic->buf[siic->finished_len++], in i2c_sirfsoc_queue_cmd()
137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); in i2c_sirfsoc_queue_cmd()
148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq()
160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, in i2c_sirfsoc_irq()
175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq()
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address()
201 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address()
212 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, in i2c_sirfsoc_xfer_msg()
[all …]
Di2c-bcm-iproc.c114 writel(status, iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_isr()
172 writel(addr, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
183 writel(val, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
196 writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
209 writel(val, iproc_i2c->base + M_CMD_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
214 writel(0, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
227 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
236 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); in bcm_iproc_i2c_xfer_single_msg()
315 writel(val, iproc_i2c->base + TIM_CFG_OFFSET); in bcm_iproc_i2c_cfg_speed()
330 writel(val, iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_init()
[all …]
Di2c-axxia.c112 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); in i2c_int_disable()
120 writel(int_en | mask, idev->base + MST_INT_ENABLE); in i2c_int_enable()
145 writel(0x01, idev->base + SOFT_RESET); in axxia_i2c_init()
155 writel(0x1, idev->base + GLOBAL_CONTROL); in axxia_i2c_init()
170 writel(t_high, idev->base + SCL_HIGH_PERIOD); in axxia_i2c_init()
172 writel(t_low, idev->base + SCL_LOW_PERIOD); in axxia_i2c_init()
174 writel(t_setup, idev->base + SDA_SETUP_TIME); in axxia_i2c_init()
176 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); in axxia_i2c_init()
178 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); in axxia_i2c_init()
193 writel(prescale, idev->base + TIMER_CLOCK_DIV); in axxia_i2c_init()
[all …]
Di2c-qup.c142 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
151 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
157 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
162 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
165 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
217 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
254 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); in qup_i2c_set_write_mode()
255 writel(total, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_set_write_mode()
258 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN, in qup_i2c_set_write_mode()
260 writel(total, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_set_write_mode()
[all …]
Di2c-puv3.c62 writel(i2c_reg | I2C_DATACMD_WRITE, I2C_DATACMD); in xfer_read()
68 writel(I2C_DATACMD_READ, I2C_DATACMD); in xfer_read()
101 writel(i2c_reg | I2C_DATACMD_WRITE, I2C_DATACMD); in xfer_write()
104 writel(*buf | I2C_DATACMD_WRITE, I2C_DATACMD); in xfer_write()
128 writel(I2C_ENABLE_DISABLE, I2C_ENABLE); in puv3_i2c_xfer()
131 writel(I2C_CON_MASTER | I2C_CON_SPEED_STD | I2C_CON_SLAVEDISABLE, I2C_CON); in puv3_i2c_xfer()
133 writel(pmsg->addr, I2C_TAR); in puv3_i2c_xfer()
136 writel(I2C_ENABLE_ENABLE, I2C_ENABLE); in puv3_i2c_xfer()
252 writel(I2C_ENABLE_DISABLE, I2C_ENABLE); in puv3_i2c_suspend()
Di2c-pxa.c301 writel(icr, _ICR(i2c)); in i2c_pxa_abort()
309 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), in i2c_pxa_abort()
378 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); in i2c_pxa_set_master()
428 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); in i2c_pxa_set_slave()
438 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); in i2c_pxa_set_slave()
439 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); in i2c_pxa_set_slave()
458 writel(ICR_UR, _ICR(i2c)); in i2c_pxa_reset()
459 writel(I2C_ISR_INIT, _ISR(i2c)); in i2c_pxa_reset()
460 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); in i2c_pxa_reset()
463 writel(i2c->slave_addr, _ISAR(i2c)); in i2c_pxa_reset()
[all …]
Di2c-exynos5.c251 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq()
340 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); in exynos5_i2c_set_timing()
341 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); in exynos5_i2c_set_timing()
342 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
344 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); in exynos5_i2c_set_timing()
345 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); in exynos5_i2c_set_timing()
346 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
348 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); in exynos5_i2c_set_timing()
386 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
388 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), in exynos5_i2c_init()
[all …]
Di2c-nomadik.c202 writel(readl(reg) | mask, reg); in i2c_set_bit()
207 writel(readl(reg) & ~mask, reg); in i2c_clr_bit()
230 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); in flush_i2c_fifo()
256 writel(mask, dev->virtbase + I2C_IMSCR); in disable_all_interrupts()
267 writel(mask, dev->virtbase + I2C_ICR); in clear_all_interrupts()
358 writel(0x0, dev->virtbase + I2C_CR); in setup_i2c_controller()
359 writel(0x0, dev->virtbase + I2C_HSMCR); in setup_i2c_controller()
360 writel(0x0, dev->virtbase + I2C_TFTR); in setup_i2c_controller()
361 writel(0x0, dev->virtbase + I2C_RFTR); in setup_i2c_controller()
362 writel(0x0, dev->virtbase + I2C_DMAR); in setup_i2c_controller()
[all …]
Di2c-mv64xxx.c205 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); in mv64xxx_i2c_hw_init()
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); in mv64xxx_i2c_hw_init()
207 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init()
209 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init()
213 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); in mv64xxx_i2c_hw_init()
214 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), in mv64xxx_i2c_hw_init()
216 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); in mv64xxx_i2c_hw_init()
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); in mv64xxx_i2c_hw_init()
218 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, in mv64xxx_i2c_hw_init()
340 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, in mv64xxx_i2c_send_start()
[all …]
/linux-4.1.27/drivers/pci/host/
Dpci-xgene.c108 writel(rtdid_val, port->csr_base + RTDID); in xgene_pcie_set_rtdid_reg()
158 writel(val, csr_base + addr); in xgene_pcie_set_ib_mask()
162 writel(val, csr_base + addr + 0x04); in xgene_pcie_set_ib_mask()
166 writel(val, csr_base + addr + 0x04); in xgene_pcie_set_ib_mask()
170 writel(val, csr_base + addr + 0x08); in xgene_pcie_set_ib_mask()
253 writel(lower_32_bits(cpu_addr), base); in xgene_pcie_setup_ob_reg()
254 writel(upper_32_bits(cpu_addr), base + 0x04); in xgene_pcie_setup_ob_reg()
255 writel(lower_32_bits(mask), base + 0x08); in xgene_pcie_setup_ob_reg()
256 writel(upper_32_bits(mask), base + 0x0c); in xgene_pcie_setup_ob_reg()
257 writel(lower_32_bits(pci_addr), base + 0x10); in xgene_pcie_setup_ob_reg()
[all …]
Dpci-keystone-dw.c117 writel(BIT(bit_pos), in ks_dw_pcie_msi_irq_ack()
119 writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI); in ks_dw_pcie_msi_irq_ack()
128 writel(BIT(bit_pos), in ks_dw_pcie_msi_set_irq()
138 writel(BIT(bit_pos), in ks_dw_pcie_msi_clear_irq()
233 writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4)); in ks_dw_pcie_enable_legacy_irqs()
252 writel(offset, ks_pcie->va_app_base + IRQ_EOI); in ks_dw_pcie_handle_legacy_irq()
301 writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS), in ks_dw_pcie_set_dbi_mode()
319 writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS), in ks_dw_pcie_clear_dbi_mode()
335 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_setup_rc_app_regs()
336 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); in ks_dw_pcie_setup_rc_app_regs()
[all …]
Dpci-versatile.c100 writel(res->start >> 28, PCI_IMAP(mem)); in versatile_pci_parse_request_of_pci_ranges()
101 writel(PHYS_OFFSET >> 28, PCI_SMAP(mem)); in versatile_pci_parse_request_of_pci_ranges()
181 writel(myslot, PCI_SELFID); in versatile_pci_probe()
186 writel(val, local_pci_cfg_base + PCI_COMMAND); in versatile_pci_probe()
191 writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); in versatile_pci_probe()
192 writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); in versatile_pci_probe()
193 writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); in versatile_pci_probe()
206 writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE); in versatile_pci_probe()
Dpci-imx6.c106 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
109 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
116 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
137 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read()
147 writel(0x00, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read()
168 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write()
172 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write()
180 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write()
189 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write()
198 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write()
[all …]
/linux-4.1.27/drivers/ata/
Dahci_xgene.c101 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); in xgene_ahci_init_memram()
171 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
213 writel(port_fbs, port_mmio + PORT_FBS); in xgene_ahci_qc_issue()
283 writel(val, mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
286 writel(0x0001fffe, mmio + PORTPHY1CFG); in xgene_ahci_set_phy_cfg()
288 writel(0x28183219, mmio + PORTPHY2CFG); in xgene_ahci_set_phy_cfg()
290 writel(0x13081008, mmio + PORTPHY3CFG); in xgene_ahci_set_phy_cfg()
292 writel(0x00480815, mmio + PORTPHY4CFG); in xgene_ahci_set_phy_cfg()
297 writel(val, mmio + PORTPHY5CFG); in xgene_ahci_set_phy_cfg()
302 writel(val, mmio + PORTAXICFG); in xgene_ahci_set_phy_cfg()
[all …]
Dahci_mvebu.c37 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
38 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
39 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
45 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config()
48 writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
49 writel(((cs->size - 1) & 0xffff0000), in ahci_mvebu_mbus_config()
61 writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR); in ahci_mvebu_regret_option()
62 writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); in ahci_mvebu_regret_option()
Dahci_tegra.c184 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); in tegra_ahci_controller_init()
197 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra_ahci_controller_init()
207 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra_ahci_controller_init()
218 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra_ahci_controller_init()
221 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, in tegra_ahci_controller_init()
223 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, in tegra_ahci_controller_init()
226 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra_ahci_controller_init()
232 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); in tegra_ahci_controller_init()
234 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); in tegra_ahci_controller_init()
238 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); in tegra_ahci_controller_init()
[all …]
Dsata_sil24.c484 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); in sil24_dev_config()
486 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); in sil24_dev_config()
523 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); in sil24_scr_write()
535 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); in sil24_config_port()
537 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); in sil24_config_port()
548 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); in sil24_config_port()
551 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); in sil24_config_port()
559 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); in sil24_config_pmp()
561 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); in sil24_config_pmp()
569 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); in sil24_clear_pmp()
[all …]
Dsata_sx4.c507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
574 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in __pdc20621_push_hdma()
577 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT); in __pdc20621_push_hdma()
667 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in pdc20621_packet_start()
670 writel(port_ofs + PDC_DIMM_ATA_PKT, in pdc20621_packet_start()
750 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in pdc20621_host_intr()
752 writel(port_ofs + PDC_DIMM_ATA_PKT, in pdc20621_host_intr()
863 writel(tmp, mmio + PDC_CTLSTAT); in pdc_freeze()
880 writel(tmp, mmio + PDC_CTLSTAT); in pdc_thaw()
[all …]
/linux-4.1.27/drivers/misc/
Dspear13xx_pcie_gadget.c72 writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
74 writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access()
82 writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
84 writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access()
123 writel(val, va_address); in spear_dbi_write_reg()
242 writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID), in pcie_gadget_store_link()
245 writel(readl(&app_reg->app_ctrl_0) in pcie_gadget_store_link()
345 writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID), in pcie_gadget_store_inta()
348 writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID), in pcie_gadget_store_inta()
383 writel(ven_msi, &app_reg->ven_msi_1); in pcie_gadget_store_send_msi()
[all …]
Dtifm_7xx1.c54 writel(TIFM_IRQ_ENABLE, fm->addr + FM_CLEAR_INTERRUPT_ENABLE); in tifm_7xx1_isr()
69 writel(irq_status, fm->addr + FM_INTERRUPT_STATUS); in tifm_7xx1_isr()
74 writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE); in tifm_7xx1_isr()
87 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_toggle_sock_power()
101 writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED, in tifm_7xx1_toggle_sock_power()
109 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, in tifm_7xx1_toggle_sock_power()
121 writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED), in tifm_7xx1_toggle_sock_power()
129 writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL), in tifm_7xx1_sock_power_off()
175 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_switch_media()
202 writel(TIFM_IRQ_FIFOMASK(socket_change_set) in tifm_7xx1_switch_media()
[all …]
Darm-charlcd.c82 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_interrupt()
98 writel(0x00, lcd->virtbase + CHAR_MASK); in charlcd_wait_complete_irq()
132 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_char()
150 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_char()
166 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_bf()
168 writel(0x01, lcd->virtbase + CHAR_MASK); in charlcd_4bit_read_bf()
190 writel(cmdhi, lcd->virtbase + CHAR_COM); in charlcd_4bit_command()
192 writel(cmdlo, lcd->virtbase + CHAR_COM); in charlcd_4bit_command()
201 writel(chhi, lcd->virtbase + CHAR_DAT); in charlcd_4bit_char()
203 writel(chlo, lcd->virtbase + CHAR_DAT); in charlcd_4bit_char()
[all …]
/linux-4.1.27/drivers/usb/phy/
Dphy-tegra-usb.c215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); in set_pts()
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
242 writel(val, base + TEGRA_USB_PORTSC1); in set_phcd()
280 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
305 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
335 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
341 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
357 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
363 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
[all …]
/linux-4.1.27/drivers/rtc/
Drtc-stmp3xxx.c95 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); in stmp3xxx_wdt_set_timeout()
96 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, in stmp3xxx_wdt_set_timeout()
98 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, in stmp3xxx_wdt_set_timeout()
101 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, in stmp3xxx_wdt_set_timeout()
103 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, in stmp3xxx_wdt_set_timeout()
170 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS); in stmp3xxx_rtc_set_mmss()
181 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ, in stmp3xxx_rtc_interrupt()
195 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | in stmp3xxx_alarm_irq_enable()
198 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, in stmp3xxx_alarm_irq_enable()
201 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | in stmp3xxx_alarm_irq_enable()
[all …]
Drtc-sun6i.c128 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_alarmirq()
149 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, in sun6i_rtc_setaie()
153 writel(alrm_val, chip->base + SUN6I_ALRM_EN); in sun6i_rtc_setaie()
154 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); in sun6i_rtc_setaie()
155 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); in sun6i_rtc_setaie()
237 writel(0, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_setalarm()
240 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_setalarm()
301 writel(time, chip->base + SUN6I_RTC_HMS); in sun6i_rtc_settime()
315 writel(date, chip->base + SUN6I_RTC_YMD); in sun6i_rtc_settime()
382 writel(0, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_probe()
[all …]
Drtc-coh901331.c59 writel(1, rtap->virtbase + COH901331_IRQ_EVENT); in coh901331_interrupt()
67 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_interrupt()
96 writel(secs, rtap->virtbase + COH901331_SET_TIME); in coh901331_set_mmss()
122 writel(time, rtap->virtbase + COH901331_ALARM); in coh901331_set_alarm()
123 writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_set_alarm()
135 writel(1, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_alarm_irq_enable()
137 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_alarm_irq_enable()
228 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_suspend()
244 writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_resume()
258 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_shutdown()
Drtc-sunxi.c168 writel(val, chip->base + SUNXI_ALRM_IRQ_STA); in sunxi_rtc_alarmirq()
190 writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, in sunxi_rtc_setaie()
194 writel(alrm_val, chip->base + SUNXI_ALRM_EN); in sunxi_rtc_setaie()
195 writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setaie()
308 writel(0, chip->base + SUNXI_ALRM_DHMS); in sunxi_rtc_setalarm()
315 writel(alrm, chip->base + SUNXI_ALRM_DHMS); in sunxi_rtc_setalarm()
317 writel(0, chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setalarm()
318 writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setalarm()
378 writel(0, chip->base + SUNXI_RTC_HMS); in sunxi_rtc_settime()
379 writel(0, chip->base + SUNXI_RTC_YMD); in sunxi_rtc_settime()
[all …]
Drtc-pl031.c101 writel(RTC_BIT_AI, ldata->base + RTC_ICR); in pl031_alarm_irq_enable()
106 writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC); in pl031_alarm_irq_enable()
108 writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC); in pl031_alarm_irq_enable()
188 writel(bcd_year, ldata->base + RTC_YLR); in pl031_stv2_set_time()
189 writel(time, ldata->base + RTC_LR); in pl031_stv2_set_time()
222 writel(bcd_year, ldata->base + RTC_YMR); in pl031_stv2_set_alarm()
223 writel(time, ldata->base + RTC_MR); in pl031_stv2_set_alarm()
240 writel(RTC_BIT_AI, ldata->base + RTC_ICR); in pl031_interrupt()
268 writel(time, ldata->base + RTC_LR); in pl031_set_time()
296 writel(time, ldata->base + RTC_MR); in pl031_set_alarm()
[all …]
Drtc-puv3.c41 writel(readl(RTC_RTSR) | RTC_RTSR_AL, RTC_RTSR); in puv3_rtc_alarmirq()
50 writel(readl(RTC_RTSR) | RTC_RTSR_HZ, RTC_RTSR); in puv3_rtc_tickirq()
67 writel(tmp, RTC_RTSR); in puv3_rtc_setaie()
82 writel(tmp, RTC_RTSR); in puv3_rtc_setpie()
109 writel(rtc_count, RTC_RCNR); in puv3_rtc_settime()
141 writel(rtcalarm_count, RTC_RTAR); in puv3_rtc_setalarm()
213 writel(readl(RTC_RTSR) & ~RTC_RTSR_HZE, RTC_RTSR); in puv3_rtc_enable()
218 writel(readl(RTC_RTSR) | RTC_RTSR_HZE, RTC_RTSR); in puv3_rtc_enable()
319 writel(ticnt_save, RTC_RTAR); in puv3_rtc_resume()
/linux-4.1.27/drivers/mmc/host/
Dtifm_sd.c150 writel(val, sock->addr + SOCK_MMCSD_DATA); in tifm_sd_write_fifo()
162 writel(val, sock->addr + SOCK_MMCSD_DATA); in tifm_sd_write_fifo()
185 writel(host->bounce_buf_data[0], in tifm_sd_transfer_data()
319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS); in tifm_sd_set_dma_data()
321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN, in tifm_sd_set_dma_data()
324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN, in tifm_sd_set_dma_data()
386 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH); in tifm_sd_exec()
387 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW); in tifm_sd_exec()
388 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND); in tifm_sd_exec()
433 writel(TIFM_MMCSD_EOFB in tifm_sd_check_status()
[all …]
Ddavinci_mmc.c262 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); in davinci_fifo_data_trans()
361 writel(0x1FFF, host->base + DAVINCI_MMCTOR); in mmc_davinci_start_command()
384 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); in mmc_davinci_start_command()
385 writel(cmd_reg, host->base + DAVINCI_MMCCMD); in mmc_davinci_start_command()
399 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_start_command()
566 writel(0, host->base + DAVINCI_MMCBLEN); in mmc_davinci_prepare_data()
567 writel(0, host->base + DAVINCI_MMCNBLK); in mmc_davinci_prepare_data()
582 writel(timeout, host->base + DAVINCI_MMCTOD); in mmc_davinci_prepare_data()
583 writel(data->blocks, host->base + DAVINCI_MMCNBLK); in mmc_davinci_prepare_data()
584 writel(data->blksz, host->base + DAVINCI_MMCBLEN); in mmc_davinci_prepare_data()
[all …]
Dmoxart-mmc.c192 writel(*status & mask, host->base + REG_CLEAR); in moxart_wait_for_status()
209 writel(RSP_TIMEOUT | RSP_CRC_OK | in moxart_send_command()
211 writel(cmd->arg, host->base + REG_ARGUMENT); in moxart_send_command()
225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); in moxart_send_command()
390 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); in moxart_prepare_data()
391 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); in moxart_prepare_data()
392 writel(host->rate, host->base + REG_DATA_TIMER); in moxart_prepare_data()
393 writel(host->data_len, host->base + REG_DATA_LENGTH); in moxart_prepare_data()
394 writel(datactrl, host->base + REG_DATA_CONTROL); in moxart_prepare_data()
421 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); in moxart_request()
[all …]
Dvia-sdmmc.c430 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); in via_restore_sdcreg()
431 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); in via_restore_sdcreg()
432 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE); in via_restore_sdcreg()
433 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN); in via_restore_sdcreg()
434 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT); in via_restore_sdcreg()
435 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); in via_restore_sdcreg()
436 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS); in via_restore_sdcreg()
437 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); in via_restore_sdcreg()
438 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); in via_restore_sdcreg()
439 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); in via_restore_sdcreg()
[all …]
/linux-4.1.27/arch/arm/mach-orion5x/
Dtsx09-common.c36 writel(0x83, UART1_REG(LCR)); in qnap_tsx09_power_off()
37 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
38 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in qnap_tsx09_power_off()
39 writel(0x03, UART1_REG(LCR)); in qnap_tsx09_power_off()
40 writel(0x00, UART1_REG(IER)); in qnap_tsx09_power_off()
41 writel(0x00, UART1_REG(FCR)); in qnap_tsx09_power_off()
42 writel(0x00, UART1_REG(MCR)); in qnap_tsx09_power_off()
45 writel('A', UART1_REG(TX)); in qnap_tsx09_power_off()
Dterastation_pro2-setup.c195 writel(buf[i++], UART1_REG(TX)); in tsp2_miconwrite()
279 writel(0x83, UART1_REG(LCR)); in tsp2_power_off()
280 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off()
281 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in tsp2_power_off()
282 writel(0x1b, UART1_REG(LCR)); in tsp2_power_off()
283 writel(0x00, UART1_REG(IER)); in tsp2_power_off()
284 writel(0x07, UART1_REG(FCR)); in tsp2_power_off()
285 writel(0x00, UART1_REG(MCR)); in tsp2_power_off()
Dkurobox_pro-setup.c216 writel(buf[i++], UART1_REG(TX)); in kurobox_pro_miconwrite()
300 writel(0x83, UART1_REG(LCR)); in kurobox_pro_power_off()
301 writel(divisor & 0xff, UART1_REG(DLL)); in kurobox_pro_power_off()
302 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in kurobox_pro_power_off()
303 writel(0x1b, UART1_REG(LCR)); in kurobox_pro_power_off()
304 writel(0x00, UART1_REG(IER)); in kurobox_pro_power_off()
305 writel(0x07, UART1_REG(FCR)); in kurobox_pro_power_off()
306 writel(0x00, UART1_REG(MCR)); in kurobox_pro_power_off()
/linux-4.1.27/drivers/net/ethernet/allwinner/
Dsun4i-emac.c98 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
111 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
192 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
194 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
268 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, in emac_setup()
274 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | in emac_setup()
283 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_setup()
286 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); in emac_setup()
289 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, in emac_setup()
293 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, in emac_setup()
[all …]
/linux-4.1.27/drivers/scsi/isci/
Dhost.c202 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); in sci_controller_isr()
212 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); in sci_controller_isr()
213 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_isr()
251 writel(0xff, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr()
252 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr()
569 writel(ihost->completion_queue_get, in sci_controller_process_completions()
592 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status); in sci_controller_error_handler()
605 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_handler()
614 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); in isci_intx_isr()
707 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_enable_interrupts()
[all …]
Dphy.c101 writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX, in sci_phy_transport_layer_initialization()
110 writel(tl_control, &iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization()
138 writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) | in sci_phy_link_layer_initialization()
146 writel(0xFEDCBA98, &llr->sas_device_name_high); in sci_phy_link_layer_initialization()
147 writel(phy_idx, &llr->sas_device_name_low); in sci_phy_link_layer_initialization()
150 writel(phy_oem->sas_address.high, &llr->source_sas_address_high); in sci_phy_link_layer_initialization()
151 writel(phy_oem->sas_address.low, &llr->source_sas_address_low); in sci_phy_link_layer_initialization()
154 writel(0, &llr->identify_frame_phy_id); in sci_phy_link_layer_initialization()
155 writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id); in sci_phy_link_layer_initialization()
162 writel(phy_configuration, &llr->phy_configuration); in sci_phy_link_layer_initialization()
[all …]
/linux-4.1.27/arch/arm/mach-s3c64xx/
Dsetup-usb-phy.c29 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init()
52 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
55 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init()
59 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, in s3c_usb_otgphy_init()
62 writel(0, S3C_RSTCON); in s3c_usb_otgphy_init()
69 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit()
72 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
/linux-4.1.27/drivers/net/ethernet/
Dkorina.c144 writel(0, &ch->dmandptr); in korina_start_dma()
145 writel(dma_addr, &ch->dmadptr); in korina_start_dma()
152 writel(0x10, &ch->dmac); in korina_abort_dma()
157 writel(0, &ch->dmas); in korina_abort_dma()
160 writel(0, &ch->dmadptr); in korina_abort_dma()
161 writel(0, &ch->dmandptr); in korina_abort_dma()
166 writel(dma_addr, &ch->dmandptr); in korina_chain_dma()
244 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), in korina_send_packet()
260 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), in korina_send_packet()
299 writel(0, &lp->eth_regs->miimcfg); in mdio_read()
[all …]
/linux-4.1.27/arch/arm/common/
Dtimer-sp.c96 writel(0, base + TIMER_CTRL); in __sp804_clocksource_and_sched_clock_init()
97 writel(0xffffffff, base + TIMER_LOAD); in __sp804_clocksource_and_sched_clock_init()
98 writel(0xffffffff, base + TIMER_VALUE); in __sp804_clocksource_and_sched_clock_init()
99 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, in __sp804_clocksource_and_sched_clock_init()
123 writel(1, clkevt_base + TIMER_INTCLR); in sp804_timer_interrupt()
135 writel(ctrl, clkevt_base + TIMER_CTRL); in sp804_set_mode()
139 writel(clkevt_reload, clkevt_base + TIMER_LOAD); in sp804_set_mode()
154 writel(ctrl, clkevt_base + TIMER_CTRL); in sp804_set_mode()
162 writel(next, clkevt_base + TIMER_LOAD); in sp804_set_next_event()
163 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); in sp804_set_next_event()
[all …]
/linux-4.1.27/drivers/tty/serial/
Dxilinx_uartps.c210 writel(CDNS_UART_IXR_FRAMING, in cdns_uart_isr()
276 writel(CDNS_UART_IXR_TXEMPTY, in cdns_uart_isr()
288 writel(port->state->xmit.buf[ in cdns_uart_isr()
308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); in cdns_uart_isr()
403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET); in cdns_uart_set_baud_rate()
404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); in cdns_uart_set_baud_rate()
405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); in cdns_uart_set_baud_rate()
454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb()
481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb()
492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); in cdns_uart_clk_notifier_cb()
[all …]
Dlpc32xx_hs.c136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
271 writel(LPC32XX_HSU_FE_INT, in __serial_lpc32xx_rx()
294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx()
306 writel((u32) xmit->buf[xmit->tail], in __serial_lpc32xx_tx()
321 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); in __serial_lpc32xx_tx()
338 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt()
345 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt()
349 writel(LPC32XX_HSU_RX_OE_INT, in serial_lpc32xx_interrupt()
362 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt()
403 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); in serial_lpc32xx_stop_tx()
[all …]
Dnetx-serial.c122 writel(val & ~CR_TIE, port->membase + UART_CR); in netx_stop_tx()
129 writel(val & ~CR_RIE, port->membase + UART_CR); in netx_stop_rx()
136 writel(val | CR_MSIE, port->membase + UART_CR); in netx_enable_ms()
144 writel(port->x_char, port->membase + UART_DR); in netx_transmit_buffer()
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); in netx_transmit_buffer()
172 writel( in netx_start_tx()
209 writel(0, port->membase + UART_SR); in netx_rxint()
264 writel(0, port->membase + UART_IIR); in netx_int()
289 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR); in netx_set_mctrl()
303 writel(line_cr, port->membase + UART_LINE_CR); in netx_break_ctl()
[all …]
Dimx.c302 writel(ucr->ucr1, port->membase + UCR1); in imx_port_ucrs_restore()
303 writel(ucr->ucr2, port->membase + UCR2); in imx_port_ucrs_restore()
304 writel(ucr->ucr3, port->membase + UCR3); in imx_port_ucrs_restore()
369 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); in imx_stop_tx()
379 writel(temp, port->membase + UCR2); in imx_stop_tx()
383 writel(temp, port->membase + UCR4); in imx_stop_tx()
405 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); in imx_stop_rx()
409 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); in imx_stop_rx()
430 writel(sport->port.x_char, sport->port.membase + URTX0); in imx_transmit_buffer()
450 writel(temp, sport->port.membase + UCR1); in imx_transmit_buffer()
[all …]
Dmxs-auart.c300 writel(s->port.x_char, in mxs_auart_tx_chars()
307 writel(xmit->buf[xmit->tail], in mxs_auart_tx_chars()
317 writel(AUART_INTR_TXIEN, in mxs_auart_tx_chars()
320 writel(AUART_INTR_TXIEN, in mxs_auart_tx_chars()
369 writel(stat, s->port.membase + AUART_STAT); in mxs_auart_rx_char()
383 writel(stat, s->port.membase + AUART_STAT); in mxs_auart_rx_chars()
429 writel(ctrl, u->membase + AUART_CTRL2); in mxs_auart_set_mctrl()
544 writel(stat, s->port.membase + AUART_STAT); in dma_rx_callback()
607 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, in mxs_auart_dma_exit()
760 writel(ctrl, u->membase + AUART_LINECTRL); in mxs_auart_settermios()
[all …]
/linux-4.1.27/sound/soc/kirkwood/
Dkirkwood-i2s.c68 writel(value, priv->io+KIRKWOOD_I2S_PLAYCTL); in kirkwood_i2s_set_fmt()
73 writel(value, priv->io+KIRKWOOD_I2S_RECCTL); in kirkwood_i2s_set_fmt()
95 writel(value, io + KIRKWOOD_DCO_CTL); in kirkwood_set_dco()
127 writel(clks_ctrl, priv->io + KIRKWOOD_CLOCKS_CTRL); in kirkwood_set_rate()
220 writel(i2s_value, priv->io+i2s_reg); in kirkwood_i2s_hw_params()
272 writel(value, priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger()
278 writel(value, priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_play_trigger()
282 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger()
289 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger()
293 writel(value, priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_play_trigger()
[all …]
Dkirkwood-dma.c57 writel(cause, priv->io + KIRKWOOD_ERR_CAUSE); in kirkwood_dma_irq()
69 writel(status, priv->io + KIRKWOOD_INT_CAUSE); in kirkwood_dma_irq()
88 writel(0, base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win)); in kirkwood_dma_conf_mbus_windows()
89 writel(0, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); in kirkwood_dma_conf_mbus_windows()
95 writel(cs->base & 0xffff0000, in kirkwood_dma_conf_mbus_windows()
97 writel(((cs->size - 1) & 0xffff0000) | in kirkwood_dma_conf_mbus_windows()
145 writel((unsigned int)-1, priv->io + KIRKWOOD_ERR_MASK); in kirkwood_dma_open()
176 writel(0, priv->io + KIRKWOOD_ERR_MASK); in kirkwood_dma_close()
212 writel(count, priv->io + KIRKWOOD_PLAY_BYTE_INT_COUNT); in kirkwood_dma_prepare()
213 writel(runtime->dma_addr, priv->io + KIRKWOOD_PLAY_BUF_ADDR); in kirkwood_dma_prepare()
[all …]
/linux-4.1.27/drivers/virtio/
Dvirtio_mmio.c120 writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features()
124 writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features()
144 writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features()
145 writel((u32)(vdev->features >> 32), in vm_finalize_features()
148 writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features()
149 writel((u32)vdev->features, in vm_finalize_features()
227 writel(le32_to_cpu(l), base + offset); in vm_set()
231 writel(le32_to_cpu(l), base + offset); in vm_set()
233 writel(le32_to_cpu(l), base + offset + sizeof l); in vm_set()
264 writel(status, vm_dev->base + VIRTIO_MMIO_STATUS); in vm_set_status()
[all …]
/linux-4.1.27/drivers/memstick/host/
Dtifm_ms.c142 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data()
144 writel(host->io_word, sock->addr + SOCK_MS_DATA); in tifm_ms_write_data()
157 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data()
238 writel(TIFM_MS_SYS_FDIR in tifm_ms_transfer_data()
241 writel(host->io_word, sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data()
243 writel(TIFM_MS_SYS_FDIR in tifm_ms_transfer_data()
246 writel(0, sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data()
279 writel(TIFM_FIFO_INT_SETALL, in tifm_ms_issue_cmd()
281 writel(TIFM_FIFO_ENABLE, in tifm_ms_issue_cmd()
294 writel(ilog2(data_len) - 2, in tifm_ms_issue_cmd()
[all …]
Djmb38x_ms.c237 writel(host->io_word[0], host->addr + DATA); in jmb38x_ms_write_data()
357 writel(host->io_word[0], host->addr + TPC_P0); in jmb38x_ms_transfer_data()
358 writel(host->io_word[1], host->addr + TPC_P1); in jmb38x_ms_transfer_data()
360 writel(host->io_word[0], host->addr + DATA); in jmb38x_ms_transfer_data()
430 writel(sg_dma_address(&host->req->sg), in jmb38x_ms_issue_cmd()
432 writel(((1 << 16) & BLOCK_COUNT_MASK) in jmb38x_ms_issue_cmd()
435 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); in jmb38x_ms_issue_cmd()
437 writel(((1 << 16) & BLOCK_COUNT_MASK) in jmb38x_ms_issue_cmd()
445 writel(t_val, host->addr + INT_STATUS_ENABLE); in jmb38x_ms_issue_cmd()
446 writel(t_val, host->addr + INT_SIGNAL_ENABLE); in jmb38x_ms_issue_cmd()
[all …]
/linux-4.1.27/arch/arm/mach-sunxi/
Dplatsmp.c83 writel(virt_to_phys(secondary_startup), in sun6i_smp_boot_secondary()
87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
95 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
99 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); in sun6i_smp_boot_secondary()
104 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
108 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
112 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
/linux-4.1.27/arch/arm/mach-mvebu/
Dpm.c54 writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); in mvebu_pm_powerdown()
61 writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); in mvebu_pm_powerdown()
125 writel(BOOT_MAGIC_WORD, store_addr++); in mvebu_pm_store_bootinfo()
126 writel(resume_pc, store_addr++); in mvebu_pm_store_bootinfo()
134 writel(MBUS_WINDOW_12_CTRL, store_addr++); in mvebu_pm_store_bootinfo()
135 writel(0x0, store_addr++); in mvebu_pm_store_bootinfo()
141 writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++); in mvebu_pm_store_bootinfo()
142 writel(mvebu_internal_reg_base(), store_addr++); in mvebu_pm_store_bootinfo()
151 writel(BOOT_MAGIC_LIST_END, store_addr); in mvebu_pm_store_bootinfo()
Dpmsu.c116 writel(virt_to_phys(boot_addr), pmsu_mp_base + in mvebu_pmsu_set_cpu_boot_addr()
218 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle()
248 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
257 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
263 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); in mvebu_v7_pmsu_idle_prepare()
352 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
360 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_exit()
439 writel(reg, mpsoc_base + MPCORE_RESET_CTL); in armada_38x_cpuidle_init()
447 writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY); in armada_38x_cpuidle_init()
528 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); in mvebu_pmsu_dfs_request_local()
[all …]
/linux-4.1.27/drivers/net/ethernet/moxa/
Dmoxart_ether.c36 writel(value, priv->base + reg); in moxart_emac_write()
88 writel(SW_RST, priv->base + REG_MAC_CTRL); in moxart_mac_reset()
92 writel(0, priv->base + REG_INTERRUPT_MASK); in moxart_mac_reset()
101 writel(0x00001010, priv->base + REG_INT_TIMER_CTRL); in moxart_mac_enable()
102 writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL); in moxart_mac_enable()
103 writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL); in moxart_mac_enable()
106 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); in moxart_mac_enable()
109 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); in moxart_mac_enable()
124 writel(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1); in moxart_mac_setup_desc_ring()
132 writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); in moxart_mac_setup_desc_ring()
[all …]
/linux-4.1.27/drivers/usb/dwc2/
Dcore_intr.c87 writel(hprt0, hsotg->regs + HPRT0); in dwc2_handle_usb_port_intr()
91 writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); in dwc2_handle_usb_port_intr()
105 writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); in dwc2_handle_mode_mismatch_intr()
157 writel(gotgctl, hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
173 writel(gotgctl, hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
205 writel(gintmsk, hsotg->regs + GINTMSK); in dwc2_handle_otg_intr()
221 writel(gotgctl, hsotg->regs + GOTGCTL); in dwc2_handle_otg_intr()
249 writel(gintmsk, hsotg->regs + GINTMSK); in dwc2_handle_otg_intr()
264 writel(gotgint, hsotg->regs + GOTGINT); in dwc2_handle_otg_intr()
283 writel(gintmsk, hsotg->regs + GINTMSK); in dwc2_handle_conn_id_status_change_intr()
[all …]
Dcore.c70 writel(0xffffffff, hsotg->regs + GOTGINT); in dwc2_enable_common_interrupts()
73 writel(0xffffffff, hsotg->regs + GINTSTS); in dwc2_enable_common_interrupts()
84 writel(intmsk, hsotg->regs + GINTMSK); in dwc2_enable_common_interrupts()
110 writel(hcfg, hsotg->regs + HCFG); in dwc2_init_fs_ls_pclk_sel()
140 writel(greset, hsotg->regs + GRSTCTL); in dwc2_core_reset()
156 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
161 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
166 writel(gusbcfg, hsotg->regs + GUSBCFG); in dwc2_core_reset()
191 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
216 writel(usbcfg, hsotg->regs + GUSBCFG); in dwc2_fs_phy_init()
[all …]
/linux-4.1.27/drivers/power/reset/
Dqnap-poweroff.c65 writel(0x83, UART1_REG(LCR)); in qnap_power_off()
66 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off()
67 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in qnap_power_off()
68 writel(0x03, UART1_REG(LCR)); in qnap_power_off()
69 writel(0x00, UART1_REG(IER)); in qnap_power_off()
70 writel(0x00, UART1_REG(FCR)); in qnap_power_off()
71 writel(0x00, UART1_REG(MCR)); in qnap_power_off()
74 writel(cfg->cmd, UART1_REG(TX)); in qnap_power_off()
/linux-4.1.27/drivers/net/ethernet/amd/
Damd8111e.c123 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | in amd8111e_read_phy()
152 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | in amd8111e_write_phy()
392 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()
393 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, in amd8111e_set_coalesce()
406 writel(VAL0|STINTEN,mmio+INTEN0); in amd8111e_set_coalesce()
407 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, in amd8111e_set_coalesce()
412 writel(0,mmio+STVAL); in amd8111e_set_coalesce()
413 writel(STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()
414 writel(0, mmio +DLY_INT_B); in amd8111e_set_coalesce()
415 writel(0, mmio+DLY_INT_A); in amd8111e_set_coalesce()
[all …]
/linux-4.1.27/drivers/staging/comedi/drivers/
Drtd520.c485 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list()
486 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
488 writel(rtd_convert_chan_gain(dev, list[ii], ii), in rtd_load_channelgain_list()
492 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
493 writel(rtd_convert_chan_gain(dev, list[0], 0), in rtd_load_channelgain_list()
507 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
510 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth()
527 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
560 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd_ai_rinsn()
566 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd_ai_rinsn()
[all …]
Dgsc_hpdi.c231 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG); in gsc_hpdi_interrupt()
257 writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG); in gsc_hpdi_interrupt()
294 writel(0, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cancel()
295 writel(0, dev->mmio + INTERRUPT_CONTROL_REG); in gsc_hpdi_cancel()
314 writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cmd()
326 writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG); in gsc_hpdi_cmd()
327 writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG); in gsc_hpdi_cmd()
328 writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG); in gsc_hpdi_cmd()
333 writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG); in gsc_hpdi_cmd()
347 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG); in gsc_hpdi_cmd()
[all …]
Ds626.c113 writel(val, dev->mmio + reg); in s626_mc_enable()
119 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
185 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_read()
200 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_write()
201 writel(wdata, dev->mmio + S626_P_DEBIAD); in s626_debi_write()
218 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
221 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
225 writel(val & 0xffff, dev->mmio + S626_P_DEBIAD); in s626_debi_replace()
250 writel(val, dev->mmio + S626_P_I2CCTRL); in s626_i2c_handshake()
400 writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR); in s626_send_dac()
[all …]
Dmite.c123 writel(0, mite->mite_io_addr + MITE_IODWBSR); in mite_setup2()
126 writel(mite->daq_phys_addr | WENAB | in mite_setup2()
129 writel(0, mite->mite_io_addr + MITE_IODWCR_1); in mite_setup2()
131 writel(mite->daq_phys_addr | WENAB, in mite_setup2()
144 writel(unknown_dma_burst_bits, in mite_setup2()
157 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); in mite_setup2()
159 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | in mite_setup2()
258 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | in mite_release_channel()
286 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); in mite_dma_arm()
357 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); in mite_prep_dma()
[all …]
/linux-4.1.27/drivers/net/ethernet/alteon/
Dacenic.c614 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); in acenic_remove_one()
616 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl); in acenic_remove_one()
621 writel(1, &regs->Mb0Lo); in acenic_remove_one()
853 writel(*(u32 *)(cmd), &regs->CmdRng[idx]); in ace_issue_cmd()
856 writel(idx, &regs->CmdPrd); in ace_issue_cmd()
883 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl); in ace_init()
895 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), in ace_init()
898 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), in ace_init()
906 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); in ace_init()
908 writel(0, &regs->Mb0Lo); in ace_init()
[all …]
/linux-4.1.27/drivers/phy/
Dphy-exynos5250-usb2.c233 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on()
239 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on()
262 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
266 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on()
285 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on()
295 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); in exynos5250_power_on()
296 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); in exynos5250_power_on()
299 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); in exynos5250_power_on()
300 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); in exynos5250_power_on()
311 writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL); in exynos5250_power_on()
[all …]
Dphy-berlin-usb.c125 writel(priv->pll_divider, in phy_berlin_usb_power_on()
127 writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL | in phy_berlin_usb_power_on()
129 writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5), in phy_berlin_usb_power_on()
131 writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 | in phy_berlin_usb_power_on()
135 writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1); in phy_berlin_usb_power_on()
136 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), in phy_berlin_usb_power_on()
139 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) | in phy_berlin_usb_power_on()
142 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), in phy_berlin_usb_power_on()
144 writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 | in phy_berlin_usb_power_on()
Dphy-exynos5250-sata.c102 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
108 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
112 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
116 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
120 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); in exynos_sata_phy_init()
125 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); in exynos_sata_phy_init()
129 writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0); in exynos_sata_phy_init()
133 writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0); in exynos_sata_phy_init()
142 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
146 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
Dphy-berlin-sata.c74 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
80 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
96 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_on()
99 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
102 writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_on()
105 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
127 writel(regval, ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
147 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); in phy_berlin_sata_power_off()
150 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_off()
/linux-4.1.27/drivers/net/ethernet/nxp/
Dlpc_eth.c454 writel(tmp, LPC_ENET_SA2(pldat->net_base)); in __lpc_set_mac()
456 writel(tmp, LPC_ENET_SA1(pldat->net_base)); in __lpc_set_mac()
458 writel(tmp, LPC_ENET_SA0(pldat->net_base)); in __lpc_set_mac()
495 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); in __lpc_params_setup()
498 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); in __lpc_params_setup()
499 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base)); in __lpc_params_setup()
503 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); in __lpc_params_setup()
506 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); in __lpc_params_setup()
507 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base)); in __lpc_params_setup()
511 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base)); in __lpc_params_setup()
[all …]
/linux-4.1.27/drivers/usb/gadget/udc/
Dnet2280.h30 writel(index, &regs->idxaddr); in get_idx_reg()
38 writel(index, &regs->idxaddr); in set_idx_reg()
39 writel(value, &regs->idxdata); in set_idx_reg()
120 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | in allow_status()
134 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp); in allow_status_338x()
196 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | in set_halt()
206 writel(BIT(CLEAR_ENDPOINT_HALT) | in clear_halt()
258 writel(BIT(GPIO3_LED_SELECT) | in net2280_led_init()
287 writel(val, &dev->regs->gpioctl); in net2280_led_speed()
300 writel(val, &dev->regs->gpioctl); in net2280_led_active()
[all …]
Dnet2280.c135 writel(tmp, &ep->dev->regs->pciirqenb0); in enable_pciirqenb()
200 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_enable()
207 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE), in net2280_enable()
250 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in net2280_enable()
255 writel(BIT(CLEAR_NAK_OUT_PACKETS) | in net2280_enable()
259 writel(tmp, &ep->cfg->ep_cfg); in net2280_enable()
269 writel(tmp, &ep->regs->ep_irqenb); in net2280_enable()
273 writel(tmp, &dev->regs->pciirqenb1); in net2280_enable()
281 writel(tmp, &ep->regs->ep_irqenb); in net2280_enable()
334 writel(0, &ep->dma->dmactl); in ep_reset_228x()
[all …]
Damd5536udc.c224 writel(tmp, &dev->regs->irqmsk); in udc_mask_unused_interrupts()
227 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk); in udc_mask_unused_interrupts()
244 writel(tmp, &dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
265 writel(tmp, &dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
342 writel(tmp, &dev->ep[ep->num].regs->ctl); in udc_ep_enable()
349 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
365 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
373 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
384 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
413 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
[all …]
Ds3c-hsudc.c184 writel(ep_addr, hsudc->regs + S3C_IR); in set_index()
189 writel(readl(ptr) | val, ptr); in __orr32()
197 writel(cfg, S3C2443_PWRCFG); in s3c_hsudc_init_phy()
201 writel(cfg, S3C2443_URSTCON); in s3c_hsudc_init_phy()
206 writel(cfg, S3C2443_URSTCON); in s3c_hsudc_init_phy()
211 writel(cfg, S3C2443_PHYCTRL); in s3c_hsudc_init_phy()
218 writel(cfg, S3C2443_PHYPWR); in s3c_hsudc_init_phy()
223 writel(cfg, S3C2443_UCLKCON); in s3c_hsudc_init_phy()
231 writel(cfg, S3C2443_PWRCFG); in s3c_hsudc_uninit_phy()
233 writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR); in s3c_hsudc_uninit_phy()
[all …]
/linux-4.1.27/drivers/vlynq/
Dvlynq.c124 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, in vlynq_reset()
131 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, in vlynq_reset()
148 writel(val, &dev->remote->int_device[virq >> 2]); in vlynq_irq_unmask()
161 writel(val, &dev->remote->int_device[virq >> 2]); in vlynq_irq_mask()
191 writel(val, &dev->remote->int_device[virq >> 2]); in vlynq_irq_type()
202 writel(status, &dev->local->status); in vlynq_local_ack()
212 writel(status, &dev->remote->status); in vlynq_remote_ack()
222 writel(status, &dev->local->int_status); in vlynq_irq()
271 writel(readl(&dev->local->status), &dev->local->status); in vlynq_setup_irq()
272 writel(readl(&dev->remote->status), &dev->remote->status); in vlynq_setup_irq()
[all …]
/linux-4.1.27/drivers/net/ethernet/agere/
Det131x.c755 writel(csr, &adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
773 writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE, in et131x_rx_dma_disable()
791 writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT), in et131x_tx_dma_enable()
815 writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | in et1310_config_mac_regs1()
823 writel(ipg, &macregs->ipg); in et1310_config_mac_regs1()
827 writel(0x00A1F037, &macregs->hfdp); in et1310_config_mac_regs1()
830 writel(0, &macregs->if_ctrl); in et1310_config_mac_regs1()
832 writel(ET_MAC_MIIMGMT_CLK_RST, &macregs->mii_mgmt_cfg); in et1310_config_mac_regs1()
847 writel(station1, &macregs->station_addr_1); in et1310_config_mac_regs1()
848 writel(station2, &macregs->station_addr_2); in et1310_config_mac_regs1()
[all …]
/linux-4.1.27/drivers/watchdog/
Dqcom-wdt.c45 writel(0, wdt->base + WDT_EN); in qcom_wdt_start()
46 writel(1, wdt->base + WDT_RST); in qcom_wdt_start()
47 writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME); in qcom_wdt_start()
48 writel(1, wdt->base + WDT_EN); in qcom_wdt_start()
56 writel(0, wdt->base + WDT_EN); in qcom_wdt_stop()
64 writel(1, wdt->base + WDT_RST); in qcom_wdt_ping()
102 writel(0, wdt->base + WDT_EN); in qcom_wdt_restart()
103 writel(1, wdt->base + WDT_RST); in qcom_wdt_restart()
104 writel(timeout, wdt->base + WDT_BITE_TIME); in qcom_wdt_restart()
105 writel(1, wdt->base + WDT_EN); in qcom_wdt_restart()
Dpnx4008_wdt.c90 writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); in pnx4008_wdt_start()
95 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); in pnx4008_wdt_start()
97 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); in pnx4008_wdt_start()
99 writel(MATCH_INT, WDTIM_INT(wdt_base)); in pnx4008_wdt_start()
101 writel(0xFFFF, WDTIM_PULSE(wdt_base)); in pnx4008_wdt_start()
102 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
104 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); in pnx4008_wdt_start()
114 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ in pnx4008_wdt_stop()
Dmoxart_wdt.c43 writel(1, moxart_wdt->base + REG_COUNT); in moxart_restart_handle()
44 writel(0x5ab9, moxart_wdt->base + REG_MODE); in moxart_restart_handle()
45 writel(0x03, moxart_wdt->base + REG_ENABLE); in moxart_restart_handle()
54 writel(0, moxart_wdt->base + REG_ENABLE); in moxart_wdt_stop()
63 writel(moxart_wdt->clock_frequency * wdt_dev->timeout, in moxart_wdt_start()
65 writel(0x5ab9, moxart_wdt->base + REG_MODE); in moxart_wdt_start()
66 writel(0x03, moxart_wdt->base + REG_ENABLE); in moxart_wdt_start()
/linux-4.1.27/drivers/net/ethernet/natsemi/
Dns83820.c469 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
477 writel(dev->rx_info.phy_descs + in kick_rx()
634 writel(readl(dev->base + TXCFG) in phy_intr()
637 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
640 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, in phy_intr()
651 writel((readl(dev->base + TXCFG) in phy_intr()
654 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, in phy_intr()
657 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, in phy_intr()
677 writel(readl(dev->base + TXCFG) in phy_intr()
680 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
[all …]
/linux-4.1.27/arch/arm/mach-highbank/
Dsysregs.h58 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_suspend()
64 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_shutdown()
70 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_soft_reset()
76 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_hard_reset()
82 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
/linux-4.1.27/drivers/input/keyboard/
Dbcm-keypad.c112 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys()
153 writel(kp->kpior, kp->base + KPIOR_OFFSET); in bcm_kp_start()
155 writel(kp->imr0_val, kp->base + KPIMR0_OFFSET); in bcm_kp_start()
156 writel(kp->imr1_val, kp->base + KPIMR1_OFFSET); in bcm_kp_start()
158 writel(kp->kpemr, kp->base + KPEMR0_OFFSET); in bcm_kp_start()
159 writel(kp->kpemr, kp->base + KPEMR1_OFFSET); in bcm_kp_start()
160 writel(kp->kpemr, kp->base + KPEMR2_OFFSET); in bcm_kp_start()
161 writel(kp->kpemr, kp->base + KPEMR3_OFFSET); in bcm_kp_start()
163 writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET); in bcm_kp_start()
164 writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET); in bcm_kp_start()
[all …]
Dlpc32xx-keys.c112 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); in lpc32xx_kscan_irq()
128 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); in lpc32xx_kscan_open()
137 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); in lpc32xx_kscan_close()
252 writel(kscandat->deb_clks, LPC32XX_KS_DEB(kscandat->kscan_base)); in lpc32xx_kscan_probe()
253 writel(kscandat->scan_delay, LPC32XX_KS_SCAN_CTL(kscandat->kscan_base)); in lpc32xx_kscan_probe()
254 writel(LPC32XX_KSCAN_FTST_USE32K_CLK, in lpc32xx_kscan_probe()
256 writel(kscandat->matrix_sz, in lpc32xx_kscan_probe()
258 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); in lpc32xx_kscan_probe()
290 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); in lpc32xx_kscan_suspend()
311 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); in lpc32xx_kscan_resume()
/linux-4.1.27/drivers/thermal/
Darmada_thermal.c80 writel(reg, priv->control); in armadaxp_init_sensor()
85 writel(reg, priv->control); in armadaxp_init_sensor()
89 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); in armadaxp_init_sensor()
91 writel(reg, priv->control); in armadaxp_init_sensor()
96 writel(reg, priv->sensor); in armadaxp_init_sensor()
106 writel(reg, priv->control); in armada370_init_sensor()
111 writel(reg, priv->control); in armada370_init_sensor()
114 writel(reg, priv->control); in armada370_init_sensor()
129 writel(reg, priv->control + 4); in armada375_init_sensor()
133 writel(reg, priv->control + 4); in armada375_init_sensor()
[all …]
/linux-4.1.27/drivers/media/rc/
Dst_rc.c115 writel(IRB_RX_OVERRUN_INT, in st_rc_rx_interrupt()
153 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); in st_rc_rx_interrupt()
174 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); in st_rc_hardware_init()
177 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); in st_rc_hardware_init()
187 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); in st_rc_hardware_init()
204 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); in st_rc_open()
205 writel(0x01, dev->rx_base + IRB_RX_EN); in st_rc_open()
215 writel(0x00, dev->rx_base + IRB_RX_EN); in st_rc_close()
216 writel(0x00, dev->rx_base + IRB_RX_INT_EN); in st_rc_close()
349 writel(0x00, rc_dev->rx_base + IRB_RX_EN); in st_rc_suspend()
[all …]
Dsunxi-cir.c113 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq()
261 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); in sunxi_ir_probe()
264 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE), in sunxi_ir_probe()
268 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); in sunxi_ir_probe()
271 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_probe()
277 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | in sunxi_ir_probe()
283 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); in sunxi_ir_probe()
313 writel(0, ir->base + SUNXI_IR_RXINT_REG); in sunxi_ir_remove()
315 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_remove()
317 writel(0, ir->base + SUNXI_IR_CTL_REG); in sunxi_ir_remove()
/linux-4.1.27/drivers/scsi/arcmsr/
Darcmsr_hba.c250 …writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);… in arcmsr_remap_pciregion()
346 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, in arcmsr_hbaA_wait_msgint_ready()
364 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, in arcmsr_hbaB_wait_msgint_ready()
366 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, in arcmsr_hbaB_wait_msgint_ready()
384 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, in arcmsr_hbaC_wait_msgint_ready()
402 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, in arcmsr_hbaD_wait_msgint_ready()
415 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0); in arcmsr_hbaA_flush_cache()
431 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); in arcmsr_hbaB_flush_cache()
447 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0); in arcmsr_hbaC_flush_cache()
448 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell); in arcmsr_hbaC_flush_cache()
[all …]
/linux-4.1.27/arch/mips/jz4740/
Dtimer.c28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_enable_watchdog()
34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_disable_watchdog()
46 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_init()
49 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_init()
/linux-4.1.27/arch/sparc/kernel/
Debus.c54 writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR); in __ebus_dma_reset()
77 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
117 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
137 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
143 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
165 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_unregister()
193 writel(len, p->regs + EBDMA_COUNT); in ebus_dma_request()
194 writel(bus_addr, p->regs + EBDMA_ADDR); in ebus_dma_request()
222 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_prepare()
253 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_enable()
/linux-4.1.27/drivers/net/ethernet/freescale/
Dfec_ptp.c137 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
146 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
161 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_enable_pps()
194 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); in fec_ptp_enable_pps()
202 writel(val, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_enable_pps()
210 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
215 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); in fec_ptp_enable_pps()
218 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
245 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
273 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); in fec_ptp_start_cyclecounter()
[all …]
/linux-4.1.27/sound/arm/
Daaci.c54 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec()
87 writel(val << 4, aaci->base + AACI_SL2TX); in aaci_ac97_write()
88 writel(reg << 12, aaci->base + AACI_SL1TX); in aaci_ac97_write()
126 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); in aaci_ac97_read()
203 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); in aaci_fifo_irq()
208 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); in aaci_fifo_irq()
218 writel(0, aacirun->base + AACI_IE); in aaci_fifo_irq()
268 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); in aaci_fifo_irq()
278 writel(0, aacirun->base + AACI_IE); in aaci_fifo_irq()
579 writel(ie, aacirun->base + AACI_IE); in aaci_pcm_playback_stop()
[all …]
/linux-4.1.27/drivers/net/ethernet/nvidia/
Dforcedeth.c1006 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings()
1008 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysA… in setup_hw_rings()
1011 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings()
1012 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); in setup_hw_rings()
1015 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPh… in setup_hw_rings()
1016 …writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingP… in setup_hw_rings()
1063 writel(powerstate, base + NvRegPowerState2); in nv_txrx_gate()
1104 writel(mask, base + NvRegIrqMask); in nv_enable_hw_interrupts()
1113 writel(mask, base + NvRegIrqMask); in nv_disable_hw_interrupts()
1116 writel(0, base + NvRegMSIIrqMask); in nv_disable_hw_interrupts()
[all …]
/linux-4.1.27/drivers/mfd/
Ddb8500-prcmu.c584 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); in db8500_prcmu_enable_dsipll()
586 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); in db8500_prcmu_enable_dsipll()
589 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); in db8500_prcmu_enable_dsipll()
590 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); in db8500_prcmu_enable_dsipll()
592 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); in db8500_prcmu_enable_dsipll()
595 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); in db8500_prcmu_enable_dsipll()
597 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); in db8500_prcmu_enable_dsipll()
605 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); in db8500_prcmu_enable_dsipll()
612 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); in db8500_prcmu_disable_dsipll()
614 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); in db8500_prcmu_disable_dsipll()
[all …]
/linux-4.1.27/arch/mips/include/asm/mach-jz4740/
Dtimer.h66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_stop()
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_start()
111 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); in jz4740_timer_ack_full()
116 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); in jz4740_timer_irq_full_enable()
117 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); in jz4740_timer_irq_full_enable()
122 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_irq_full_disable()
/linux-4.1.27/arch/arm/mach-dove/
Dmpp.c77 writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc()
114 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1()
115 writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1()
116 writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1()
117 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1()
143 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
/linux-4.1.27/drivers/clk/
Dclk-highbank.c62 writel(reg, hbclk->reg); in clk_pll_prepare()
79 writel(reg, hbclk->reg); in clk_pll_unprepare()
89 writel(reg, hbclk->reg); in clk_pll_enable()
101 writel(reg, hbclk->reg); in clk_pll_disable()
169 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); in clk_pll_set_rate()
171 writel(reg | HB_PLL_RESET, hbclk->reg); in clk_pll_set_rate()
174 writel(reg | HB_PLL_RESET, hbclk->reg); in clk_pll_set_rate()
175 writel(reg, hbclk->reg); in clk_pll_set_rate()
184 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); in clk_pll_set_rate()
187 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); in clk_pll_set_rate()
[all …]
/linux-4.1.27/drivers/mtd/nand/
Dsh_flctl.c86 writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl)); in empty_fifo()
87 writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); in empty_fifo()
211 writel(addr2, FLADR2(flctl)); in set_addr()
220 writel(addr, FLADR(flctl)); in set_addr()
299 writel(0, FL4ECCCR(flctl)); in wait_recfifo_ready()
325 writel(0, FL4ECCCR(flctl)); in wait_recfifo_ready()
375 writel(reg, FLINTDMACR(flctl)); in flctl_dma_fifo0_transfer()
403 writel(reg, FLINTDMACR(flctl)); in flctl_dma_fifo0_transfer()
473 writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl)); in write_fiforeg()
496 writel(buf[i], FLECFIFO(flctl)); in write_ec_fiforeg()
[all …]
/linux-4.1.27/drivers/net/phy/
Dmdio-sun4i.c46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read()
48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write()
75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
88 writel(value, data->membase + EMAC_MAC_MWTD_REG); in sun4i_mdio_write()
/linux-4.1.27/drivers/input/serio/
Dsun4i-ps2.c117 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
124 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
153 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
160 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
167 writel(rval, drvdata->reg_base + PS2_REG_CLKDR); in sun4i_ps2_open()
174 writel(rval, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_open()
187 writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_close()
199 writel(val, drvdata->reg_base + PS2_REG_DATA); in sun4i_ps2_write()
[all …]
/linux-4.1.27/arch/arm/mach-rockchip/
Drockchip.c48 writel(0, reg_base + 0x30); in rockchip_timer_init()
49 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init()
50 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init()
51 writel(1, reg_base + 0x30); in rockchip_timer_init()
/linux-4.1.27/drivers/net/ethernet/calxeda/
Dxgmac.c519 writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR); in xgmac_dma_flush_tx_fifo()
602 writel(value, ioaddr + XGMAC_CONTROL); in xgmac_mac_enable()
606 writel(value, ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_enable()
613 writel(value, ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_disable()
617 writel(value, ioaddr + XGMAC_CONTROL); in xgmac_mac_disable()
627 writel(data, ioaddr + XGMAC_ADDR_HIGH(num)); in xgmac_set_mac_addr()
629 writel(data, ioaddr + XGMAC_ADDR_LOW(num)); in xgmac_set_mac_addr()
631 writel(0, ioaddr + XGMAC_ADDR_HIGH(num)); in xgmac_set_mac_addr()
632 writel(0, ioaddr + XGMAC_ADDR_LOW(num)); in xgmac_set_mac_addr()
671 writel(flow, priv->base + XGMAC_FLOW_CTRL); in xgmac_set_flow_ctrl()
[all …]
/linux-4.1.27/drivers/usb/early/
Dehci-dbgp.c181 writel(ctrl | DBGP_DONE, &ehci_debug->control); in dbgp_wait_until_complete()
206 writel(ctrl | DBGP_GO, &ehci_debug->control); in dbgp_wait_until_done()
252 writel(lo, &ehci_debug->data03); in dbgp_set_data()
253 writel(hi, &ehci_debug->data47); in dbgp_set_data()
291 writel(addr, &ehci_debug->address); in dbgp_bulk_write()
292 writel(pids, &ehci_debug->pids); in dbgp_bulk_write()
317 writel(addr, &ehci_debug->address); in dbgp_bulk_read()
318 writel(pids, &ehci_debug->pids); in dbgp_bulk_read()
358 writel(addr, &ehci_debug->address); in dbgp_control_msg()
359 writel(pids, &ehci_debug->pids); in dbgp_control_msg()
[all …]
/linux-4.1.27/drivers/iio/adc/
Dexynos_adc.c199 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_v1_init_hw()
211 writel(con, ADC_V1_CON(info->regs)); in exynos_adc_v1_exit_hw()
216 writel(1, ADC_V1_INTCLR(info->regs)); in exynos_adc_v1_clear_irq()
224 writel(addr, ADC_V1_MUX(info->regs)); in exynos_adc_v1_start_conv()
227 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
250 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv()
253 writel(addr, ADC_S3C2410_MUX(info->regs)); in exynos_adc_s3c2416_start_conv()
256 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv()
274 writel(addr, ADC_S3C2410_MUX(info->regs)); in exynos_adc_s3c2443_start_conv()
277 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_s3c2443_start_conv()
[all …]
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-coh901.c255 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set()
257 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set()
272 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input()
299 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output()
378 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set()
382 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set()
390 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
398 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
406 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set()
436 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_toggle_trigger()
[all …]
/linux-4.1.27/drivers/ide/
Dpalm_bk3710.c94 writel(val32, base + BK3710_UDMASTB); in palm_bk3710_setudmamode()
99 writel(val32, base + BK3710_UDMATRP); in palm_bk3710_setudmamode()
104 writel(val32, base + BK3710_UDMAENV); in palm_bk3710_setudmamode()
132 writel(val32, base + BK3710_DMASTB); in palm_bk3710_setdmamode()
136 writel(val32, base + BK3710_DMARCVR); in palm_bk3710_setdmamode()
162 writel(val32, base + BK3710_DATSTB); in palm_bk3710_setpiomode()
166 writel(val32, base + BK3710_DATRCVR); in palm_bk3710_setpiomode()
184 writel(val32, base + BK3710_REGSTB); in palm_bk3710_setpiomode()
188 writel(val32, base + BK3710_REGRCVR); in palm_bk3710_setpiomode()
258 writel(0x001, base + BK3710_MISCCTL); in palm_bk3710_chipinit()
[all …]
/linux-4.1.27/sound/soc/spear/
Dspdif_in.c52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_configure()
53 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_configure()
74 writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_shutdown()
91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_format()
130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
131 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_trigger()
139 writel(ctrl, host->io_base + SPDIF_IN_CTRL); in spdif_in_trigger()
140 writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK); in spdif_in_trigger()
196 writel(0, host->io_base + SPDIF_IN_IRQ); in spdif_in_irq()
/linux-4.1.27/drivers/memory/
Demif.c298 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); in set_lpmode()
846 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); in get_temperature_level()
852 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); in get_temperature_level()
876 writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); in setup_registers()
877 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); in setup_registers()
878 writel(regs->pwr_mgmt_ctrl_shdw, in setup_registers()
884 writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); in setup_registers()
885 writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); in setup_registers()
886 writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); in setup_registers()
910 writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); in setup_volt_sensitive_regs()
[all …]
/linux-4.1.27/drivers/mtd/devices/
Dspear_smi.c231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
234 writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE, in spear_smi_read_sr()
248 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
389 writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1); in spear_smi_write_enable()
392 writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2); in spear_smi_write_enable()
398 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_write_enable()
[all …]
/linux-4.1.27/arch/arm/mach-omap1/
Dtime.c82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start()
103 writel(load_val, &timer->load_tim); in omap_mpu_timer_start()
105 writel(timerflags, &timer->cntl); in omap_mpu_timer_start()
112 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
/linux-4.1.27/sound/soc/intel/haswell/
Dsst-haswell-dsp.c258 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D3()
265 writel(val, sst->addr.pci_cfg + SST_VDRTCTL0); in hsw_set_dsp_D3()
270 writel(val, sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D3()
279 writel(val, sst->addr.pci_cfg + SST_PMCS); in hsw_set_dsp_D3()
285 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D3()
314 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D0()
319 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); in hsw_set_dsp_D0()
324 writel(reg, sst->addr.pci_cfg + SST_PMCS); in hsw_set_dsp_D0()
358 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D0()
365 writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); in hsw_set_dsp_D0()
[all …]

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