Lines Matching refs:writel
224 writel(tmp, &dev->regs->irqmsk); in udc_mask_unused_interrupts()
227 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk); in udc_mask_unused_interrupts()
244 writel(tmp, &dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
265 writel(tmp, &dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
342 writel(tmp, &dev->ep[ep->num].regs->ctl); in udc_ep_enable()
349 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
365 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
373 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
384 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
413 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
418 writel(tmp, &dev->regs->ep_irqmsk); in udc_ep_enable()
427 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
452 writel(tmp, &ep->regs->ctl); in ep_init()
458 writel(tmp, ®s->ep_irqmsk); in ep_init()
464 writel(tmp, &ep->regs->ctl); in ep_init()
468 writel(tmp, &ep->regs->sts); in ep_init()
473 writel(tmp, &ep->regs->ctl); in ep_init()
477 writel(0, &ep->regs->desptr); in ep_init()
639 writel(*(buf + i), ep->txfifo); in udc_txfifo_write()
648 writel(0, &ep->regs->confirm); in udc_txfifo_write()
804 writel(tmp, &ep->regs->ctl); in prep_dma()
1044 writel(tmp, &dev->regs->ctl); in udc_set_rde()
1107 writel(tmp, &dev->regs->ctl); in udc_queue()
1115 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_queue()
1146 writel(tmp, &dev->regs->ctl); in udc_queue()
1161 writel(req->td_phys, &ep->regs->desptr); in udc_queue()
1167 writel(tmp, &ep->regs->ctl); in udc_queue()
1176 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1182 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1277 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE), in udc_dequeue()
1289 writel(ep->bna_dummy_req->td_phys, in udc_dequeue()
1292 writel(tmp, &udc->regs->ctl); in udc_dequeue()
1335 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1357 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1456 writel(tmp, &dev->regs->cfg); in startup_registers()
1482 writel(tmp, &dev->regs->ctl); in udc_basic_init()
1491 writel(tmp, &dev->regs->cfg); in udc_basic_init()
1557 writel(reg, &dev->ep[tmp].regs->ctl); in udc_setup_endpoints()
1664 writel(tmp, &dev->regs->cfg); in udc_tasklet_disconnect()
1681 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts); in udc_soft_reset()
1683 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts); in udc_soft_reset()
1686 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_soft_reset()
1708 writel(tmp, &udc->regs->ctl); in udc_timer_function()
1765 writel(tmp, &ep->regs->ctl); in udc_handle_halt_state()
1816 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1830 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); in activate_control_endpoints()
1840 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1850 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1860 writel(tmp, &dev->csr->ne[0]); in activate_control_endpoints()
1866 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma, in activate_control_endpoints()
1868 writel(dev->ep[UDC_EP0OUT_IX].td_phys, in activate_control_endpoints()
1887 writel(tmp, &dev->regs->ctl); in activate_control_endpoints()
1893 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1900 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in activate_control_endpoints()
1939 writel(tmp, &dev->regs->ctl); in amd5536_udc_start()
1980 writel(tmp, &dev->regs->ctl); in amd5536_udc_stop()
1999 writel(reg, &dev->ep[tmp].regs->ctl); in udc_process_cnak_queue()
2010 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_process_cnak_queue()
2065 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); in udc_data_out_isr()
2079 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_out_isr()
2196 writel(req->td_phys, in udc_data_out_isr()
2209 writel(ep->bna_dummy_req->td_phys, in udc_data_out_isr()
2253 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts); in udc_data_out_isr()
2282 writel(epsts, &ep->regs->sts); in udc_data_in_isr()
2294 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_in_isr()
2333 writel(tmp, &dev->regs->ep_irqmsk); in udc_data_in_isr()
2384 writel(req->td_phys, &ep->regs->desptr); in udc_data_in_isr()
2396 writel(tmp, &ep->regs->ctl); in udc_data_in_isr()
2405 writel(tmp, in udc_data_in_isr()
2410 writel(epsts, &ep->regs->sts); in udc_data_in_isr()
2433 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts); in udc_control_out_isr()
2439 writel(AMD_BIT(UDC_EPSTS_BNA), in udc_control_out_isr()
2460 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2466 writel(UDC_EPSTS_OUT_CLEAR, in udc_control_out_isr()
2495 writel(ep->bna_dummy_req->td_phys, in udc_control_out_isr()
2546 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2553 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2562 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_control_out_isr()
2569 writel(UDC_EPSTS_OUT_CLEAR, in udc_control_out_isr()
2576 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts); in udc_control_out_isr()
2598 writel(dev->ep[UDC_EP0OUT_IX].td_phys, in udc_control_out_isr()
2645 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts); in udc_control_in_isr()
2654 writel(AMD_BIT(UDC_EPSTS_TDC), in udc_control_in_isr()
2663 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2671 writel(tmp, &ep->regs->ctl); in udc_control_in_isr()
2680 writel(req->td_phys, &ep->regs->desptr); in udc_control_in_isr()
2692 writel(tmp, in udc_control_in_isr()
2724 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2781 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2787 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2840 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2846 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2896 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); in udc_dev_isr()
2897 writel(tmp, &dev->regs->cfg); in udc_dev_isr()
2908 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
2952 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
2992 writel(ep_irq, &dev->regs->ep_irqsts); in udc_irq()
3008 writel(reg, &dev->regs->irqsts); in udc_irq()
3070 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_pci_remove()
3309 writel(reg, &dev->regs->ctl); in udc_probe()
3332 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()
3334 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()