469 #define __kick_rx(dev)	writel(CR_RXE, dev->base + CR)
477 		writel(dev->rx_info.phy_descs +  in kick_rx()
634 			writel(readl(dev->base + TXCFG)  in phy_intr()
637 			writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,  in phy_intr()
640 			writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,  in phy_intr()
651 			writel((readl(dev->base + TXCFG)  in phy_intr()
654 			writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,  in phy_intr()
657 			writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,  in phy_intr()
677 			writel(readl(dev->base + TXCFG)  in phy_intr()
680 			writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,  in phy_intr()
683 			writel(readl(dev->base + TXCFG)  in phy_intr()
686 			writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),  in phy_intr()
692 			writel(new_cfg, dev->base + CFG);  in phy_intr()
735 	writel(0, dev->base + RXDP_HI);  in ns83820_setup_rx()
736 	writel(dev->rx_info.phy_descs, dev->base + RXDP);  in ns83820_setup_rx()
744 		writel(0x0001, dev->base + CCSR);  in ns83820_setup_rx()
745 		writel(0, dev->base + RFCR);  in ns83820_setup_rx()
746 		writel(0x7fc00000, dev->base + RFCR);  in ns83820_setup_rx()
747 		writel(0xffc00000, dev->base + RFCR);  in ns83820_setup_rx()
766 		writel(dev->IMR_cache, dev->base + IMR);  in ns83820_setup_rx()
767 		writel(1, dev->base + IER);  in ns83820_setup_rx()
787 	writel(dev->IMR_cache, dev->base + IMR);  in ns83820_cleanup_rx()
798 	writel(0, dev->base + RXDP_HI);  in ns83820_cleanup_rx()
799 	writel(0, dev->base + RXDP);  in ns83820_cleanup_rx()
945 	writel(ihr, dev->base + IHR);
949 	writel(dev->IMR_cache, dev->base + IMR);
962 	writel(CR_TXE, dev->base + CR);
1314 				writel(readl(dev->base + TXCFG)
1317 				writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1320 				writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1338 			writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1340 			writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1347 			writel(0x00000000, dev->base + TBICR);
1386 	writel(0, dev->base + IMR);
1387 	writel(0, dev->base + IER);
1437 		writel(dev->IMR_cache, dev->base + IMR);
1459 		writel(CR_RXE, dev->base + CR);
1494 			writel(dev->IMR_cache, dev->base + IMR);
1508 		writel(dev->IMR_cache, dev->base + IMR);
1522 		writel(dev->ihr, dev->base + IHR);
1529 	writel(which, dev->base + CR);
1631 	writel(0, dev->base + PQCR);
1648 	writel(0, dev->base + TXDP_HI);
1649 	writel(desc, dev->base + TXDP);
1674 		writel(i*2, dev->base + RFCR);
1711 	writel(val & ~RFCR_RFEN, rfcr);
1712 	writel(val, rfcr);
1728 	writel(enable, dev->base + PTSCR);
1760 	writel(dev->MEAR_cache, dev->base + MEAR);
1771 	writel(dev->MEAR_cache, dev->base + MEAR);
1779 	writel(dev->MEAR_cache, dev->base + MEAR);
1793 	writel(dev->MEAR_cache, dev->base + MEAR);
1802 	writel(dev->MEAR_cache, dev->base + MEAR);
2040 	writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2084 		writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2087 		writel(readl(dev->base + TANAR)
2092 		writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2094 		writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2100 	writel(dev->CFG_cache, dev->base + CFG);
2105 		writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2107 		writel(dev->CFG_cache, dev->base + CFG);
2114 		writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2124 	writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2129 	writel(0x000, dev->base + IHR);
2130 	writel(0x100, dev->base + IHR);
2131 	writel(0x000, dev->base + IHR);
2139 	writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2145 	writel(0, dev->base + PQCR);
2165 	writel(VRCR_INIT_VALUE, dev->base + VRCR);
2176 	writel(VTCR_INIT_VALUE, dev->base + VTCR);
2180 	writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2185 	writel(0, dev->base + WCSR);