28 	writel(cfg, dev->regs + FIMC_REG_CISRCFMT);  in fimc_hw_reset()
33 	writel(cfg, dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_reset()
38 	writel(cfg, dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_reset()
97 		writel(cfg, dev->regs + FIMC_REG_CITRGFMT);  in fimc_hw_set_rotation()
103 		writel(flip, dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_set_rotation()
142 	writel(cfg, dev->regs + FIMC_REG_CITRGFMT);  in fimc_hw_set_target_format()
147 	writel(cfg, dev->regs + FIMC_REG_CITAREA);  in fimc_hw_set_target_format()
157 	writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);  in fimc_hw_set_out_dma_size()
165 	writel(cfg, dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_set_out_dma_size()
179 	writel(cfg, dev->regs + FIMC_REG_CIOYOFF);  in fimc_hw_set_out_dma()
182 	writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);  in fimc_hw_set_out_dma()
185 	writel(cfg, dev->regs + FIMC_REG_CIOCROFF);  in fimc_hw_set_out_dma()
211 	writel(cfg, dev->regs + FIMC_REG_CIOCTRL);  in fimc_hw_set_out_dma()
221 	writel(cfg, dev->regs + FIMC_REG_ORGISIZE);  in fimc_hw_en_autoload()
231 	writel(cfg, dev->regs + FIMC_REG_CIOCTRL);  in fimc_hw_en_lastirq()
244 	writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);  in fimc_hw_set_prescaler()
247 	writel(cfg, dev->regs + FIMC_REG_CISCPREDST);  in fimc_hw_set_prescaler()
311 	writel(cfg, dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_scaler()
333 		writel(cfg, dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_mainscaler()
341 		writel(cfg, dev->regs + FIMC_REG_CIEXTEN);  in fimc_hw_set_mainscaler()
345 		writel(cfg, dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_mainscaler()
363 	writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);  in fimc_hw_enable_capture()
371 	writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);  in fimc_hw_disable_capture()
388 	writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);  in fimc_hw_set_effect()
403 	writel(cfg, dev->regs + FIMC_REG_CIOCTRL);  in fimc_hw_set_rgb_alpha()
419 	writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);  in fimc_hw_set_in_dma_size()
420 	writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);  in fimc_hw_set_in_dma_size()
432 	writel(cfg, dev->regs + FIMC_REG_CIIYOFF);  in fimc_hw_set_in_dma()
435 	writel(cfg, dev->regs + FIMC_REG_CIICBOFF);  in fimc_hw_set_in_dma()
438 	writel(cfg, dev->regs + FIMC_REG_CIICROFF);  in fimc_hw_set_in_dma()
490 	writel(cfg, dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_set_in_dma()
502 	writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);  in fimc_hw_set_in_dma()
518 	writel(cfg, dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_set_input_path()
529 	writel(cfg, dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_set_output_path()
536 	writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);  in fimc_hw_set_input_addr()
538 	writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));  in fimc_hw_set_input_addr()
539 	writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));  in fimc_hw_set_input_addr()
540 	writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));  in fimc_hw_set_input_addr()
543 	writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);  in fimc_hw_set_input_addr()
551 		writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));  in fimc_hw_set_output_addr()
552 		writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));  in fimc_hw_set_output_addr()
553 		writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));  in fimc_hw_set_output_addr()
583 	writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);  in fimc_hw_set_camera_polarity()
645 	writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);  in fimc_hw_set_camera_source()
659 	writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);  in fimc_hw_set_camera_offset()
665 	writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);  in fimc_hw_set_camera_offset()
708 		writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);  in fimc_hw_set_camera_type()
729 	writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);  in fimc_hw_set_camera_type()
738 	writel(cfg, dev->regs + FIMC_REG_CIGCTRL);  in fimc_hw_clear_irq()
748 	writel(cfg, dev->regs + FIMC_REG_CISCCTRL);  in fimc_hw_enable_scaler()
758 	writel(cfg, dev->regs + FIMC_REG_MSCTRL);  in fimc_hw_activate_input_dma()