101 	writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);  in xgene_ahci_init_memram()
171 		writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);  in xgene_ahci_restart_engine()
213 		writel(port_fbs, port_mmio + PORT_FBS);  in xgene_ahci_qc_issue()
283 	writel(val, mmio + PORTCFG);  in xgene_ahci_set_phy_cfg()
286 	writel(0x0001fffe, mmio + PORTPHY1CFG);  in xgene_ahci_set_phy_cfg()
288 	writel(0x28183219, mmio + PORTPHY2CFG);  in xgene_ahci_set_phy_cfg()
290 	writel(0x13081008, mmio + PORTPHY3CFG);  in xgene_ahci_set_phy_cfg()
292 	writel(0x00480815, mmio + PORTPHY4CFG);  in xgene_ahci_set_phy_cfg()
297 	writel(val, mmio + PORTPHY5CFG);  in xgene_ahci_set_phy_cfg()
302 	writel(val, mmio + PORTAXICFG);  in xgene_ahci_set_phy_cfg()
307 	writel(val, mmio + PORTRANSCFG);  in xgene_ahci_set_phy_cfg()
392 	writel(val, port_mmio + PORT_SCR_ERR);  in xgene_ahci_do_hardreset()
423 	writel(portcmd_saved, port_mmio + PORT_CMD);  in xgene_ahci_hardreset()
424 	writel(portclb_saved, port_mmio + PORT_LST_ADDR);  in xgene_ahci_hardreset()
425 	writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);  in xgene_ahci_hardreset()
426 	writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);  in xgene_ahci_hardreset()
427 	writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);  in xgene_ahci_hardreset()
474 	writel(port_fbs, port_mmio + PORT_FBS);  in xgene_ahci_pmp_softreset()
524 	writel(port_fbs, port_mmio + PORT_FBS);  in xgene_ahci_softreset()
537 			writel(port_fbs_save, port_mmio + PORT_FBS);  in xgene_ahci_softreset()
578 	writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);  in xgene_ahci_hw_init()
580 	writel(0, ctx->csr_core + INTSTATUSMASK);  in xgene_ahci_hw_init()
585 	writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);  in xgene_ahci_hw_init()
587 	writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);  in xgene_ahci_hw_init()
591 	writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);  in xgene_ahci_hw_init()
592 	writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);  in xgene_ahci_hw_init()
593 	writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);  in xgene_ahci_hw_init()
594 	writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);  in xgene_ahci_hw_init()
600 	writel(val, ctx->csr_core + BUSCTLREG);  in xgene_ahci_hw_init()
605 	writel(val, ctx->csr_core + IOFMSTRWAUX);  in xgene_ahci_hw_init()
623 	writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);  in xgene_ahci_mux_select()