255 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));  in u300_gpio_set()
257 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));  in u300_gpio_set()
272 	writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_direction_input()
299 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_direction_output()
378 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));  in u300_gpio_config_set()
382 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));  in u300_gpio_config_set()
390 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_config_set()
398 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_config_set()
406 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_config_set()
436 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_toggle_trigger()
441 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_toggle_trigger()
471 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_gpio_irq_type()
477 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_gpio_irq_type()
497 	writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));  in u300_gpio_irq_enable()
511 	writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));  in u300_gpio_irq_disable()
538 	writel(val, U300_PIN_REG(pinoffset, iev));  in u300_gpio_irq_handler()
697 	writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,  in u300_gpio_probe()
736 		writel(0x0, gpio->base + portno * gpio->stride + ifr);  in u300_gpio_probe()
771 	writel(0x00000000U, gpio->base + U300_GPIO_CR);  in u300_gpio_remove()