1/*
2 * Copyright (C) 2014 Marvell Technology Group Ltd.
3 *
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
5 * Jisheng Zhang <jszhang@marvell.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/gpio.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/of_gpio.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/reset.h>
20
21#define USB_PHY_PLL		0x04
22#define USB_PHY_PLL_CONTROL	0x08
23#define USB_PHY_TX_CTRL0	0x10
24#define USB_PHY_TX_CTRL1	0x14
25#define USB_PHY_TX_CTRL2	0x18
26#define USB_PHY_RX_CTRL		0x20
27#define USB_PHY_ANALOG		0x34
28
29/* USB_PHY_PLL */
30#define CLK_REF_DIV(x)		((x) << 4)
31#define FEEDBACK_CLK_DIV(x)	((x) << 8)
32
33/* USB_PHY_PLL_CONTROL */
34#define CLK_STABLE		BIT(0)
35#define PLL_CTRL_PIN		BIT(1)
36#define PLL_CTRL_REG		BIT(2)
37#define PLL_ON			BIT(3)
38#define PHASE_OFF_TOL_125	(0x0 << 5)
39#define PHASE_OFF_TOL_250	BIT(5)
40#define KVC0_CALIB		(0x0 << 9)
41#define KVC0_REG_CTRL		BIT(9)
42#define KVC0_HIGH		(0x0 << 10)
43#define KVC0_LOW		(0x3 << 10)
44#define CLK_BLK_EN		BIT(13)
45
46/* USB_PHY_TX_CTRL0 */
47#define EXT_HS_RCAL_EN		BIT(3)
48#define EXT_FS_RCAL_EN		BIT(4)
49#define IMPCAL_VTH_DIV(x)	((x) << 5)
50#define EXT_RS_RCAL_DIV(x)	((x) << 8)
51#define EXT_FS_RCAL_DIV(x)	((x) << 12)
52
53/* USB_PHY_TX_CTRL1 */
54#define TX_VDD15_14		(0x0 << 4)
55#define TX_VDD15_15		BIT(4)
56#define TX_VDD15_16		(0x2 << 4)
57#define TX_VDD15_17		(0x3 << 4)
58#define TX_VDD12_VDD		(0x0 << 6)
59#define TX_VDD12_11		BIT(6)
60#define TX_VDD12_12		(0x2 << 6)
61#define TX_VDD12_13		(0x3 << 6)
62#define LOW_VDD_EN		BIT(8)
63#define TX_OUT_AMP(x)		((x) << 9)
64
65/* USB_PHY_TX_CTRL2 */
66#define TX_CHAN_CTRL_REG(x)	((x) << 0)
67#define DRV_SLEWRATE(x)		((x) << 4)
68#define IMP_CAL_FS_HS_DLY_0	(0x0 << 6)
69#define IMP_CAL_FS_HS_DLY_1	BIT(6)
70#define IMP_CAL_FS_HS_DLY_2	(0x2 << 6)
71#define IMP_CAL_FS_HS_DLY_3	(0x3 << 6)
72#define FS_DRV_EN_MASK(x)	((x) << 8)
73#define HS_DRV_EN_MASK(x)	((x) << 12)
74
75/* USB_PHY_RX_CTRL */
76#define PHASE_FREEZE_DLY_2_CL	(0x0 << 0)
77#define PHASE_FREEZE_DLY_4_CL	BIT(0)
78#define ACK_LENGTH_8_CL		(0x0 << 2)
79#define ACK_LENGTH_12_CL	BIT(2)
80#define ACK_LENGTH_16_CL	(0x2 << 2)
81#define ACK_LENGTH_20_CL	(0x3 << 2)
82#define SQ_LENGTH_3		(0x0 << 4)
83#define SQ_LENGTH_6		BIT(4)
84#define SQ_LENGTH_9		(0x2 << 4)
85#define SQ_LENGTH_12		(0x3 << 4)
86#define DISCON_THRESHOLD_260	(0x0 << 6)
87#define DISCON_THRESHOLD_270	BIT(6)
88#define DISCON_THRESHOLD_280	(0x2 << 6)
89#define DISCON_THRESHOLD_290	(0x3 << 6)
90#define SQ_THRESHOLD(x)		((x) << 8)
91#define LPF_COEF(x)		((x) << 12)
92#define INTPL_CUR_10		(0x0 << 14)
93#define INTPL_CUR_20		BIT(14)
94#define INTPL_CUR_30		(0x2 << 14)
95#define INTPL_CUR_40		(0x3 << 14)
96
97/* USB_PHY_ANALOG */
98#define ANA_PWR_UP		BIT(1)
99#define ANA_PWR_DOWN		BIT(2)
100#define V2I_VCO_RATIO(x)	((x) << 7)
101#define R_ROTATE_90		(0x0 << 10)
102#define R_ROTATE_0		BIT(10)
103#define MODE_TEST_EN		BIT(11)
104#define ANA_TEST_DC_CTRL(x)	((x) << 12)
105
106static const u32 phy_berlin_pll_dividers[] = {
107	/* Berlin 2 */
108	CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
109	/* Berlin 2CD/Q */
110	CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
111};
112
113struct phy_berlin_usb_priv {
114	void __iomem		*base;
115	struct reset_control	*rst_ctrl;
116	u32			pll_divider;
117};
118
119static int phy_berlin_usb_power_on(struct phy *phy)
120{
121	struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
122
123	reset_control_reset(priv->rst_ctrl);
124
125	writel(priv->pll_divider,
126	       priv->base + USB_PHY_PLL);
127	writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
128	       CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
129	writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
130	       priv->base + USB_PHY_ANALOG);
131	writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
132	       DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
133	       INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
134
135	writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
136	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
137	       priv->base + USB_PHY_TX_CTRL0);
138
139	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
140	       EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
141
142	writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
143	       priv->base + USB_PHY_TX_CTRL0);
144	writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
145	       FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
146
147	return 0;
148}
149
150static struct phy_ops phy_berlin_usb_ops = {
151	.power_on	= phy_berlin_usb_power_on,
152	.owner		= THIS_MODULE,
153};
154
155static const struct of_device_id phy_berlin_sata_of_match[] = {
156	{
157		.compatible = "marvell,berlin2-usb-phy",
158		.data = &phy_berlin_pll_dividers[0],
159	},
160	{
161		.compatible = "marvell,berlin2cd-usb-phy",
162		.data = &phy_berlin_pll_dividers[1],
163	},
164	{ },
165};
166MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
167
168static int phy_berlin_usb_probe(struct platform_device *pdev)
169{
170	const struct of_device_id *match =
171		of_match_device(phy_berlin_sata_of_match, &pdev->dev);
172	struct phy_berlin_usb_priv *priv;
173	struct resource *res;
174	struct phy *phy;
175	struct phy_provider *phy_provider;
176
177	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
178	if (!priv)
179		return -ENOMEM;
180
181	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
182	priv->base = devm_ioremap_resource(&pdev->dev, res);
183	if (IS_ERR(priv->base))
184		return PTR_ERR(priv->base);
185
186	priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
187	if (IS_ERR(priv->rst_ctrl))
188		return PTR_ERR(priv->rst_ctrl);
189
190	priv->pll_divider = *((u32 *)match->data);
191
192	phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
193	if (IS_ERR(phy)) {
194		dev_err(&pdev->dev, "failed to create PHY\n");
195		return PTR_ERR(phy);
196	}
197
198	platform_set_drvdata(pdev, priv);
199	phy_set_drvdata(phy, priv);
200
201	phy_provider =
202		devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
203	return PTR_ERR_OR_ZERO(phy_provider);
204}
205
206static struct platform_driver phy_berlin_usb_driver = {
207	.probe	= phy_berlin_usb_probe,
208	.driver	= {
209		.name		= "phy-berlin-usb",
210		.owner		= THIS_MODULE,
211		.of_match_table	= phy_berlin_sata_of_match,
212	 },
213};
214module_platform_driver(phy_berlin_usb_driver);
215
216MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
217MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
218MODULE_LICENSE("GPL");
219