40 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_func_reset()
51 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);  in exynos_mipi_dsi_sw_reset()
62 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_sw_reset_release()
90 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);  in exynos_mipi_dsi_set_interrupt_mask()
100 	writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);  in exynos_mipi_dsi_init_fifo_pointer()
104 	writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);  in exynos_mipi_dsi_init_fifo_pointer()
113 	writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);  in exynos_mipi_dsi_set_phy_tunning()
128 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_stand_by()
139 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_disp_resol()
145 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);  in exynos_mipi_dsi_set_main_disp_resol()
161 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);  in exynos_mipi_dsi_set_main_disp_vporch()
174 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);  in exynos_mipi_dsi_set_main_disp_hporch()
188 	writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);  in exynos_mipi_dsi_set_main_disp_sync_area()
199 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);  in exynos_mipi_dsi_set_sub_disp_resol()
204 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);  in exynos_mipi_dsi_set_sub_disp_resol()
207 	writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);  in exynos_mipi_dsi_set_sub_disp_resol()
226 	writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_init_config()
250 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_display_config()
265 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_enable_lane()
277 	writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);  in exynos_mipi_dsi_set_data_lane_number()
292 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);  in exynos_mipi_dsi_enable_afc()
303 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_pll_bypass()
313 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_set_pll_pms()
324 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_pll_freq_band()
337 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_pll_freq()
343 	writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);  in exynos_mipi_dsi_pll_stable_time()
353 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_enable_pll()
364 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_set_byte_clock_src()
375 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_byte_clock()
388 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_set_esc_clk_prs()
402 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_esc_clk_on_lane()
413 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_force_dphy_stop_state()
442 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_stop_state_counter()
453 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);  in exynos_mipi_dsi_set_bta_timeout()
464 	writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);  in exynos_mipi_dsi_set_lpdr_timeout()
477 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_cpu_transfer_mode()
490 	writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);  in exynos_mipi_dsi_set_lcdc_transfer_mode()
501 	writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);  in exynos_mipi_dsi_enable_hs_clock()
512 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);  in exynos_mipi_dsi_dp_dn_swap()
523 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_hs_zero_ctrl()
533 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);  in exynos_mipi_dsi_prep_ctrl()
548 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_clear_interrupt()
561 	writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);  in exynos_mipi_dsi_set_interrupt()
583 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);  in exynos_mipi_dsi_wr_tx_header()
591 	writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);  in exynos_mipi_dsi_rd_tx_header()
610 	writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +  in _exynos_mipi_dsi_clear_frame_done()
617 	writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);  in exynos_mipi_dsi_wr_tx_data()