1/* 2 * Copyright (C) 2009 Samsung Electronics Ltd. 3 * Jaswinder Singh <jassi.brar@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/init.h> 17#include <linux/module.h> 18#include <linux/interrupt.h> 19#include <linux/delay.h> 20#include <linux/clk.h> 21#include <linux/dma-mapping.h> 22#include <linux/dmaengine.h> 23#include <linux/platform_device.h> 24#include <linux/pm_runtime.h> 25#include <linux/spi/spi.h> 26#include <linux/gpio.h> 27#include <linux/of.h> 28#include <linux/of_gpio.h> 29 30#include <linux/platform_data/spi-s3c64xx.h> 31 32#define MAX_SPI_PORTS 6 33#define S3C64XX_SPI_QUIRK_POLL (1 << 0) 34#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 35 36/* Registers and bit-fields */ 37 38#define S3C64XX_SPI_CH_CFG 0x00 39#define S3C64XX_SPI_CLK_CFG 0x04 40#define S3C64XX_SPI_MODE_CFG 0x08 41#define S3C64XX_SPI_SLAVE_SEL 0x0C 42#define S3C64XX_SPI_INT_EN 0x10 43#define S3C64XX_SPI_STATUS 0x14 44#define S3C64XX_SPI_TX_DATA 0x18 45#define S3C64XX_SPI_RX_DATA 0x1C 46#define S3C64XX_SPI_PACKET_CNT 0x20 47#define S3C64XX_SPI_PENDING_CLR 0x24 48#define S3C64XX_SPI_SWAP_CFG 0x28 49#define S3C64XX_SPI_FB_CLK 0x2C 50 51#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 52#define S3C64XX_SPI_CH_SW_RST (1<<5) 53#define S3C64XX_SPI_CH_SLAVE (1<<4) 54#define S3C64XX_SPI_CPOL_L (1<<3) 55#define S3C64XX_SPI_CPHA_B (1<<2) 56#define S3C64XX_SPI_CH_RXCH_ON (1<<1) 57#define S3C64XX_SPI_CH_TXCH_ON (1<<0) 58 59#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 60#define S3C64XX_SPI_CLKSEL_SRCSHFT 9 61#define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 62#define S3C64XX_SPI_PSR_MASK 0xff 63 64#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 65#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 66#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 67#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 68#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 69#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 70#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 71#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 72#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 73#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 74#define S3C64XX_SPI_MODE_4BURST (1<<0) 75 76#define S3C64XX_SPI_SLAVE_AUTO (1<<1) 77#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) 78#define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4) 79 80#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 81#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 82#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 83#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 84#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 85#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 86#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 87 88#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 89#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 90#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 91#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 92#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 93#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 94 95#define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 96 97#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 98#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 99#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 100#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 101#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 102 103#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 104#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 105#define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 106#define S3C64XX_SPI_SWAP_RX_EN (1<<4) 107#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 108#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 109#define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 110#define S3C64XX_SPI_SWAP_TX_EN (1<<0) 111 112#define S3C64XX_SPI_FBCLK_MSK (3<<0) 113 114#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 115#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 116 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 117#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) 118#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ 119 FIFO_LVL_MASK(i)) 120 121#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 122#define S3C64XX_SPI_TRAILCNT_OFF 19 123 124#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 125 126#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 127#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) 128 129#define RXBUSY (1<<2) 130#define TXBUSY (1<<3) 131 132struct s3c64xx_spi_dma_data { 133 struct dma_chan *ch; 134 enum dma_transfer_direction direction; 135 unsigned int dmach; 136}; 137 138/** 139 * struct s3c64xx_spi_info - SPI Controller hardware info 140 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. 141 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. 142 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 143 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 144 * @clk_from_cmu: True, if the controller does not include a clock mux and 145 * prescaler unit. 146 * 147 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 148 * differ in some aspects such as the size of the fifo and spi bus clock 149 * setup. Such differences are specified to the driver using this structure 150 * which is provided as driver data to the driver. 151 */ 152struct s3c64xx_spi_port_config { 153 int fifo_lvl_mask[MAX_SPI_PORTS]; 154 int rx_lvl_offset; 155 int tx_st_done; 156 int quirks; 157 bool high_speed; 158 bool clk_from_cmu; 159}; 160 161/** 162 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 163 * @clk: Pointer to the spi clock. 164 * @src_clk: Pointer to the clock used to generate SPI signals. 165 * @master: Pointer to the SPI Protocol master. 166 * @cntrlr_info: Platform specific data for the controller this driver manages. 167 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. 168 * @lock: Controller specific lock. 169 * @state: Set of FLAGS to indicate status. 170 * @rx_dmach: Controller's DMA channel for Rx. 171 * @tx_dmach: Controller's DMA channel for Tx. 172 * @sfr_start: BUS address of SPI controller regs. 173 * @regs: Pointer to ioremap'ed controller registers. 174 * @irq: interrupt 175 * @xfer_completion: To indicate completion of xfer task. 176 * @cur_mode: Stores the active configuration of the controller. 177 * @cur_bpw: Stores the active bits per word settings. 178 * @cur_speed: Stores the active xfer clock speed. 179 */ 180struct s3c64xx_spi_driver_data { 181 void __iomem *regs; 182 struct clk *clk; 183 struct clk *src_clk; 184 struct platform_device *pdev; 185 struct spi_master *master; 186 struct s3c64xx_spi_info *cntrlr_info; 187 struct spi_device *tgl_spi; 188 spinlock_t lock; 189 unsigned long sfr_start; 190 struct completion xfer_completion; 191 unsigned state; 192 unsigned cur_mode, cur_bpw; 193 unsigned cur_speed; 194 struct s3c64xx_spi_dma_data rx_dma; 195 struct s3c64xx_spi_dma_data tx_dma; 196 struct s3c64xx_spi_port_config *port_conf; 197 unsigned int port_id; 198}; 199 200static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 201{ 202 void __iomem *regs = sdd->regs; 203 unsigned long loops; 204 u32 val; 205 206 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 207 208 val = readl(regs + S3C64XX_SPI_CH_CFG); 209 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 210 writel(val, regs + S3C64XX_SPI_CH_CFG); 211 212 val = readl(regs + S3C64XX_SPI_CH_CFG); 213 val |= S3C64XX_SPI_CH_SW_RST; 214 val &= ~S3C64XX_SPI_CH_HS_EN; 215 writel(val, regs + S3C64XX_SPI_CH_CFG); 216 217 /* Flush TxFIFO*/ 218 loops = msecs_to_loops(1); 219 do { 220 val = readl(regs + S3C64XX_SPI_STATUS); 221 } while (TX_FIFO_LVL(val, sdd) && loops--); 222 223 if (loops == 0) 224 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 225 226 /* Flush RxFIFO*/ 227 loops = msecs_to_loops(1); 228 do { 229 val = readl(regs + S3C64XX_SPI_STATUS); 230 if (RX_FIFO_LVL(val, sdd)) 231 readl(regs + S3C64XX_SPI_RX_DATA); 232 else 233 break; 234 } while (loops--); 235 236 if (loops == 0) 237 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 238 239 val = readl(regs + S3C64XX_SPI_CH_CFG); 240 val &= ~S3C64XX_SPI_CH_SW_RST; 241 writel(val, regs + S3C64XX_SPI_CH_CFG); 242 243 val = readl(regs + S3C64XX_SPI_MODE_CFG); 244 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 245 writel(val, regs + S3C64XX_SPI_MODE_CFG); 246} 247 248static void s3c64xx_spi_dmacb(void *data) 249{ 250 struct s3c64xx_spi_driver_data *sdd; 251 struct s3c64xx_spi_dma_data *dma = data; 252 unsigned long flags; 253 254 if (dma->direction == DMA_DEV_TO_MEM) 255 sdd = container_of(data, 256 struct s3c64xx_spi_driver_data, rx_dma); 257 else 258 sdd = container_of(data, 259 struct s3c64xx_spi_driver_data, tx_dma); 260 261 spin_lock_irqsave(&sdd->lock, flags); 262 263 if (dma->direction == DMA_DEV_TO_MEM) { 264 sdd->state &= ~RXBUSY; 265 if (!(sdd->state & TXBUSY)) 266 complete(&sdd->xfer_completion); 267 } else { 268 sdd->state &= ~TXBUSY; 269 if (!(sdd->state & RXBUSY)) 270 complete(&sdd->xfer_completion); 271 } 272 273 spin_unlock_irqrestore(&sdd->lock, flags); 274} 275 276static void prepare_dma(struct s3c64xx_spi_dma_data *dma, 277 struct sg_table *sgt) 278{ 279 struct s3c64xx_spi_driver_data *sdd; 280 struct dma_slave_config config; 281 struct dma_async_tx_descriptor *desc; 282 283 memset(&config, 0, sizeof(config)); 284 285 if (dma->direction == DMA_DEV_TO_MEM) { 286 sdd = container_of((void *)dma, 287 struct s3c64xx_spi_driver_data, rx_dma); 288 config.direction = dma->direction; 289 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 290 config.src_addr_width = sdd->cur_bpw / 8; 291 config.src_maxburst = 1; 292 dmaengine_slave_config(dma->ch, &config); 293 } else { 294 sdd = container_of((void *)dma, 295 struct s3c64xx_spi_driver_data, tx_dma); 296 config.direction = dma->direction; 297 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 298 config.dst_addr_width = sdd->cur_bpw / 8; 299 config.dst_maxburst = 1; 300 dmaengine_slave_config(dma->ch, &config); 301 } 302 303 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 304 dma->direction, DMA_PREP_INTERRUPT); 305 306 desc->callback = s3c64xx_spi_dmacb; 307 desc->callback_param = dma; 308 309 dmaengine_submit(desc); 310 dma_async_issue_pending(dma->ch); 311} 312 313static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 314{ 315 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 316 dma_filter_fn filter = sdd->cntrlr_info->filter; 317 struct device *dev = &sdd->pdev->dev; 318 dma_cap_mask_t mask; 319 int ret; 320 321 if (!is_polling(sdd)) { 322 dma_cap_zero(mask); 323 dma_cap_set(DMA_SLAVE, mask); 324 325 /* Acquire DMA channels */ 326 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter, 327 (void *)(long)sdd->rx_dma.dmach, dev, "rx"); 328 if (!sdd->rx_dma.ch) { 329 dev_err(dev, "Failed to get RX DMA channel\n"); 330 ret = -EBUSY; 331 goto out; 332 } 333 spi->dma_rx = sdd->rx_dma.ch; 334 335 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter, 336 (void *)(long)sdd->tx_dma.dmach, dev, "tx"); 337 if (!sdd->tx_dma.ch) { 338 dev_err(dev, "Failed to get TX DMA channel\n"); 339 ret = -EBUSY; 340 goto out_rx; 341 } 342 spi->dma_tx = sdd->tx_dma.ch; 343 } 344 345 return 0; 346 347out_rx: 348 dma_release_channel(sdd->rx_dma.ch); 349out: 350 return ret; 351} 352 353static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) 354{ 355 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 356 357 /* Free DMA channels */ 358 if (!is_polling(sdd)) { 359 dma_release_channel(sdd->rx_dma.ch); 360 dma_release_channel(sdd->tx_dma.ch); 361 } 362 363 return 0; 364} 365 366static bool s3c64xx_spi_can_dma(struct spi_master *master, 367 struct spi_device *spi, 368 struct spi_transfer *xfer) 369{ 370 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 371 372 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; 373} 374 375static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, 376 struct spi_device *spi, 377 struct spi_transfer *xfer, int dma_mode) 378{ 379 void __iomem *regs = sdd->regs; 380 u32 modecfg, chcfg; 381 382 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 383 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 384 385 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 386 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 387 388 if (dma_mode) { 389 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 390 } else { 391 /* Always shift in data in FIFO, even if xfer is Tx only, 392 * this helps setting PCKT_CNT value for generating clocks 393 * as exactly needed. 394 */ 395 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 396 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 397 | S3C64XX_SPI_PACKET_CNT_EN, 398 regs + S3C64XX_SPI_PACKET_CNT); 399 } 400 401 if (xfer->tx_buf != NULL) { 402 sdd->state |= TXBUSY; 403 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 404 if (dma_mode) { 405 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 406 prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 407 } else { 408 switch (sdd->cur_bpw) { 409 case 32: 410 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 411 xfer->tx_buf, xfer->len / 4); 412 break; 413 case 16: 414 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 415 xfer->tx_buf, xfer->len / 2); 416 break; 417 default: 418 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 419 xfer->tx_buf, xfer->len); 420 break; 421 } 422 } 423 } 424 425 if (xfer->rx_buf != NULL) { 426 sdd->state |= RXBUSY; 427 428 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 429 && !(sdd->cur_mode & SPI_CPHA)) 430 chcfg |= S3C64XX_SPI_CH_HS_EN; 431 432 if (dma_mode) { 433 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 434 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 436 | S3C64XX_SPI_PACKET_CNT_EN, 437 regs + S3C64XX_SPI_PACKET_CNT); 438 prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 439 } 440 } 441 442 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 443 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 444} 445 446static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 447 int timeout_ms) 448{ 449 void __iomem *regs = sdd->regs; 450 unsigned long val = 1; 451 u32 status; 452 453 /* max fifo depth available */ 454 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; 455 456 if (timeout_ms) 457 val = msecs_to_loops(timeout_ms); 458 459 do { 460 status = readl(regs + S3C64XX_SPI_STATUS); 461 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 462 463 /* return the actual received data length */ 464 return RX_FIFO_LVL(status, sdd); 465} 466 467static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 468 struct spi_transfer *xfer) 469{ 470 void __iomem *regs = sdd->regs; 471 unsigned long val; 472 u32 status; 473 int ms; 474 475 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 476 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 477 ms += 10; /* some tolerance */ 478 479 val = msecs_to_jiffies(ms) + 10; 480 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 481 482 /* 483 * If the previous xfer was completed within timeout, then 484 * proceed further else return -EIO. 485 * DmaTx returns after simply writing data in the FIFO, 486 * w/o waiting for real transmission on the bus to finish. 487 * DmaRx returns only after Dma read data from FIFO which 488 * needs bus transmission to finish, so we don't worry if 489 * Xfer involved Rx(with or without Tx). 490 */ 491 if (val && !xfer->rx_buf) { 492 val = msecs_to_loops(10); 493 status = readl(regs + S3C64XX_SPI_STATUS); 494 while ((TX_FIFO_LVL(status, sdd) 495 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 496 && --val) { 497 cpu_relax(); 498 status = readl(regs + S3C64XX_SPI_STATUS); 499 } 500 501 } 502 503 /* If timed out while checking rx/tx status return error */ 504 if (!val) 505 return -EIO; 506 507 return 0; 508} 509 510static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 511 struct spi_transfer *xfer) 512{ 513 void __iomem *regs = sdd->regs; 514 unsigned long val; 515 u32 status; 516 int loops; 517 u32 cpy_len; 518 u8 *buf; 519 int ms; 520 521 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 522 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 523 ms += 10; /* some tolerance */ 524 525 val = msecs_to_loops(ms); 526 do { 527 status = readl(regs + S3C64XX_SPI_STATUS); 528 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 529 530 531 /* If it was only Tx */ 532 if (!xfer->rx_buf) { 533 sdd->state &= ~TXBUSY; 534 return 0; 535 } 536 537 /* 538 * If the receive length is bigger than the controller fifo 539 * size, calculate the loops and read the fifo as many times. 540 * loops = length / max fifo size (calculated by using the 541 * fifo mask). 542 * For any size less than the fifo size the below code is 543 * executed atleast once. 544 */ 545 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); 546 buf = xfer->rx_buf; 547 do { 548 /* wait for data to be received in the fifo */ 549 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 550 (loops ? ms : 0)); 551 552 switch (sdd->cur_bpw) { 553 case 32: 554 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 555 buf, cpy_len / 4); 556 break; 557 case 16: 558 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 559 buf, cpy_len / 2); 560 break; 561 default: 562 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 563 buf, cpy_len); 564 break; 565 } 566 567 buf = buf + cpy_len; 568 } while (loops--); 569 sdd->state &= ~RXBUSY; 570 571 return 0; 572} 573 574static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 575{ 576 void __iomem *regs = sdd->regs; 577 u32 val; 578 579 /* Disable Clock */ 580 if (sdd->port_conf->clk_from_cmu) { 581 clk_disable_unprepare(sdd->src_clk); 582 } else { 583 val = readl(regs + S3C64XX_SPI_CLK_CFG); 584 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 585 writel(val, regs + S3C64XX_SPI_CLK_CFG); 586 } 587 588 /* Set Polarity and Phase */ 589 val = readl(regs + S3C64XX_SPI_CH_CFG); 590 val &= ~(S3C64XX_SPI_CH_SLAVE | 591 S3C64XX_SPI_CPOL_L | 592 S3C64XX_SPI_CPHA_B); 593 594 if (sdd->cur_mode & SPI_CPOL) 595 val |= S3C64XX_SPI_CPOL_L; 596 597 if (sdd->cur_mode & SPI_CPHA) 598 val |= S3C64XX_SPI_CPHA_B; 599 600 writel(val, regs + S3C64XX_SPI_CH_CFG); 601 602 /* Set Channel & DMA Mode */ 603 val = readl(regs + S3C64XX_SPI_MODE_CFG); 604 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 605 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 606 607 switch (sdd->cur_bpw) { 608 case 32: 609 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 610 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 611 break; 612 case 16: 613 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 614 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 615 break; 616 default: 617 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 618 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 619 break; 620 } 621 622 writel(val, regs + S3C64XX_SPI_MODE_CFG); 623 624 if (sdd->port_conf->clk_from_cmu) { 625 /* Configure Clock */ 626 /* There is half-multiplier before the SPI */ 627 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); 628 /* Enable Clock */ 629 clk_prepare_enable(sdd->src_clk); 630 } else { 631 /* Configure Clock */ 632 val = readl(regs + S3C64XX_SPI_CLK_CFG); 633 val &= ~S3C64XX_SPI_PSR_MASK; 634 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) 635 & S3C64XX_SPI_PSR_MASK); 636 writel(val, regs + S3C64XX_SPI_CLK_CFG); 637 638 /* Enable Clock */ 639 val = readl(regs + S3C64XX_SPI_CLK_CFG); 640 val |= S3C64XX_SPI_ENCLK_ENABLE; 641 writel(val, regs + S3C64XX_SPI_CLK_CFG); 642 } 643} 644 645#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 646 647static int s3c64xx_spi_prepare_message(struct spi_master *master, 648 struct spi_message *msg) 649{ 650 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 651 struct spi_device *spi = msg->spi; 652 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 653 654 /* If Master's(controller) state differs from that needed by Slave */ 655 if (sdd->cur_speed != spi->max_speed_hz 656 || sdd->cur_mode != spi->mode 657 || sdd->cur_bpw != spi->bits_per_word) { 658 sdd->cur_bpw = spi->bits_per_word; 659 sdd->cur_speed = spi->max_speed_hz; 660 sdd->cur_mode = spi->mode; 661 s3c64xx_spi_config(sdd); 662 } 663 664 /* Configure feedback delay */ 665 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 666 667 return 0; 668} 669 670static int s3c64xx_spi_transfer_one(struct spi_master *master, 671 struct spi_device *spi, 672 struct spi_transfer *xfer) 673{ 674 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 675 int status; 676 u32 speed; 677 u8 bpw; 678 unsigned long flags; 679 int use_dma; 680 681 reinit_completion(&sdd->xfer_completion); 682 683 /* Only BPW and Speed may change across transfers */ 684 bpw = xfer->bits_per_word; 685 speed = xfer->speed_hz ? : spi->max_speed_hz; 686 687 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 688 sdd->cur_bpw = bpw; 689 sdd->cur_speed = speed; 690 s3c64xx_spi_config(sdd); 691 } 692 693 /* Polling method for xfers not bigger than FIFO capacity */ 694 use_dma = 0; 695 if (!is_polling(sdd) && 696 (sdd->rx_dma.ch && sdd->tx_dma.ch && 697 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) 698 use_dma = 1; 699 700 spin_lock_irqsave(&sdd->lock, flags); 701 702 /* Pending only which is to be done */ 703 sdd->state &= ~RXBUSY; 704 sdd->state &= ~TXBUSY; 705 706 enable_datapath(sdd, spi, xfer, use_dma); 707 708 /* Start the signals */ 709 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 710 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 711 else 712 writel(readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL) 713 | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2, 714 sdd->regs + S3C64XX_SPI_SLAVE_SEL); 715 716 spin_unlock_irqrestore(&sdd->lock, flags); 717 718 if (use_dma) 719 status = wait_for_dma(sdd, xfer); 720 else 721 status = wait_for_pio(sdd, xfer); 722 723 if (status) { 724 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 725 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 726 (sdd->state & RXBUSY) ? 'f' : 'p', 727 (sdd->state & TXBUSY) ? 'f' : 'p', 728 xfer->len); 729 730 if (use_dma) { 731 if (xfer->tx_buf != NULL 732 && (sdd->state & TXBUSY)) 733 dmaengine_terminate_all(sdd->tx_dma.ch); 734 if (xfer->rx_buf != NULL 735 && (sdd->state & RXBUSY)) 736 dmaengine_terminate_all(sdd->rx_dma.ch); 737 } 738 } else { 739 flush_fifo(sdd); 740 } 741 742 return status; 743} 744 745static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( 746 struct spi_device *spi) 747{ 748 struct s3c64xx_spi_csinfo *cs; 749 struct device_node *slave_np, *data_np = NULL; 750 u32 fb_delay = 0; 751 752 slave_np = spi->dev.of_node; 753 if (!slave_np) { 754 dev_err(&spi->dev, "device node not found\n"); 755 return ERR_PTR(-EINVAL); 756 } 757 758 data_np = of_get_child_by_name(slave_np, "controller-data"); 759 if (!data_np) { 760 dev_err(&spi->dev, "child node 'controller-data' not found\n"); 761 return ERR_PTR(-EINVAL); 762 } 763 764 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 765 if (!cs) { 766 of_node_put(data_np); 767 return ERR_PTR(-ENOMEM); 768 } 769 770 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 771 cs->fb_delay = fb_delay; 772 of_node_put(data_np); 773 return cs; 774} 775 776/* 777 * Here we only check the validity of requested configuration 778 * and save the configuration in a local data-structure. 779 * The controller is actually configured only just before we 780 * get a message to transfer. 781 */ 782static int s3c64xx_spi_setup(struct spi_device *spi) 783{ 784 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 785 struct s3c64xx_spi_driver_data *sdd; 786 struct s3c64xx_spi_info *sci; 787 int err; 788 789 sdd = spi_master_get_devdata(spi->master); 790 if (spi->dev.of_node) { 791 cs = s3c64xx_get_slave_ctrldata(spi); 792 spi->controller_data = cs; 793 } else if (cs) { 794 /* On non-DT platforms the SPI core will set spi->cs_gpio 795 * to -ENOENT. The GPIO pin used to drive the chip select 796 * is defined by using platform data so spi->cs_gpio value 797 * has to be override to have the proper GPIO pin number. 798 */ 799 spi->cs_gpio = cs->line; 800 } 801 802 if (IS_ERR_OR_NULL(cs)) { 803 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 804 return -ENODEV; 805 } 806 807 if (!spi_get_ctldata(spi)) { 808 if (gpio_is_valid(spi->cs_gpio)) { 809 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, 810 dev_name(&spi->dev)); 811 if (err) { 812 dev_err(&spi->dev, 813 "Failed to get /CS gpio [%d]: %d\n", 814 spi->cs_gpio, err); 815 goto err_gpio_req; 816 } 817 } 818 819 spi_set_ctldata(spi, cs); 820 } 821 822 sci = sdd->cntrlr_info; 823 824 pm_runtime_get_sync(&sdd->pdev->dev); 825 826 /* Check if we can provide the requested rate */ 827 if (!sdd->port_conf->clk_from_cmu) { 828 u32 psr, speed; 829 830 /* Max possible */ 831 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); 832 833 if (spi->max_speed_hz > speed) 834 spi->max_speed_hz = speed; 835 836 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; 837 psr &= S3C64XX_SPI_PSR_MASK; 838 if (psr == S3C64XX_SPI_PSR_MASK) 839 psr--; 840 841 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 842 if (spi->max_speed_hz < speed) { 843 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 844 psr++; 845 } else { 846 err = -EINVAL; 847 goto setup_exit; 848 } 849 } 850 851 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 852 if (spi->max_speed_hz >= speed) { 853 spi->max_speed_hz = speed; 854 } else { 855 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 856 spi->max_speed_hz); 857 err = -EINVAL; 858 goto setup_exit; 859 } 860 } 861 862 pm_runtime_put(&sdd->pdev->dev); 863 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 864 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 865 return 0; 866 867setup_exit: 868 pm_runtime_put(&sdd->pdev->dev); 869 /* setup() returns with device de-selected */ 870 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 871 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 872 873 if (gpio_is_valid(spi->cs_gpio)) 874 gpio_free(spi->cs_gpio); 875 spi_set_ctldata(spi, NULL); 876 877err_gpio_req: 878 if (spi->dev.of_node) 879 kfree(cs); 880 881 return err; 882} 883 884static void s3c64xx_spi_cleanup(struct spi_device *spi) 885{ 886 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 887 888 if (gpio_is_valid(spi->cs_gpio)) { 889 gpio_free(spi->cs_gpio); 890 if (spi->dev.of_node) 891 kfree(cs); 892 else { 893 /* On non-DT platforms, the SPI core sets 894 * spi->cs_gpio to -ENOENT and .setup() 895 * overrides it with the GPIO pin value 896 * passed using platform data. 897 */ 898 spi->cs_gpio = -ENOENT; 899 } 900 } 901 902 spi_set_ctldata(spi, NULL); 903} 904 905static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 906{ 907 struct s3c64xx_spi_driver_data *sdd = data; 908 struct spi_master *spi = sdd->master; 909 unsigned int val, clr = 0; 910 911 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 912 913 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 914 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 915 dev_err(&spi->dev, "RX overrun\n"); 916 } 917 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 918 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 919 dev_err(&spi->dev, "RX underrun\n"); 920 } 921 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 922 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 923 dev_err(&spi->dev, "TX overrun\n"); 924 } 925 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 926 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 927 dev_err(&spi->dev, "TX underrun\n"); 928 } 929 930 /* Clear the pending irq by setting and then clearing it */ 931 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 932 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 933 934 return IRQ_HANDLED; 935} 936 937static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) 938{ 939 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 940 void __iomem *regs = sdd->regs; 941 unsigned int val; 942 943 sdd->cur_speed = 0; 944 945 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 946 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); 947 948 /* Disable Interrupts - we use Polling if not DMA mode */ 949 writel(0, regs + S3C64XX_SPI_INT_EN); 950 951 if (!sdd->port_conf->clk_from_cmu) 952 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 953 regs + S3C64XX_SPI_CLK_CFG); 954 writel(0, regs + S3C64XX_SPI_MODE_CFG); 955 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 956 957 /* Clear any irq pending bits, should set and clear the bits */ 958 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 959 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 960 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 961 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 962 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 963 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 964 965 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 966 967 val = readl(regs + S3C64XX_SPI_MODE_CFG); 968 val &= ~S3C64XX_SPI_MODE_4BURST; 969 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 970 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 971 writel(val, regs + S3C64XX_SPI_MODE_CFG); 972 973 flush_fifo(sdd); 974} 975 976#ifdef CONFIG_OF 977static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 978{ 979 struct s3c64xx_spi_info *sci; 980 u32 temp; 981 982 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 983 if (!sci) 984 return ERR_PTR(-ENOMEM); 985 986 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 987 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 988 sci->src_clk_nr = 0; 989 } else { 990 sci->src_clk_nr = temp; 991 } 992 993 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 994 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 995 sci->num_cs = 1; 996 } else { 997 sci->num_cs = temp; 998 } 999 1000 return sci; 1001} 1002#else 1003static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1004{ 1005 return dev_get_platdata(dev); 1006} 1007#endif 1008 1009static const struct of_device_id s3c64xx_spi_dt_match[]; 1010 1011static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1012 struct platform_device *pdev) 1013{ 1014#ifdef CONFIG_OF 1015 if (pdev->dev.of_node) { 1016 const struct of_device_id *match; 1017 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); 1018 return (struct s3c64xx_spi_port_config *)match->data; 1019 } 1020#endif 1021 return (struct s3c64xx_spi_port_config *) 1022 platform_get_device_id(pdev)->driver_data; 1023} 1024 1025static int s3c64xx_spi_probe(struct platform_device *pdev) 1026{ 1027 struct resource *mem_res; 1028 struct resource *res; 1029 struct s3c64xx_spi_driver_data *sdd; 1030 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1031 struct spi_master *master; 1032 int ret, irq; 1033 char clk_name[16]; 1034 1035 if (!sci && pdev->dev.of_node) { 1036 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1037 if (IS_ERR(sci)) 1038 return PTR_ERR(sci); 1039 } 1040 1041 if (!sci) { 1042 dev_err(&pdev->dev, "platform_data missing!\n"); 1043 return -ENODEV; 1044 } 1045 1046 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1047 if (mem_res == NULL) { 1048 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1049 return -ENXIO; 1050 } 1051 1052 irq = platform_get_irq(pdev, 0); 1053 if (irq < 0) { 1054 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); 1055 return irq; 1056 } 1057 1058 master = spi_alloc_master(&pdev->dev, 1059 sizeof(struct s3c64xx_spi_driver_data)); 1060 if (master == NULL) { 1061 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1062 return -ENOMEM; 1063 } 1064 1065 platform_set_drvdata(pdev, master); 1066 1067 sdd = spi_master_get_devdata(master); 1068 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1069 sdd->master = master; 1070 sdd->cntrlr_info = sci; 1071 sdd->pdev = pdev; 1072 sdd->sfr_start = mem_res->start; 1073 if (pdev->dev.of_node) { 1074 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1075 if (ret < 0) { 1076 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 1077 ret); 1078 goto err0; 1079 } 1080 sdd->port_id = ret; 1081 } else { 1082 sdd->port_id = pdev->id; 1083 } 1084 1085 sdd->cur_bpw = 8; 1086 1087 if (!sdd->pdev->dev.of_node) { 1088 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1089 if (!res) { 1090 dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n"); 1091 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; 1092 } else 1093 sdd->tx_dma.dmach = res->start; 1094 1095 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1096 if (!res) { 1097 dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n"); 1098 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL; 1099 } else 1100 sdd->rx_dma.dmach = res->start; 1101 } 1102 1103 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1104 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1105 1106 master->dev.of_node = pdev->dev.of_node; 1107 master->bus_num = sdd->port_id; 1108 master->setup = s3c64xx_spi_setup; 1109 master->cleanup = s3c64xx_spi_cleanup; 1110 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1111 master->prepare_message = s3c64xx_spi_prepare_message; 1112 master->transfer_one = s3c64xx_spi_transfer_one; 1113 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1114 master->num_chipselect = sci->num_cs; 1115 master->dma_alignment = 8; 1116 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1117 SPI_BPW_MASK(8); 1118 /* the spi->mode bits understood by this driver: */ 1119 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1120 master->auto_runtime_pm = true; 1121 if (!is_polling(sdd)) 1122 master->can_dma = s3c64xx_spi_can_dma; 1123 1124 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); 1125 if (IS_ERR(sdd->regs)) { 1126 ret = PTR_ERR(sdd->regs); 1127 goto err0; 1128 } 1129 1130 if (sci->cfg_gpio && sci->cfg_gpio()) { 1131 dev_err(&pdev->dev, "Unable to config gpio\n"); 1132 ret = -EBUSY; 1133 goto err0; 1134 } 1135 1136 /* Setup clocks */ 1137 sdd->clk = devm_clk_get(&pdev->dev, "spi"); 1138 if (IS_ERR(sdd->clk)) { 1139 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1140 ret = PTR_ERR(sdd->clk); 1141 goto err0; 1142 } 1143 1144 if (clk_prepare_enable(sdd->clk)) { 1145 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1146 ret = -EBUSY; 1147 goto err0; 1148 } 1149 1150 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1151 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); 1152 if (IS_ERR(sdd->src_clk)) { 1153 dev_err(&pdev->dev, 1154 "Unable to acquire clock '%s'\n", clk_name); 1155 ret = PTR_ERR(sdd->src_clk); 1156 goto err2; 1157 } 1158 1159 if (clk_prepare_enable(sdd->src_clk)) { 1160 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1161 ret = -EBUSY; 1162 goto err2; 1163 } 1164 1165 /* Setup Deufult Mode */ 1166 s3c64xx_spi_hwinit(sdd, sdd->port_id); 1167 1168 spin_lock_init(&sdd->lock); 1169 init_completion(&sdd->xfer_completion); 1170 1171 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1172 "spi-s3c64xx", sdd); 1173 if (ret != 0) { 1174 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1175 irq, ret); 1176 goto err3; 1177 } 1178 1179 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1180 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1181 sdd->regs + S3C64XX_SPI_INT_EN); 1182 1183 pm_runtime_set_active(&pdev->dev); 1184 pm_runtime_enable(&pdev->dev); 1185 1186 ret = devm_spi_register_master(&pdev->dev, master); 1187 if (ret != 0) { 1188 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); 1189 goto err3; 1190 } 1191 1192 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", 1193 sdd->port_id, master->num_chipselect); 1194 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n", 1195 mem_res, 1196 sdd->rx_dma.dmach, sdd->tx_dma.dmach); 1197 1198 return 0; 1199 1200err3: 1201 clk_disable_unprepare(sdd->src_clk); 1202err2: 1203 clk_disable_unprepare(sdd->clk); 1204err0: 1205 spi_master_put(master); 1206 1207 return ret; 1208} 1209 1210static int s3c64xx_spi_remove(struct platform_device *pdev) 1211{ 1212 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1213 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1214 1215 pm_runtime_disable(&pdev->dev); 1216 1217 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1218 1219 clk_disable_unprepare(sdd->src_clk); 1220 1221 clk_disable_unprepare(sdd->clk); 1222 1223 return 0; 1224} 1225 1226#ifdef CONFIG_PM_SLEEP 1227static int s3c64xx_spi_suspend(struct device *dev) 1228{ 1229 struct spi_master *master = dev_get_drvdata(dev); 1230 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1231 1232 int ret = spi_master_suspend(master); 1233 if (ret) 1234 return ret; 1235 1236 if (!pm_runtime_suspended(dev)) { 1237 clk_disable_unprepare(sdd->clk); 1238 clk_disable_unprepare(sdd->src_clk); 1239 } 1240 1241 sdd->cur_speed = 0; /* Output Clock is stopped */ 1242 1243 return 0; 1244} 1245 1246static int s3c64xx_spi_resume(struct device *dev) 1247{ 1248 struct spi_master *master = dev_get_drvdata(dev); 1249 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1250 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1251 1252 if (sci->cfg_gpio) 1253 sci->cfg_gpio(); 1254 1255 if (!pm_runtime_suspended(dev)) { 1256 clk_prepare_enable(sdd->src_clk); 1257 clk_prepare_enable(sdd->clk); 1258 } 1259 1260 s3c64xx_spi_hwinit(sdd, sdd->port_id); 1261 1262 return spi_master_resume(master); 1263} 1264#endif /* CONFIG_PM_SLEEP */ 1265 1266#ifdef CONFIG_PM 1267static int s3c64xx_spi_runtime_suspend(struct device *dev) 1268{ 1269 struct spi_master *master = dev_get_drvdata(dev); 1270 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1271 1272 clk_disable_unprepare(sdd->clk); 1273 clk_disable_unprepare(sdd->src_clk); 1274 1275 return 0; 1276} 1277 1278static int s3c64xx_spi_runtime_resume(struct device *dev) 1279{ 1280 struct spi_master *master = dev_get_drvdata(dev); 1281 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1282 int ret; 1283 1284 ret = clk_prepare_enable(sdd->src_clk); 1285 if (ret != 0) 1286 return ret; 1287 1288 ret = clk_prepare_enable(sdd->clk); 1289 if (ret != 0) { 1290 clk_disable_unprepare(sdd->src_clk); 1291 return ret; 1292 } 1293 1294 return 0; 1295} 1296#endif /* CONFIG_PM */ 1297 1298static const struct dev_pm_ops s3c64xx_spi_pm = { 1299 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1300 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1301 s3c64xx_spi_runtime_resume, NULL) 1302}; 1303 1304static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1305 .fifo_lvl_mask = { 0x7f }, 1306 .rx_lvl_offset = 13, 1307 .tx_st_done = 21, 1308 .high_speed = true, 1309}; 1310 1311static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1312 .fifo_lvl_mask = { 0x7f, 0x7F }, 1313 .rx_lvl_offset = 13, 1314 .tx_st_done = 21, 1315}; 1316 1317static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1318 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1319 .rx_lvl_offset = 15, 1320 .tx_st_done = 25, 1321 .high_speed = true, 1322}; 1323 1324static struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1325 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1326 .rx_lvl_offset = 15, 1327 .tx_st_done = 25, 1328 .high_speed = true, 1329 .clk_from_cmu = true, 1330}; 1331 1332static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { 1333 .fifo_lvl_mask = { 0x1ff }, 1334 .rx_lvl_offset = 15, 1335 .tx_st_done = 25, 1336 .high_speed = true, 1337 .clk_from_cmu = true, 1338 .quirks = S3C64XX_SPI_QUIRK_POLL, 1339}; 1340 1341static struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1342 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1343 .rx_lvl_offset = 15, 1344 .tx_st_done = 25, 1345 .high_speed = true, 1346 .clk_from_cmu = true, 1347 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1348}; 1349 1350static struct platform_device_id s3c64xx_spi_driver_ids[] = { 1351 { 1352 .name = "s3c2443-spi", 1353 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1354 }, { 1355 .name = "s3c6410-spi", 1356 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1357 }, { 1358 .name = "s5pv210-spi", 1359 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, 1360 }, { 1361 .name = "exynos4210-spi", 1362 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, 1363 }, 1364 { }, 1365}; 1366 1367static const struct of_device_id s3c64xx_spi_dt_match[] = { 1368 { .compatible = "samsung,s3c2443-spi", 1369 .data = (void *)&s3c2443_spi_port_config, 1370 }, 1371 { .compatible = "samsung,s3c6410-spi", 1372 .data = (void *)&s3c6410_spi_port_config, 1373 }, 1374 { .compatible = "samsung,s5pv210-spi", 1375 .data = (void *)&s5pv210_spi_port_config, 1376 }, 1377 { .compatible = "samsung,exynos4210-spi", 1378 .data = (void *)&exynos4_spi_port_config, 1379 }, 1380 { .compatible = "samsung,exynos5440-spi", 1381 .data = (void *)&exynos5440_spi_port_config, 1382 }, 1383 { .compatible = "samsung,exynos7-spi", 1384 .data = (void *)&exynos7_spi_port_config, 1385 }, 1386 { }, 1387}; 1388MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1389 1390static struct platform_driver s3c64xx_spi_driver = { 1391 .driver = { 1392 .name = "s3c64xx-spi", 1393 .pm = &s3c64xx_spi_pm, 1394 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1395 }, 1396 .probe = s3c64xx_spi_probe, 1397 .remove = s3c64xx_spi_remove, 1398 .id_table = s3c64xx_spi_driver_ids, 1399}; 1400MODULE_ALIAS("platform:s3c64xx-spi"); 1401 1402module_platform_driver(s3c64xx_spi_driver); 1403 1404MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1405MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1406MODULE_LICENSE("GPL"); 1407