231 	writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);  in spear_smi_read_sr()
234 	writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,  in spear_smi_read_sr()
248 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_read_sr()
249 	writel(0, dev->io_base + SMI_CR2);  in spear_smi_read_sr()
307 	writel(0, dev->io_base + SMI_SR);  in spear_smi_int_handler()
343 	writel(0, dev->io_base + SMI_SR);  in spear_smi_hw_init()
345 	writel(val, dev->io_base + SMI_CR1);  in spear_smi_hw_init()
389 	writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_write_enable()
392 	writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);  in spear_smi_write_enable()
398 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_write_enable()
399 	writel(0, dev->io_base + SMI_CR2);  in spear_smi_write_enable()
461 	writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);  in spear_smi_erase_sector()
464 	writel(command, dev->io_base + SMI_TR);  in spear_smi_erase_sector()
466 	writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),  in spear_smi_erase_sector()
479 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_erase_sector()
480 	writel(0, dev->io_base + SMI_CR2);  in spear_smi_erase_sector()
584 	writel(val, dev->io_base + SMI_CR1);  in spear_mtd_read()
589 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_mtd_read()
618 	writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_cpy_toio()
622 	writel(ctrlreg1, dev->io_base + SMI_CR1);  in spear_smi_cpy_toio()
726 	writel(val | SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_probe_flash()
729 	writel(OPCODE_RDID, dev->io_base + SMI_TR);  in spear_smi_probe_flash()
733 	writel(val, dev->io_base + SMI_CR2);  in spear_smi_probe_flash()
751 	writel(val & ~SW_MODE, dev->io_base + SMI_CR1);  in spear_smi_probe_flash()